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drm/amd/display: updated wm table for Renoir
[ Upstream commit 410066d24c
]
[Why]
For certain timings, Renoir may underflow due to sr exit
latency being too slow.
[How]
Updated wm table for renoir.
Signed-off-by: Jake Wang <haonan.wang2@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
parent
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commit
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1 changed files with 6 additions and 6 deletions
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@ -704,24 +704,24 @@ static struct wm_table ddr4_wm_table_rn = {
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.wm_inst = WM_B,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 10.12,
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.sr_enter_plus_exit_time_us = 11.48,
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.sr_exit_time_us = 11.12,
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.sr_enter_plus_exit_time_us = 12.48,
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.valid = true,
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},
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{
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.wm_inst = WM_C,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 10.12,
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.sr_enter_plus_exit_time_us = 11.48,
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.sr_exit_time_us = 11.12,
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.sr_enter_plus_exit_time_us = 12.48,
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.valid = true,
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},
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{
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.wm_inst = WM_D,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 10.12,
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.sr_enter_plus_exit_time_us = 11.48,
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.sr_exit_time_us = 11.12,
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.sr_enter_plus_exit_time_us = 12.48,
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.valid = true,
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},
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}
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