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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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Merge branch 'remotes/lorenzo/pci/mvebu'
- Add Pali Rohár as pci-mvebu.c maintainer (Pali Rohár) - Make struct pci_bridge_emul_ops const (Pali Rohár) - Rename PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR to PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD since it doesn't apply to BARs (Pali Rohár) - Add new flag PCI_BRIDGE_EMUL_NO_IO_FORWARD for bridges that don't support IO forwarding (Pali Rohár) - Add Kconfig help text for CONFIG_PCI_MVEBU (Pali Rohár) - Remove duplicate nports assignment (Pali Rohár) - Set PCI_BRIDGE_EMUL_NO_IO_FORWARD when IO is unsupported (Pali Rohár) - Initialize vendor, device and revision of emulated bridge (Pali Rohár) - Fix Data Link Layer Link Active reporting on emulated bridge (Pali Rohár) - Rearrange tests in bridge emulation for easier maintenance (Russell King) - Add emulated bridge support for PCIe extended capabilities (Russell King) - Add emulated bridge support for bridge Subsystem Vendor ID capability (Pali Rohár) - Configure Maximum Link Width based on DT "num-lanes" property (Pali Rohár) - Emulate bridge Subsystem Vendor ID capability (Pali Rohár) - Emulate AER Capability (Pali Rohár) - Use PCI core bridge->ops and bridge->child_ops to separate config accesses to Root Port vs downstream devices (Pali Rohár) - Unmask all INTx interrupts; they're reported via a single shared GIC source (Pali Rohár) - Add INTx support (Pali Rohár) * remotes/lorenzo/pci/mvebu: PCI: mvebu: Implement support for legacy INTx interrupts PCI: mvebu: Fix macro names and comments about legacy interrupts dt-bindings: PCI: mvebu: Update information about intx interrupts PCI: mvebu: Use child_ops API PCI: mvebu: Add support for Advanced Error Reporting registers on emulated bridge PCI: mvebu: Add support for PCI Bridge Subsystem Vendor ID on emulated bridge PCI: mvebu: Correctly configure x1/x4 mode dt-bindings: PCI: mvebu: Add num-lanes property PCI: pci-bridge-emul: Add support for PCI Bridge Subsystem Vendor ID capability PCI: pci-bridge-emul: Add support for PCIe extended capabilities PCI: pci-bridge-emul: Re-arrange register tests PCI: mvebu: Fix reporting Data Link Layer Link Active on emulated bridge PCI: mvebu: Update comment for PCI_EXP_LNKCTL register on emulated bridge PCI: mvebu: Update comment for PCI_EXP_LNKCAP register on emulated bridge PCI: mvebu: Properly initialize vendor, device and revision of emulated bridge PCI: mvebu: Set PCI_BRIDGE_EMUL_NO_IO_FORWARD when IO is unsupported PCI: mvebu: Remove duplicate nports assignment PCI: mvebu: Add help string for CONFIG_PCI_MVEBU option PCI: pci-bridge-emul: Add support for new flag PCI_BRIDGE_EMUL_NO_IO_FORWARD PCI: pci-bridge-emul: Rename PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR to PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD PCI: pci-bridge-emul: Make struct pci_bridge_emul_ops as const MAINTAINERS: Add Pali Rohár as pci-mvebu.c maintainer
This commit is contained in:
Bjorn Helgaas
commit
9b2c25fa12
7 changed files with 506 additions and 140 deletions
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@ -77,9 +77,15 @@ and the following optional properties:
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- marvell,pcie-lane: the physical PCIe lane number, for ports having
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multiple lanes. If this property is not found, we assume that the
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value is 0.
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- num-lanes: number of SerDes PCIe lanes for this link (1 or 4)
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- reset-gpios: optional GPIO to PERST#
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- reset-delay-us: delay in us to wait after reset de-assertion, if not
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specified will default to 100ms, as required by the PCIe specification.
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- interrupt-names: list of interrupt names, supported are:
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- "intx" - interrupt line triggered by one of the legacy interrupt
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- interrupts or interrupts-extended: List of the interrupt sources which
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corresponding to the "interrupt-names". If non-empty then also additional
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'interrupt-controller' subnode must be defined.
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Example:
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@ -141,6 +147,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 58>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <0>;
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num-lanes = <1>;
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/* low-active PERST# reset on GPIO 25 */
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reset-gpios = <&gpio0 25 1>;
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/* wait 20ms for device settle after reset deassertion */
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@ -161,6 +168,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 59>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <1>;
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num-lanes = <1>;
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clocks = <&gateclk 6>;
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};
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@ -177,6 +185,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 60>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <2>;
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num-lanes = <1>;
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clocks = <&gateclk 7>;
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};
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@ -193,6 +202,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 61>;
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marvell,pcie-port = <0>;
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marvell,pcie-lane = <3>;
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num-lanes = <1>;
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clocks = <&gateclk 8>;
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};
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@ -209,6 +219,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 62>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <0>;
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num-lanes = <1>;
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clocks = <&gateclk 9>;
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};
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@ -225,6 +236,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 63>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <1>;
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num-lanes = <1>;
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clocks = <&gateclk 10>;
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};
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@ -241,6 +253,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 64>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <2>;
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num-lanes = <1>;
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clocks = <&gateclk 11>;
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};
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@ -257,6 +270,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 65>;
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marvell,pcie-port = <1>;
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marvell,pcie-lane = <3>;
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num-lanes = <1>;
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clocks = <&gateclk 12>;
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};
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@ -273,6 +287,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 99>;
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marvell,pcie-port = <2>;
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marvell,pcie-lane = <0>;
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num-lanes = <1>;
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clocks = <&gateclk 26>;
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};
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@ -289,6 +304,7 @@ pcie-controller {
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interrupt-map = <0 0 0 0 &mpic 103>;
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marvell,pcie-port = <3>;
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marvell,pcie-lane = <0>;
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num-lanes = <1>;
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clocks = <&gateclk 27>;
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};
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};
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@ -14784,6 +14784,7 @@ F: drivers/pci/controller/mobiveil/pcie-mobiveil*
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PCI DRIVER FOR MVEBU (Marvell Armada 370 and Armada XP SOC support)
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M: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
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M: Pali Rohár <pali@kernel.org>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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@ -10,6 +10,10 @@ config PCI_MVEBU
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depends on ARM
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depends on OF
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select PCI_BRIDGE_EMUL
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help
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Add support for Marvell EBU PCIe controller. This PCIe controller
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is used on 32-bit Marvell ARM SoCs: Dove, Kirkwood, Armada 370,
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Armada XP, Armada 375, Armada 38x and Armada 39x.
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config PCI_AARDVARK
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tristate "Aardvark PCIe controller"
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@ -945,7 +945,7 @@ advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
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}
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}
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static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
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static const struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
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.read_base = advk_pci_bridge_emul_base_conf_read,
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.write_base = advk_pci_bridge_emul_base_conf_write,
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.read_pcie = advk_pci_bridge_emul_pcie_conf_read,
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@ -32,8 +32,9 @@
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#define PCIE_DEV_REV_OFF 0x0008
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#define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
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#define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
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#define PCIE_SSDEV_ID_OFF 0x002c
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#define PCIE_CAP_PCIEXP 0x0060
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#define PCIE_HEADER_LOG_4_OFF 0x0128
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#define PCIE_CAP_PCIERR_OFF 0x0100
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#define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
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#define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
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#define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
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@ -53,9 +54,10 @@
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PCIE_CONF_ADDR_EN)
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#define PCIE_CONF_DATA_OFF 0x18fc
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#define PCIE_INT_CAUSE_OFF 0x1900
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#define PCIE_INT_UNMASK_OFF 0x1910
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#define PCIE_INT_INTX(i) BIT(24+i)
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#define PCIE_INT_PM_PME BIT(28)
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#define PCIE_MASK_OFF 0x1910
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#define PCIE_MASK_ENABLE_INTS 0x0f000000
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#define PCIE_INT_ALL_MASK GENMASK(31, 0)
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#define PCIE_CTRL_OFF 0x1a00
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#define PCIE_CTRL_X1_MODE 0x0001
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#define PCIE_CTRL_RC_MODE BIT(1)
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@ -93,6 +95,7 @@ struct mvebu_pcie_port {
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void __iomem *base;
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u32 port;
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u32 lane;
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bool is_x4;
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int devfn;
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unsigned int mem_target;
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unsigned int mem_attr;
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@ -108,6 +111,9 @@ struct mvebu_pcie_port {
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struct mvebu_pcie_window iowin;
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u32 saved_pcie_stat;
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struct resource regs;
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struct irq_domain *intx_irq_domain;
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raw_spinlock_t irq_lock;
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int intx_irq;
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};
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static inline void mvebu_writel(struct mvebu_pcie_port *port, u32 val, u32 reg)
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@ -233,13 +239,25 @@ static void mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
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static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
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{
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u32 ctrl, cmd, dev_rev, mask;
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u32 ctrl, lnkcap, cmd, dev_rev, unmask;
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/* Setup PCIe controller to Root Complex mode. */
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ctrl = mvebu_readl(port, PCIE_CTRL_OFF);
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ctrl |= PCIE_CTRL_RC_MODE;
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mvebu_writel(port, ctrl, PCIE_CTRL_OFF);
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/*
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* Set Maximum Link Width to X1 or X4 in Root Port's PCIe Link
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* Capability register. This register is defined by PCIe specification
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* as read-only but this mvebu controller has it as read-write and must
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* be set to number of SerDes PCIe lanes (1 or 4). If this register is
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* not set correctly then link with endpoint card is not established.
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*/
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lnkcap = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
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lnkcap &= ~PCI_EXP_LNKCAP_MLW;
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lnkcap |= (port->is_x4 ? 4 : 1) << 4;
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mvebu_writel(port, lnkcap, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP);
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/* Disable Root Bridge I/O space, memory space and bus mastering. */
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cmd = mvebu_readl(port, PCIE_CMD_OFF);
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cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
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@ -274,17 +292,51 @@ static void mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
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/* Point PCIe unit MBUS decode windows to DRAM space. */
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mvebu_pcie_setup_wins(port);
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/* Enable interrupt lines A-D. */
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mask = mvebu_readl(port, PCIE_MASK_OFF);
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mask |= PCIE_MASK_ENABLE_INTS;
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mvebu_writel(port, mask, PCIE_MASK_OFF);
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/* Mask all interrupt sources. */
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mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
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/* Clear all interrupt causes. */
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mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
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/* Check if "intx" interrupt was specified in DT. */
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if (port->intx_irq > 0)
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return;
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/*
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* Fallback code when "intx" interrupt was not specified in DT:
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* Unmask all legacy INTx interrupts as driver does not provide a way
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* for masking and unmasking of individual legacy INTx interrupts.
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* Legacy INTx are reported via one shared GIC source and therefore
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* kernel cannot distinguish which individual legacy INTx was triggered.
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* These interrupts are shared, so it should not cause any issue. Just
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* performance penalty as every PCIe interrupt handler needs to be
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* called when some interrupt is triggered.
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*/
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unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
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unmask |= PCIE_INT_INTX(0) | PCIE_INT_INTX(1) |
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PCIE_INT_INTX(2) | PCIE_INT_INTX(3);
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mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
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}
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static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
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struct pci_bus *bus,
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u32 devfn, int where, int size, u32 *val)
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static struct mvebu_pcie_port *mvebu_pcie_find_port(struct mvebu_pcie *pcie,
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struct pci_bus *bus,
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int devfn);
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static int mvebu_pcie_child_rd_conf(struct pci_bus *bus, u32 devfn, int where,
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int size, u32 *val)
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{
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void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
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struct mvebu_pcie *pcie = bus->sysdata;
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struct mvebu_pcie_port *port;
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void __iomem *conf_data;
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port = mvebu_pcie_find_port(pcie, bus, devfn);
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if (!port)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (!mvebu_pcie_link_up(port))
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return PCIBIOS_DEVICE_NOT_FOUND;
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conf_data = port->base + PCIE_CONF_DATA_OFF;
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mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
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PCIE_CONF_ADDR_OFF);
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@ -300,18 +352,27 @@ static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
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*val = readl_relaxed(conf_data);
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break;
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default:
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*val = 0xffffffff;
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return PCIBIOS_BAD_REGISTER_NUMBER;
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}
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return PCIBIOS_SUCCESSFUL;
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}
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static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
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struct pci_bus *bus,
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u32 devfn, int where, int size, u32 val)
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static int mvebu_pcie_child_wr_conf(struct pci_bus *bus, u32 devfn,
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int where, int size, u32 val)
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{
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void __iomem *conf_data = port->base + PCIE_CONF_DATA_OFF;
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struct mvebu_pcie *pcie = bus->sysdata;
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struct mvebu_pcie_port *port;
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void __iomem *conf_data;
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port = mvebu_pcie_find_port(pcie, bus, devfn);
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if (!port)
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return PCIBIOS_DEVICE_NOT_FOUND;
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if (!mvebu_pcie_link_up(port))
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return PCIBIOS_DEVICE_NOT_FOUND;
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conf_data = port->base + PCIE_CONF_DATA_OFF;
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mvebu_writel(port, PCIE_CONF_ADDR(bus->number, devfn, where),
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PCIE_CONF_ADDR_OFF);
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@ -333,6 +394,11 @@ static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
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return PCIBIOS_SUCCESSFUL;
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}
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static struct pci_ops mvebu_pcie_child_ops = {
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.read = mvebu_pcie_child_rd_conf,
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.write = mvebu_pcie_child_wr_conf,
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};
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/*
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* Remove windows, starting from the largest ones to the smallest
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* ones.
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@ -438,12 +504,6 @@ static int mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
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return mvebu_pcie_set_window(port, port->io_target, port->io_attr,
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&desired, &port->iowin);
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if (!mvebu_has_ioport(port)) {
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dev_WARN(&port->pcie->pdev->dev,
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"Attempt to set IO when IO is disabled\n");
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return -EOPNOTSUPP;
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}
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/*
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* We read the PCI-to-PCI bridge emulated registers, and
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* calculate the base address and size of the address decoding
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@ -552,15 +612,20 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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case PCI_EXP_LNKCAP:
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/*
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* PCIe requires the clock power management capability to be
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* hard-wired to zero for downstream ports
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* PCIe requires that the Clock Power Management capability bit
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* is hard-wired to zero for downstream ports but HW returns 1.
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* Additionally enable Data Link Layer Link Active Reporting
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* Capable bit as DL_Active indication is provided too.
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*/
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*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
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~PCI_EXP_LNKCAP_CLKPM;
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*value = (mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCAP) &
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~PCI_EXP_LNKCAP_CLKPM) | PCI_EXP_LNKCAP_DLLLARC;
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break;
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case PCI_EXP_LNKCTL:
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*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL);
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/* DL_Active indication is provided via PCIE_STAT_OFF */
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*value = mvebu_readl(port, PCIE_CAP_PCIEXP + PCI_EXP_LNKCTL) |
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(mvebu_pcie_link_up(port) ?
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(PCI_EXP_LNKSTA_DLLLA << 16) : 0);
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break;
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case PCI_EXP_SLTCTL:
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|
@ -590,6 +655,37 @@ mvebu_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
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return PCI_BRIDGE_EMUL_HANDLED;
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}
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static pci_bridge_emul_read_status_t
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mvebu_pci_bridge_emul_ext_conf_read(struct pci_bridge_emul *bridge,
|
||||
int reg, u32 *value)
|
||||
{
|
||||
struct mvebu_pcie_port *port = bridge->data;
|
||||
|
||||
switch (reg) {
|
||||
case 0:
|
||||
case PCI_ERR_UNCOR_STATUS:
|
||||
case PCI_ERR_UNCOR_MASK:
|
||||
case PCI_ERR_UNCOR_SEVER:
|
||||
case PCI_ERR_COR_STATUS:
|
||||
case PCI_ERR_COR_MASK:
|
||||
case PCI_ERR_CAP:
|
||||
case PCI_ERR_HEADER_LOG+0:
|
||||
case PCI_ERR_HEADER_LOG+4:
|
||||
case PCI_ERR_HEADER_LOG+8:
|
||||
case PCI_ERR_HEADER_LOG+12:
|
||||
case PCI_ERR_ROOT_COMMAND:
|
||||
case PCI_ERR_ROOT_STATUS:
|
||||
case PCI_ERR_ROOT_ERR_SRC:
|
||||
*value = mvebu_readl(port, PCIE_CAP_PCIERR_OFF + reg);
|
||||
break;
|
||||
|
||||
default:
|
||||
return PCI_BRIDGE_EMUL_NOT_HANDLED;
|
||||
}
|
||||
|
||||
return PCI_BRIDGE_EMUL_HANDLED;
|
||||
}
|
||||
|
||||
static void
|
||||
mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
|
||||
int reg, u32 old, u32 new, u32 mask)
|
||||
|
|
@ -599,24 +695,18 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
|
|||
|
||||
switch (reg) {
|
||||
case PCI_COMMAND:
|
||||
if (!mvebu_has_ioport(port)) {
|
||||
conf->command = cpu_to_le16(
|
||||
le16_to_cpu(conf->command) & ~PCI_COMMAND_IO);
|
||||
new &= ~PCI_COMMAND_IO;
|
||||
}
|
||||
|
||||
mvebu_writel(port, new, PCIE_CMD_OFF);
|
||||
break;
|
||||
|
||||
case PCI_IO_BASE:
|
||||
if ((mask & 0xffff) && mvebu_pcie_handle_iobase_change(port)) {
|
||||
if ((mask & 0xffff) && mvebu_has_ioport(port) &&
|
||||
mvebu_pcie_handle_iobase_change(port)) {
|
||||
/* On error disable IO range */
|
||||
conf->iobase &= ~0xf0;
|
||||
conf->iolimit &= ~0xf0;
|
||||
conf->iobase |= 0xf0;
|
||||
conf->iobaseupper = cpu_to_le16(0x0000);
|
||||
conf->iolimitupper = cpu_to_le16(0x0000);
|
||||
if (mvebu_has_ioport(port))
|
||||
conf->iobase |= 0xf0;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -630,14 +720,14 @@ mvebu_pci_bridge_emul_base_conf_write(struct pci_bridge_emul *bridge,
|
|||
break;
|
||||
|
||||
case PCI_IO_BASE_UPPER16:
|
||||
if (mvebu_pcie_handle_iobase_change(port)) {
|
||||
if (mvebu_has_ioport(port) &&
|
||||
mvebu_pcie_handle_iobase_change(port)) {
|
||||
/* On error disable IO range */
|
||||
conf->iobase &= ~0xf0;
|
||||
conf->iolimit &= ~0xf0;
|
||||
conf->iobase |= 0xf0;
|
||||
conf->iobaseupper = cpu_to_le16(0x0000);
|
||||
conf->iolimitupper = cpu_to_le16(0x0000);
|
||||
if (mvebu_has_ioport(port))
|
||||
conf->iobase |= 0xf0;
|
||||
}
|
||||
break;
|
||||
|
||||
|
|
@ -675,10 +765,9 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
|
|||
|
||||
case PCI_EXP_LNKCTL:
|
||||
/*
|
||||
* If we don't support CLKREQ, we must ensure that the
|
||||
* CLKREQ enable bit always reads zero. Since we haven't
|
||||
* had this capability, and it's dependent on board wiring,
|
||||
* disable it for the time being.
|
||||
* PCIe requires that the Enable Clock Power Management bit
|
||||
* is hard-wired to zero for downstream ports but HW allows
|
||||
* to change it.
|
||||
*/
|
||||
new &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
|
||||
|
||||
|
|
@ -709,11 +798,45 @@ mvebu_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
|
|||
}
|
||||
}
|
||||
|
||||
static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
|
||||
static void
|
||||
mvebu_pci_bridge_emul_ext_conf_write(struct pci_bridge_emul *bridge,
|
||||
int reg, u32 old, u32 new, u32 mask)
|
||||
{
|
||||
struct mvebu_pcie_port *port = bridge->data;
|
||||
|
||||
switch (reg) {
|
||||
/* These are W1C registers, so clear other bits */
|
||||
case PCI_ERR_UNCOR_STATUS:
|
||||
case PCI_ERR_COR_STATUS:
|
||||
case PCI_ERR_ROOT_STATUS:
|
||||
new &= mask;
|
||||
fallthrough;
|
||||
|
||||
case PCI_ERR_UNCOR_MASK:
|
||||
case PCI_ERR_UNCOR_SEVER:
|
||||
case PCI_ERR_COR_MASK:
|
||||
case PCI_ERR_CAP:
|
||||
case PCI_ERR_HEADER_LOG+0:
|
||||
case PCI_ERR_HEADER_LOG+4:
|
||||
case PCI_ERR_HEADER_LOG+8:
|
||||
case PCI_ERR_HEADER_LOG+12:
|
||||
case PCI_ERR_ROOT_COMMAND:
|
||||
case PCI_ERR_ROOT_ERR_SRC:
|
||||
mvebu_writel(port, new, PCIE_CAP_PCIERR_OFF + reg);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static const struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
|
||||
.read_base = mvebu_pci_bridge_emul_base_conf_read,
|
||||
.write_base = mvebu_pci_bridge_emul_base_conf_write,
|
||||
.read_pcie = mvebu_pci_bridge_emul_pcie_conf_read,
|
||||
.write_pcie = mvebu_pci_bridge_emul_pcie_conf_write,
|
||||
.read_ext = mvebu_pci_bridge_emul_ext_conf_read,
|
||||
.write_ext = mvebu_pci_bridge_emul_ext_conf_write,
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -722,19 +845,24 @@ static struct pci_bridge_emul_ops mvebu_pci_bridge_emul_ops = {
|
|||
*/
|
||||
static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
|
||||
{
|
||||
unsigned int bridge_flags = PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD;
|
||||
struct pci_bridge_emul *bridge = &port->bridge;
|
||||
u32 dev_id = mvebu_readl(port, PCIE_DEV_ID_OFF);
|
||||
u32 dev_rev = mvebu_readl(port, PCIE_DEV_REV_OFF);
|
||||
u32 ssdev_id = mvebu_readl(port, PCIE_SSDEV_ID_OFF);
|
||||
u32 pcie_cap = mvebu_readl(port, PCIE_CAP_PCIEXP);
|
||||
u8 pcie_cap_ver = ((pcie_cap >> 16) & PCI_EXP_FLAGS_VERS);
|
||||
|
||||
bridge->conf.vendor = PCI_VENDOR_ID_MARVELL;
|
||||
bridge->conf.device = mvebu_readl(port, PCIE_DEV_ID_OFF) >> 16;
|
||||
bridge->conf.class_revision =
|
||||
mvebu_readl(port, PCIE_DEV_REV_OFF) & 0xff;
|
||||
bridge->conf.vendor = cpu_to_le16(dev_id & 0xffff);
|
||||
bridge->conf.device = cpu_to_le16(dev_id >> 16);
|
||||
bridge->conf.class_revision = cpu_to_le32(dev_rev & 0xff);
|
||||
|
||||
if (mvebu_has_ioport(port)) {
|
||||
/* We support 32 bits I/O addressing */
|
||||
bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
|
||||
bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
|
||||
} else {
|
||||
bridge_flags |= PCI_BRIDGE_EMUL_NO_IO_FORWARD;
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -743,11 +871,13 @@ static int mvebu_pci_bridge_emul_init(struct mvebu_pcie_port *port)
|
|||
*/
|
||||
bridge->pcie_conf.cap = cpu_to_le16(pcie_cap_ver);
|
||||
|
||||
bridge->subsystem_vendor_id = ssdev_id & 0xffff;
|
||||
bridge->subsystem_id = ssdev_id >> 16;
|
||||
bridge->has_pcie = true;
|
||||
bridge->data = port;
|
||||
bridge->ops = &mvebu_pci_bridge_emul_ops;
|
||||
|
||||
return pci_bridge_emul_init(bridge, PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR);
|
||||
return pci_bridge_emul_init(bridge, bridge_flags);
|
||||
}
|
||||
|
||||
static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
|
||||
|
|
@ -784,25 +914,12 @@ static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
|
|||
{
|
||||
struct mvebu_pcie *pcie = bus->sysdata;
|
||||
struct mvebu_pcie_port *port;
|
||||
int ret;
|
||||
|
||||
port = mvebu_pcie_find_port(pcie, bus, devfn);
|
||||
if (!port)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
/* Access the emulated PCI-to-PCI bridge */
|
||||
if (bus->number == 0)
|
||||
return pci_bridge_emul_conf_write(&port->bridge, where,
|
||||
size, val);
|
||||
|
||||
if (!mvebu_pcie_link_up(port))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
/* Access the real PCIe interface */
|
||||
ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
|
||||
where, size, val);
|
||||
|
||||
return ret;
|
||||
return pci_bridge_emul_conf_write(&port->bridge, where, size, val);
|
||||
}
|
||||
|
||||
/* PCI configuration space read function */
|
||||
|
|
@ -811,25 +928,12 @@ static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
|
|||
{
|
||||
struct mvebu_pcie *pcie = bus->sysdata;
|
||||
struct mvebu_pcie_port *port;
|
||||
int ret;
|
||||
|
||||
port = mvebu_pcie_find_port(pcie, bus, devfn);
|
||||
if (!port)
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
/* Access the emulated PCI-to-PCI bridge */
|
||||
if (bus->number == 0)
|
||||
return pci_bridge_emul_conf_read(&port->bridge, where,
|
||||
size, val);
|
||||
|
||||
if (!mvebu_pcie_link_up(port))
|
||||
return PCIBIOS_DEVICE_NOT_FOUND;
|
||||
|
||||
/* Access the real PCIe interface */
|
||||
ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
|
||||
where, size, val);
|
||||
|
||||
return ret;
|
||||
return pci_bridge_emul_conf_read(&port->bridge, where, size, val);
|
||||
}
|
||||
|
||||
static struct pci_ops mvebu_pcie_ops = {
|
||||
|
|
@ -837,6 +941,108 @@ static struct pci_ops mvebu_pcie_ops = {
|
|||
.write = mvebu_pcie_wr_conf,
|
||||
};
|
||||
|
||||
static void mvebu_pcie_intx_irq_mask(struct irq_data *d)
|
||||
{
|
||||
struct mvebu_pcie_port *port = d->domain->host_data;
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
unsigned long flags;
|
||||
u32 unmask;
|
||||
|
||||
raw_spin_lock_irqsave(&port->irq_lock, flags);
|
||||
unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
|
||||
unmask &= ~PCIE_INT_INTX(hwirq);
|
||||
mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
|
||||
raw_spin_unlock_irqrestore(&port->irq_lock, flags);
|
||||
}
|
||||
|
||||
static void mvebu_pcie_intx_irq_unmask(struct irq_data *d)
|
||||
{
|
||||
struct mvebu_pcie_port *port = d->domain->host_data;
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
unsigned long flags;
|
||||
u32 unmask;
|
||||
|
||||
raw_spin_lock_irqsave(&port->irq_lock, flags);
|
||||
unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
|
||||
unmask |= PCIE_INT_INTX(hwirq);
|
||||
mvebu_writel(port, unmask, PCIE_INT_UNMASK_OFF);
|
||||
raw_spin_unlock_irqrestore(&port->irq_lock, flags);
|
||||
}
|
||||
|
||||
static struct irq_chip intx_irq_chip = {
|
||||
.name = "mvebu-INTx",
|
||||
.irq_mask = mvebu_pcie_intx_irq_mask,
|
||||
.irq_unmask = mvebu_pcie_intx_irq_unmask,
|
||||
};
|
||||
|
||||
static int mvebu_pcie_intx_irq_map(struct irq_domain *h,
|
||||
unsigned int virq, irq_hw_number_t hwirq)
|
||||
{
|
||||
struct mvebu_pcie_port *port = h->host_data;
|
||||
|
||||
irq_set_status_flags(virq, IRQ_LEVEL);
|
||||
irq_set_chip_and_handler(virq, &intx_irq_chip, handle_level_irq);
|
||||
irq_set_chip_data(virq, port);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_domain_ops mvebu_pcie_intx_irq_domain_ops = {
|
||||
.map = mvebu_pcie_intx_irq_map,
|
||||
.xlate = irq_domain_xlate_onecell,
|
||||
};
|
||||
|
||||
static int mvebu_pcie_init_irq_domain(struct mvebu_pcie_port *port)
|
||||
{
|
||||
struct device *dev = &port->pcie->pdev->dev;
|
||||
struct device_node *pcie_intc_node;
|
||||
|
||||
raw_spin_lock_init(&port->irq_lock);
|
||||
|
||||
pcie_intc_node = of_get_next_child(port->dn, NULL);
|
||||
if (!pcie_intc_node) {
|
||||
dev_err(dev, "No PCIe Intc node found for %s\n", port->name);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
port->intx_irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
|
||||
&mvebu_pcie_intx_irq_domain_ops,
|
||||
port);
|
||||
of_node_put(pcie_intc_node);
|
||||
if (!port->intx_irq_domain) {
|
||||
dev_err(dev, "Failed to get INTx IRQ domain for %s\n", port->name);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mvebu_pcie_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct mvebu_pcie_port *port = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
struct device *dev = &port->pcie->pdev->dev;
|
||||
u32 cause, unmask, status;
|
||||
int i;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
cause = mvebu_readl(port, PCIE_INT_CAUSE_OFF);
|
||||
unmask = mvebu_readl(port, PCIE_INT_UNMASK_OFF);
|
||||
status = cause & unmask;
|
||||
|
||||
/* Process legacy INTx interrupts */
|
||||
for (i = 0; i < PCI_NUM_INTX; i++) {
|
||||
if (!(status & PCIE_INT_INTX(i)))
|
||||
continue;
|
||||
|
||||
if (generic_handle_domain_irq(port->intx_irq_domain, i) == -EINVAL)
|
||||
dev_err_ratelimited(dev, "unexpected INT%c IRQ\n", (char)i+'A');
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static int mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
|
||||
{
|
||||
/* Interrupt support on mvebu emulated bridges is not implemented yet */
|
||||
|
|
@ -986,6 +1192,7 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
|
|||
struct device *dev = &pcie->pdev->dev;
|
||||
enum of_gpio_flags flags;
|
||||
int reset_gpio, ret;
|
||||
u32 num_lanes;
|
||||
|
||||
port->pcie = pcie;
|
||||
|
||||
|
|
@ -998,6 +1205,9 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
|
|||
if (of_property_read_u32(child, "marvell,pcie-lane", &port->lane))
|
||||
port->lane = 0;
|
||||
|
||||
if (!of_property_read_u32(child, "num-lanes", &num_lanes) && num_lanes == 4)
|
||||
port->is_x4 = true;
|
||||
|
||||
port->name = devm_kasprintf(dev, GFP_KERNEL, "pcie%d.%d", port->port,
|
||||
port->lane);
|
||||
if (!port->name) {
|
||||
|
|
@ -1030,6 +1240,21 @@ static int mvebu_pcie_parse_port(struct mvebu_pcie *pcie,
|
|||
port->io_attr = -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Old DT bindings do not contain "intx" interrupt
|
||||
* so do not fail probing driver when interrupt does not exist.
|
||||
*/
|
||||
port->intx_irq = of_irq_get_byname(child, "intx");
|
||||
if (port->intx_irq == -EPROBE_DEFER) {
|
||||
ret = port->intx_irq;
|
||||
goto err;
|
||||
}
|
||||
if (port->intx_irq <= 0) {
|
||||
dev_warn(dev, "%s: legacy INTx interrupts cannot be masked individually, "
|
||||
"%pOF does not contain intx interrupt\n",
|
||||
port->name, child);
|
||||
}
|
||||
|
||||
reset_gpio = of_get_named_gpio_flags(child, "reset-gpios", 0, &flags);
|
||||
if (reset_gpio == -EPROBE_DEFER) {
|
||||
ret = reset_gpio;
|
||||
|
|
@ -1226,6 +1451,7 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
|
|||
|
||||
for (i = 0; i < pcie->nports; i++) {
|
||||
struct mvebu_pcie_port *port = &pcie->ports[i];
|
||||
int irq = port->intx_irq;
|
||||
|
||||
child = port->dn;
|
||||
if (!child)
|
||||
|
|
@ -1253,6 +1479,22 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
|
|||
continue;
|
||||
}
|
||||
|
||||
if (irq > 0) {
|
||||
ret = mvebu_pcie_init_irq_domain(port);
|
||||
if (ret) {
|
||||
dev_err(dev, "%s: cannot init irq domain\n",
|
||||
port->name);
|
||||
pci_bridge_emul_cleanup(&port->bridge);
|
||||
devm_iounmap(dev, port->base);
|
||||
port->base = NULL;
|
||||
mvebu_pcie_powerdown(port);
|
||||
continue;
|
||||
}
|
||||
irq_set_chained_handler_and_data(irq,
|
||||
mvebu_pcie_irq_handler,
|
||||
port);
|
||||
}
|
||||
|
||||
/*
|
||||
* PCIe topology exported by mvebu hw is quite complicated. In
|
||||
* reality has something like N fully independent host bridges
|
||||
|
|
@ -1332,10 +1574,9 @@ static int mvebu_pcie_probe(struct platform_device *pdev)
|
|||
mvebu_pcie_set_local_dev_nr(port, 0);
|
||||
}
|
||||
|
||||
pcie->nports = i;
|
||||
|
||||
bridge->sysdata = pcie;
|
||||
bridge->ops = &mvebu_pcie_ops;
|
||||
bridge->child_ops = &mvebu_pcie_child_ops;
|
||||
bridge->align_resource = mvebu_pcie_align_resource;
|
||||
bridge->map_irq = mvebu_pcie_map_irq;
|
||||
|
||||
|
|
@ -1357,6 +1598,7 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
|
|||
|
||||
for (i = 0; i < pcie->nports; i++) {
|
||||
struct mvebu_pcie_port *port = &pcie->ports[i];
|
||||
int irq = port->intx_irq;
|
||||
|
||||
if (!port->base)
|
||||
continue;
|
||||
|
|
@ -1367,7 +1609,17 @@ static int mvebu_pcie_remove(struct platform_device *pdev)
|
|||
mvebu_writel(port, cmd, PCIE_CMD_OFF);
|
||||
|
||||
/* Mask all interrupt sources. */
|
||||
mvebu_writel(port, 0, PCIE_MASK_OFF);
|
||||
mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_UNMASK_OFF);
|
||||
|
||||
/* Clear all interrupt causes. */
|
||||
mvebu_writel(port, ~PCIE_INT_ALL_MASK, PCIE_INT_CAUSE_OFF);
|
||||
|
||||
if (irq > 0)
|
||||
irq_set_chained_handler_and_data(irq, NULL, NULL);
|
||||
|
||||
/* Remove IRQ domains. */
|
||||
if (port->intx_irq_domain)
|
||||
irq_domain_remove(port->intx_irq_domain);
|
||||
|
||||
/* Free config space for emulated root bridge. */
|
||||
pci_bridge_emul_cleanup(&port->bridge);
|
||||
|
|
|
|||
|
|
@ -21,8 +21,11 @@
|
|||
#include "pci-bridge-emul.h"
|
||||
|
||||
#define PCI_BRIDGE_CONF_END PCI_STD_HEADER_SIZEOF
|
||||
#define PCI_CAP_SSID_SIZEOF (PCI_SSVID_DEVICE_ID + 2)
|
||||
#define PCI_CAP_SSID_START PCI_BRIDGE_CONF_END
|
||||
#define PCI_CAP_SSID_END (PCI_CAP_SSID_START + PCI_CAP_SSID_SIZEOF)
|
||||
#define PCI_CAP_PCIE_SIZEOF (PCI_EXP_SLTSTA2 + 2)
|
||||
#define PCI_CAP_PCIE_START PCI_BRIDGE_CONF_END
|
||||
#define PCI_CAP_PCIE_START PCI_CAP_SSID_END
|
||||
#define PCI_CAP_PCIE_END (PCI_CAP_PCIE_START + PCI_CAP_PCIE_SIZEOF)
|
||||
|
||||
/**
|
||||
|
|
@ -315,6 +318,25 @@ struct pci_bridge_reg_behavior pcie_cap_regs_behavior[PCI_CAP_PCIE_SIZEOF / 4] =
|
|||
},
|
||||
};
|
||||
|
||||
static pci_bridge_emul_read_status_t
|
||||
pci_bridge_emul_read_ssid(struct pci_bridge_emul *bridge, int reg, u32 *value)
|
||||
{
|
||||
switch (reg) {
|
||||
case PCI_CAP_LIST_ID:
|
||||
*value = PCI_CAP_ID_SSVID |
|
||||
(bridge->has_pcie ? (PCI_CAP_PCIE_START << 8) : 0);
|
||||
return PCI_BRIDGE_EMUL_HANDLED;
|
||||
|
||||
case PCI_SSVID_VENDOR_ID:
|
||||
*value = bridge->subsystem_vendor_id |
|
||||
(bridge->subsystem_id << 16);
|
||||
return PCI_BRIDGE_EMUL_HANDLED;
|
||||
|
||||
default:
|
||||
return PCI_BRIDGE_EMUL_NOT_HANDLED;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Initialize a pci_bridge_emul structure to represent a fake PCI
|
||||
* bridge configuration space. The caller needs to have initialized
|
||||
|
|
@ -343,9 +365,17 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
|
|||
if (!bridge->pci_regs_behavior)
|
||||
return -ENOMEM;
|
||||
|
||||
if (bridge->has_pcie) {
|
||||
if (bridge->subsystem_vendor_id)
|
||||
bridge->conf.capabilities_pointer = PCI_CAP_SSID_START;
|
||||
else if (bridge->has_pcie)
|
||||
bridge->conf.capabilities_pointer = PCI_CAP_PCIE_START;
|
||||
else
|
||||
bridge->conf.capabilities_pointer = 0;
|
||||
|
||||
if (bridge->conf.capabilities_pointer)
|
||||
bridge->conf.status |= cpu_to_le16(PCI_STATUS_CAP_LIST);
|
||||
|
||||
if (bridge->has_pcie) {
|
||||
bridge->pcie_conf.cap_id = PCI_CAP_ID_EXP;
|
||||
bridge->pcie_conf.cap |= cpu_to_le16(PCI_EXP_TYPE_ROOT_PORT << 4);
|
||||
bridge->pcie_cap_regs_behavior =
|
||||
|
|
@ -379,11 +409,20 @@ int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
|
|||
~(BIT(10) << 16);
|
||||
}
|
||||
|
||||
if (flags & PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR) {
|
||||
if (flags & PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD) {
|
||||
bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].ro = ~0;
|
||||
bridge->pci_regs_behavior[PCI_PREF_MEMORY_BASE / 4].rw = 0;
|
||||
}
|
||||
|
||||
if (flags & PCI_BRIDGE_EMUL_NO_IO_FORWARD) {
|
||||
bridge->pci_regs_behavior[PCI_COMMAND / 4].ro |= PCI_COMMAND_IO;
|
||||
bridge->pci_regs_behavior[PCI_COMMAND / 4].rw &= ~PCI_COMMAND_IO;
|
||||
bridge->pci_regs_behavior[PCI_IO_BASE / 4].ro |= GENMASK(15, 0);
|
||||
bridge->pci_regs_behavior[PCI_IO_BASE / 4].rw &= ~GENMASK(15, 0);
|
||||
bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].ro = ~0;
|
||||
bridge->pci_regs_behavior[PCI_IO_BASE_UPPER16 / 4].rw = 0;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(pci_bridge_emul_init);
|
||||
|
|
@ -415,25 +454,33 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
|
|||
__le32 *cfgspace;
|
||||
const struct pci_bridge_reg_behavior *behavior;
|
||||
|
||||
if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END) {
|
||||
*value = 0;
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END) {
|
||||
*value = 0;
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
|
||||
if (reg < PCI_BRIDGE_CONF_END) {
|
||||
/* Emulated PCI space */
|
||||
read_op = bridge->ops->read_base;
|
||||
cfgspace = (__le32 *) &bridge->conf;
|
||||
behavior = bridge->pci_regs_behavior;
|
||||
} else if (reg >= PCI_CAP_SSID_START && reg < PCI_CAP_SSID_END && bridge->subsystem_vendor_id) {
|
||||
/* Emulated PCI Bridge Subsystem Vendor ID capability */
|
||||
reg -= PCI_CAP_SSID_START;
|
||||
read_op = pci_bridge_emul_read_ssid;
|
||||
cfgspace = NULL;
|
||||
behavior = NULL;
|
||||
} else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) {
|
||||
/* Our emulated PCIe capability */
|
||||
reg -= PCI_CAP_PCIE_START;
|
||||
read_op = bridge->ops->read_pcie;
|
||||
cfgspace = (__le32 *) &bridge->pcie_conf;
|
||||
behavior = bridge->pcie_cap_regs_behavior;
|
||||
} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
|
||||
/* PCIe extended capability space */
|
||||
reg -= PCI_CFG_SPACE_SIZE;
|
||||
read_op = bridge->ops->read_ext;
|
||||
cfgspace = NULL;
|
||||
behavior = NULL;
|
||||
} else {
|
||||
read_op = bridge->ops->read_base;
|
||||
cfgspace = (__le32 *) &bridge->conf;
|
||||
behavior = bridge->pci_regs_behavior;
|
||||
/* Not implemented */
|
||||
*value = 0;
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
if (read_op)
|
||||
|
|
@ -441,15 +488,20 @@ int pci_bridge_emul_conf_read(struct pci_bridge_emul *bridge, int where,
|
|||
else
|
||||
ret = PCI_BRIDGE_EMUL_NOT_HANDLED;
|
||||
|
||||
if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED)
|
||||
*value = le32_to_cpu(cfgspace[reg / 4]);
|
||||
if (ret == PCI_BRIDGE_EMUL_NOT_HANDLED) {
|
||||
if (cfgspace)
|
||||
*value = le32_to_cpu(cfgspace[reg / 4]);
|
||||
else
|
||||
*value = 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Make sure we never return any reserved bit with a value
|
||||
* different from 0.
|
||||
*/
|
||||
*value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
|
||||
behavior[reg / 4].w1c;
|
||||
if (behavior)
|
||||
*value &= behavior[reg / 4].ro | behavior[reg / 4].rw |
|
||||
behavior[reg / 4].w1c;
|
||||
|
||||
if (size == 1)
|
||||
*value = (*value >> (8 * (where & 3))) & 0xff;
|
||||
|
|
@ -477,11 +529,31 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
|
|||
__le32 *cfgspace;
|
||||
const struct pci_bridge_reg_behavior *behavior;
|
||||
|
||||
if (bridge->has_pcie && reg >= PCI_CAP_PCIE_END)
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
|
||||
if (ret != PCIBIOS_SUCCESSFUL)
|
||||
return ret;
|
||||
|
||||
if (!bridge->has_pcie && reg >= PCI_BRIDGE_CONF_END)
|
||||
if (reg < PCI_BRIDGE_CONF_END) {
|
||||
/* Emulated PCI space */
|
||||
write_op = bridge->ops->write_base;
|
||||
cfgspace = (__le32 *) &bridge->conf;
|
||||
behavior = bridge->pci_regs_behavior;
|
||||
} else if (reg >= PCI_CAP_PCIE_START && reg < PCI_CAP_PCIE_END && bridge->has_pcie) {
|
||||
/* Our emulated PCIe capability */
|
||||
reg -= PCI_CAP_PCIE_START;
|
||||
write_op = bridge->ops->write_pcie;
|
||||
cfgspace = (__le32 *) &bridge->pcie_conf;
|
||||
behavior = bridge->pcie_cap_regs_behavior;
|
||||
} else if (reg >= PCI_CFG_SPACE_SIZE && bridge->has_pcie) {
|
||||
/* PCIe extended capability space */
|
||||
reg -= PCI_CFG_SPACE_SIZE;
|
||||
write_op = bridge->ops->write_ext;
|
||||
cfgspace = NULL;
|
||||
behavior = NULL;
|
||||
} else {
|
||||
/* Not implemented */
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
shift = (where & 0x3) * 8;
|
||||
|
||||
|
|
@ -494,44 +566,38 @@ int pci_bridge_emul_conf_write(struct pci_bridge_emul *bridge, int where,
|
|||
else
|
||||
return PCIBIOS_BAD_REGISTER_NUMBER;
|
||||
|
||||
ret = pci_bridge_emul_conf_read(bridge, reg, 4, &old);
|
||||
if (ret != PCIBIOS_SUCCESSFUL)
|
||||
return ret;
|
||||
if (behavior) {
|
||||
/* Keep all bits, except the RW bits */
|
||||
new = old & (~mask | ~behavior[reg / 4].rw);
|
||||
|
||||
if (bridge->has_pcie && reg >= PCI_CAP_PCIE_START) {
|
||||
reg -= PCI_CAP_PCIE_START;
|
||||
write_op = bridge->ops->write_pcie;
|
||||
cfgspace = (__le32 *) &bridge->pcie_conf;
|
||||
behavior = bridge->pcie_cap_regs_behavior;
|
||||
/* Update the value of the RW bits */
|
||||
new |= (value << shift) & (behavior[reg / 4].rw & mask);
|
||||
|
||||
/* Clear the W1C bits */
|
||||
new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
|
||||
} else {
|
||||
write_op = bridge->ops->write_base;
|
||||
cfgspace = (__le32 *) &bridge->conf;
|
||||
behavior = bridge->pci_regs_behavior;
|
||||
new = old & ~mask;
|
||||
new |= (value << shift) & mask;
|
||||
}
|
||||
|
||||
/* Keep all bits, except the RW bits */
|
||||
new = old & (~mask | ~behavior[reg / 4].rw);
|
||||
if (cfgspace) {
|
||||
/* Save the new value with the cleared W1C bits into the cfgspace */
|
||||
cfgspace[reg / 4] = cpu_to_le32(new);
|
||||
}
|
||||
|
||||
/* Update the value of the RW bits */
|
||||
new |= (value << shift) & (behavior[reg / 4].rw & mask);
|
||||
if (behavior) {
|
||||
/*
|
||||
* Clear the W1C bits not specified by the write mask, so that the
|
||||
* write_op() does not clear them.
|
||||
*/
|
||||
new &= ~(behavior[reg / 4].w1c & ~mask);
|
||||
|
||||
/* Clear the W1C bits */
|
||||
new &= ~((value << shift) & (behavior[reg / 4].w1c & mask));
|
||||
|
||||
/* Save the new value with the cleared W1C bits into the cfgspace */
|
||||
cfgspace[reg / 4] = cpu_to_le32(new);
|
||||
|
||||
/*
|
||||
* Clear the W1C bits not specified by the write mask, so that the
|
||||
* write_op() does not clear them.
|
||||
*/
|
||||
new &= ~(behavior[reg / 4].w1c & ~mask);
|
||||
|
||||
/*
|
||||
* Set the W1C bits specified by the write mask, so that write_op()
|
||||
* knows about that they are to be cleared.
|
||||
*/
|
||||
new |= (value << shift) & (behavior[reg / 4].w1c & mask);
|
||||
/*
|
||||
* Set the W1C bits specified by the write mask, so that write_op()
|
||||
* knows about that they are to be cleared.
|
||||
*/
|
||||
new |= (value << shift) & (behavior[reg / 4].w1c & mask);
|
||||
}
|
||||
|
||||
if (write_op)
|
||||
write_op(bridge, reg, old, new, mask);
|
||||
|
|
|
|||
|
|
@ -90,6 +90,14 @@ struct pci_bridge_emul_ops {
|
|||
*/
|
||||
pci_bridge_emul_read_status_t (*read_pcie)(struct pci_bridge_emul *bridge,
|
||||
int reg, u32 *value);
|
||||
|
||||
/*
|
||||
* Same as ->read_base(), except it is for reading from the
|
||||
* PCIe extended capability configuration space.
|
||||
*/
|
||||
pci_bridge_emul_read_status_t (*read_ext)(struct pci_bridge_emul *bridge,
|
||||
int reg, u32 *value);
|
||||
|
||||
/*
|
||||
* Called when writing to the regular PCI bridge configuration
|
||||
* space. old is the current value, new is the new value being
|
||||
|
|
@ -105,6 +113,13 @@ struct pci_bridge_emul_ops {
|
|||
*/
|
||||
void (*write_pcie)(struct pci_bridge_emul *bridge, int reg,
|
||||
u32 old, u32 new, u32 mask);
|
||||
|
||||
/*
|
||||
* Same as ->write_base(), except it is for writing from the
|
||||
* PCIe extended capability configuration space.
|
||||
*/
|
||||
void (*write_ext)(struct pci_bridge_emul *bridge, int reg,
|
||||
u32 old, u32 new, u32 mask);
|
||||
};
|
||||
|
||||
struct pci_bridge_reg_behavior;
|
||||
|
|
@ -112,15 +127,27 @@ struct pci_bridge_reg_behavior;
|
|||
struct pci_bridge_emul {
|
||||
struct pci_bridge_emul_conf conf;
|
||||
struct pci_bridge_emul_pcie_conf pcie_conf;
|
||||
struct pci_bridge_emul_ops *ops;
|
||||
const struct pci_bridge_emul_ops *ops;
|
||||
struct pci_bridge_reg_behavior *pci_regs_behavior;
|
||||
struct pci_bridge_reg_behavior *pcie_cap_regs_behavior;
|
||||
void *data;
|
||||
bool has_pcie;
|
||||
u16 subsystem_vendor_id;
|
||||
u16 subsystem_id;
|
||||
};
|
||||
|
||||
enum {
|
||||
PCI_BRIDGE_EMUL_NO_PREFETCHABLE_BAR = BIT(0),
|
||||
/*
|
||||
* PCI bridge does not support forwarding of prefetchable memory
|
||||
* requests between primary and secondary buses.
|
||||
*/
|
||||
PCI_BRIDGE_EMUL_NO_PREFMEM_FORWARD = BIT(0),
|
||||
|
||||
/*
|
||||
* PCI bridge does not support forwarding of IO requests between
|
||||
* primary and secondary buses.
|
||||
*/
|
||||
PCI_BRIDGE_EMUL_NO_IO_FORWARD = BIT(1),
|
||||
};
|
||||
|
||||
int pci_bridge_emul_init(struct pci_bridge_emul *bridge,
|
||||
|
|
|
|||
Loading…
Reference in a new issue