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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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sparc32: Use PROM device probing for sun4m timer registers.
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller
parent
3c50370103
commit
9b2e43ae4e
2 changed files with 58 additions and 108 deletions
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@ -35,49 +35,6 @@ struct sun4c_timer_info {
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#define SUN_TIMER_PHYSADDR 0xf3000000
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/* A sun4m has two blocks of registers which are probably of the same
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* structure. LSI Logic's L64851 is told to _decrement_ from the limit
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* value. Aurora behaves similarly but its limit value is compacted in
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* other fashion (it's wider). Documented fields are defined here.
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*/
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/* As with the interrupt register, we have two classes of timer registers
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* which are per-cpu and master. Per-cpu timers only hit that cpu and are
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* only level 14 ticks, master timer hits all cpus and is level 10.
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*/
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#define SUN4M_PRM_CNT_L 0x80000000
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#define SUN4M_PRM_CNT_LVALUE 0x7FFFFC00
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struct sun4m_timer_percpu_info {
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__volatile__ unsigned int l14_timer_limit; /* Initial value is 0x009c4000 */
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__volatile__ unsigned int l14_cur_count;
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/* This register appears to be write only and/or inaccessible
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* on Uni-Processor sun4m machines.
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*/
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__volatile__ unsigned int l14_limit_noclear; /* Data access error is here */
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__volatile__ unsigned int cntrl; /* =1 after POST on Aurora */
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__volatile__ unsigned char space[PAGE_SIZE - 16];
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};
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struct sun4m_timer_regs {
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struct sun4m_timer_percpu_info cpu_timers[SUN4M_NCPUS];
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volatile unsigned int l10_timer_limit;
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volatile unsigned int l10_cur_count;
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/* Again, this appears to be write only and/or inaccessible
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* on uni-processor sun4m machines.
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*/
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volatile unsigned int l10_limit_noclear;
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/* This register too, it must be magic. */
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volatile unsigned int foobar;
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volatile unsigned int cfg; /* equals zero at boot time... */
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};
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#define SUN4D_PRM_CNT_L 0x80000000
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#define SUN4D_PRM_CNT_LVALUE 0x7FFFFC00
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@ -267,95 +267,88 @@ static void sun4m_set_udt(int cpu)
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}
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#endif
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struct sun4m_timer_percpu {
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u32 l14_limit;
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u32 l14_count;
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u32 l14_limit_noclear;
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u32 user_timer_start_stop;
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};
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static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
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struct sun4m_timer_global {
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u32 l10_limit;
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u32 l10_count;
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u32 l10_limit_noclear;
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u32 reserved;
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u32 timer_config;
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};
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static struct sun4m_timer_global __iomem *timers_global;
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#define OBIO_INTR 0x20
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#define TIMER_IRQ (OBIO_INTR | 10)
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#define PROFILE_IRQ (OBIO_INTR | 14)
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static struct sun4m_timer_regs *sun4m_timers;
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unsigned int lvl14_resolution = (((1000000/HZ) + 1) << 10);
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static void sun4m_clear_clock_irq(void)
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{
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volatile unsigned int clear_intr;
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clear_intr = sun4m_timers->l10_timer_limit;
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sbus_readl(&timers_global->l10_limit);
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}
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static void sun4m_clear_profile_irq(int cpu)
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{
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volatile unsigned int clear;
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clear = sun4m_timers->cpu_timers[cpu].l14_timer_limit;
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sbus_readl(&timers_percpu[cpu]->l14_limit);
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}
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static void sun4m_load_profile_irq(int cpu, unsigned int limit)
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{
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sun4m_timers->cpu_timers[cpu].l14_timer_limit = limit;
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sbus_writel(limit, &timers_percpu[cpu]->l14_limit);
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}
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static void __init sun4m_init_timers(irq_handler_t counter_fn)
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{
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int reg_count, irq, cpu;
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struct linux_prom_registers cnt_regs[PROMREG_MAX];
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int obio_node, cnt_node;
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struct resource r;
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struct device_node *dp = of_find_node_by_name(NULL, "counter");
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int i, err, len, num_cpu_timers;
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const u32 *addr;
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cnt_node = 0;
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if((obio_node =
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prom_searchsiblings (prom_getchild(prom_root_node), "obio")) == 0 ||
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(obio_node = prom_getchild (obio_node)) == 0 ||
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(cnt_node = prom_searchsiblings (obio_node, "counter")) == 0) {
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prom_printf("Cannot find /obio/counter node\n");
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prom_halt();
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}
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reg_count = prom_getproperty(cnt_node, "reg",
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(void *) cnt_regs, sizeof(cnt_regs));
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reg_count = (reg_count/sizeof(struct linux_prom_registers));
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/* Apply the obio ranges to the timer registers. */
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prom_apply_obio_ranges(cnt_regs, reg_count);
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cnt_regs[4].phys_addr = cnt_regs[reg_count-1].phys_addr;
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cnt_regs[4].reg_size = cnt_regs[reg_count-1].reg_size;
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cnt_regs[4].which_io = cnt_regs[reg_count-1].which_io;
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for(obio_node = 1; obio_node < 4; obio_node++) {
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cnt_regs[obio_node].phys_addr =
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cnt_regs[obio_node-1].phys_addr + PAGE_SIZE;
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cnt_regs[obio_node].reg_size = cnt_regs[obio_node-1].reg_size;
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cnt_regs[obio_node].which_io = cnt_regs[obio_node-1].which_io;
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if (!dp) {
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printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
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return;
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}
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memset((char*)&r, 0, sizeof(struct resource));
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/* Map the per-cpu Counter registers. */
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r.flags = cnt_regs[0].which_io;
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r.start = cnt_regs[0].phys_addr;
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sun4m_timers = (struct sun4m_timer_regs *) of_ioremap(&r, 0,
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PAGE_SIZE*SUN4M_NCPUS, "sun4m_cpu_cnt");
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/* Map the system Counter register. */
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/* XXX Here we expect consequent calls to yeld adjusent maps. */
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r.flags = cnt_regs[4].which_io;
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r.start = cnt_regs[4].phys_addr;
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of_ioremap(&r, 0, cnt_regs[4].reg_size, "sun4m_sys_cnt");
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sun4m_timers->l10_timer_limit = (((1000000/HZ) + 1) << 10);
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master_l10_counter = &sun4m_timers->l10_cur_count;
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master_l10_limit = &sun4m_timers->l10_timer_limit;
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irq = request_irq(TIMER_IRQ,
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counter_fn,
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(IRQF_DISABLED | SA_STATIC_ALLOC),
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"timer", NULL);
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if (irq) {
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prom_printf("time_init: unable to attach IRQ%d\n",TIMER_IRQ);
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prom_halt();
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addr = of_get_property(dp, "address", &len);
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if (!addr) {
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printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
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return;
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}
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if (!cpu_find_by_instance(1, NULL, NULL)) {
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for(cpu = 0; cpu < 4; cpu++)
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sun4m_timers->cpu_timers[cpu].l14_timer_limit = 0;
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sun4m_interrupts->set = SUN4M_INT_E14;
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} else {
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sun4m_timers->cpu_timers[0].l14_timer_limit = 0;
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num_cpu_timers = (len / sizeof(u32)) - 1;
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for (i = 0; i < num_cpu_timers; i++) {
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timers_percpu[i] = (void __iomem *)
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(unsigned long) addr[i];
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}
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timers_global = (void __iomem *)
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(unsigned long) addr[num_cpu_timers];
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sbus_writel((((1000000/HZ) + 1) << 10), &timers_global->l10_limit);
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master_l10_counter = &timers_global->l10_count;
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master_l10_limit = &timers_global->l10_limit;
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err = request_irq(TIMER_IRQ, counter_fn,
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(IRQF_DISABLED | SA_STATIC_ALLOC), "timer", NULL);
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if (err) {
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printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
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err);
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return;
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}
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for (i = 0; i < num_cpu_timers; i++)
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sbus_writel(0, &timers_percpu[i]->l14_limit);
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if (num_cpu_timers == 4)
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sbus_writel(SUN4M_INT_E14, &sun4m_interrupts->set);
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#ifdef CONFIG_SMP
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{
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unsigned long flags;
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