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drm/tegra: sor: Add Tegra194 support
The SOR implemented in Tegra194 is subtly different from its predecessor found in Tegra186. Most notably some registers have been moved around so it is no longer compatible. Signed-off-by: Thierry Reding <treding@nvidia.com>
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2 changed files with 111 additions and 0 deletions
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@ -1257,6 +1257,7 @@ static const struct of_device_id host1x_drm_subdevs[] = {
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{ .compatible = "nvidia,tegra186-vic", },
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{ .compatible = "nvidia,tegra194-display", },
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{ .compatible = "nvidia,tegra194-dc", },
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{ .compatible = "nvidia,tegra194-sor", },
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{ /* sentinel */ }
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};
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@ -282,6 +282,85 @@ static const struct tegra_sor_hdmi_settings tegra186_sor_hdmi_defaults[] = {
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}
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};
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static const struct tegra_sor_hdmi_settings tegra194_sor_hdmi_defaults[] = {
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{
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.frequency = 54000000,
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.vcocap = 0,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
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.tmds_termadj = 0xf,
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.tx_pu_value = 0,
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.bg_temp_coef = 3,
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.bg_vref_level = 8,
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.avdd10_level = 4,
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.avdd14_level = 4,
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.sparepll = 0x54,
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.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
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.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
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}, {
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.frequency = 75000000,
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.vcocap = 1,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
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.tmds_termadj = 0xf,
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.tx_pu_value = 0,
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.bg_temp_coef = 3,
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.bg_vref_level = 8,
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.avdd10_level = 4,
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.avdd14_level = 4,
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.sparepll = 0x44,
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.drive_current = { 0x3a, 0x3a, 0x3a, 0x33 },
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.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
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}, {
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.frequency = 150000000,
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.vcocap = 3,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
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.tmds_termadj = 15,
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.tx_pu_value = 0x66 /* 0 */,
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.bg_temp_coef = 3,
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.bg_vref_level = 8,
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.avdd10_level = 4,
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.avdd14_level = 4,
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.sparepll = 0x00, /* 0x34 */
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.drive_current = { 0x3a, 0x3a, 0x3a, 0x37 },
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.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
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}, {
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.frequency = 300000000,
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.vcocap = 3,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
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.tmds_termadj = 15,
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.tx_pu_value = 64,
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.bg_temp_coef = 3,
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.bg_vref_level = 8,
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.avdd10_level = 4,
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.avdd14_level = 4,
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.sparepll = 0x34,
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.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
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.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
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}, {
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.frequency = 600000000,
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.vcocap = 3,
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.filter = 5,
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.ichpmp = 5,
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.loadadj = 3,
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.tmds_termadj = 12,
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.tx_pu_value = 96,
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.bg_temp_coef = 3,
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.bg_vref_level = 8,
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.avdd10_level = 4,
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.avdd14_level = 4,
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.sparepll = 0x34,
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.drive_current = { 0x3d, 0x3d, 0x3d, 0x33 },
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.preemphasis = { 0x00, 0x00, 0x00, 0x00 },
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}
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};
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struct tegra_sor_regs {
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unsigned int head_state0;
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unsigned int head_state1;
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@ -2894,7 +2973,38 @@ static const struct tegra_sor_soc tegra186_sor1 = {
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.xbar_cfg = tegra124_sor_xbar_cfg,
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};
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static const struct tegra_sor_regs tegra194_sor_regs = {
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.head_state0 = 0x151,
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.head_state1 = 0x155,
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.head_state2 = 0x159,
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.head_state3 = 0x15d,
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.head_state4 = 0x161,
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.head_state5 = 0x165,
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.pll0 = 0x169,
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.pll1 = 0x16a,
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.pll2 = 0x16b,
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.pll3 = 0x16c,
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.dp_padctl0 = 0x16e,
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.dp_padctl2 = 0x16f,
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};
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static const struct tegra_sor_soc tegra194_sor = {
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.supports_edp = true,
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.supports_lvds = false,
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.supports_hdmi = true,
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.supports_dp = true,
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.regs = &tegra194_sor_regs,
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.has_nvdisplay = true,
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.num_settings = ARRAY_SIZE(tegra194_sor_hdmi_defaults),
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.settings = tegra194_sor_hdmi_defaults,
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.xbar_cfg = tegra210_sor_xbar_cfg,
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};
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static const struct of_device_id tegra_sor_of_match[] = {
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{ .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
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{ .compatible = "nvidia,tegra186-sor1", .data = &tegra186_sor1 },
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{ .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
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{ .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
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