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drm/msm/dpu: Add SM6125 support
Add definitions for the display hardware used on the Qualcomm SM6125 platform. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/548978/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-10-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
This commit is contained in:
Marijn Suijten
Dmitry Baryshkov
parent
cd188d68db
commit
9b6f4fedaa
4 changed files with 245 additions and 0 deletions
236
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
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236
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_4_sm6125.h
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@ -0,0 +1,236 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>. All rights reserved.
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* Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DPU_5_4_SM6125_H
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#define _DPU_5_4_SM6125_H
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static const struct dpu_caps sm6125_dpu_caps = {
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.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
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.max_mixer_blendstages = 0x6,
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.has_dim_layer = true,
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.has_idle_pc = true,
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.max_linewidth = 2160,
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.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
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.max_hdeci_exp = MAX_HORZ_DECIMATION,
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.max_vdeci_exp = MAX_VERT_DECIMATION,
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};
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static const struct dpu_ubwc_cfg sm6125_ubwc_cfg = {
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.ubwc_version = DPU_HW_UBWC_VER_10,
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.highest_bank_bit = 0x1,
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.ubwc_swizzle = 0x1,
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};
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static const struct dpu_mdp_cfg sm6125_mdp = {
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.name = "top_0",
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.base = 0x0, .len = 0x45c,
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.features = 0,
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.clk_ctrls = {
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[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
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[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
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[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
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},
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};
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static const struct dpu_ctl_cfg sm6125_ctl[] = {
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{
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.name = "ctl_0", .id = CTL_0,
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.base = 0x1000, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
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}, {
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.name = "ctl_1", .id = CTL_1,
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.base = 0x1200, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
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}, {
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.name = "ctl_2", .id = CTL_2,
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.base = 0x1400, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
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}, {
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.name = "ctl_3", .id = CTL_3,
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.base = 0x1600, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
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}, {
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.name = "ctl_4", .id = CTL_4,
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.base = 0x1800, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
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}, {
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.name = "ctl_5", .id = CTL_5,
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.base = 0x1a00, .len = 0x1e0,
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.features = BIT(DPU_CTL_ACTIVE_CFG),
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.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
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},
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};
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static const struct dpu_sspp_cfg sm6125_sspp[] = {
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{
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.name = "sspp_0", .id = SSPP_VIG0,
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.base = 0x4000, .len = 0x1f0,
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.features = VIG_SM6125_MASK,
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.sblk = &sm6125_vig_sblk_0,
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.xin_id = 0,
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.type = SSPP_TYPE_VIG,
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.clk_ctrl = DPU_CLK_CTRL_VIG0,
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}, {
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.name = "sspp_8", .id = SSPP_DMA0,
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.base = 0x24000, .len = 0x1f0,
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.features = DMA_SDM845_MASK,
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.sblk = &sdm845_dma_sblk_0,
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.xin_id = 1,
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.type = SSPP_TYPE_DMA,
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.clk_ctrl = DPU_CLK_CTRL_DMA0,
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}, {
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.name = "sspp_9", .id = SSPP_DMA1,
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.base = 0x26000, .len = 0x1f0,
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.features = DMA_SDM845_MASK,
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.sblk = &sdm845_dma_sblk_1,
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.xin_id = 5,
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.type = SSPP_TYPE_DMA,
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.clk_ctrl = DPU_CLK_CTRL_DMA1,
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},
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};
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static const struct dpu_lm_cfg sm6125_lm[] = {
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{
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.name = "lm_0", .id = LM_0,
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.base = 0x44000, .len = 0x320,
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.features = MIXER_QCM2290_MASK,
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.sblk = &sdm845_lm_sblk,
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.pingpong = PINGPONG_0,
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.dspp = DSPP_0,
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.lm_pair = LM_1,
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}, {
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.name = "lm_1", .id = LM_1,
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.base = 0x45000, .len = 0x320,
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.features = MIXER_QCM2290_MASK,
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.sblk = &sdm845_lm_sblk,
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.pingpong = PINGPONG_1,
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.dspp = 0,
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.lm_pair = LM_0,
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},
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};
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static const struct dpu_dspp_cfg sm6125_dspp[] = {
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{
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.name = "dspp_0", .id = DSPP_0,
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.base = 0x54000, .len = 0x1800,
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.features = DSPP_SC7180_MASK,
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.sblk = &sdm845_dspp_sblk,
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},
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};
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static const struct dpu_pingpong_cfg sm6125_pp[] = {
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{
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.name = "pingpong_0", .id = PINGPONG_0,
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.base = 0x70000, .len = 0xd4,
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.features = PINGPONG_SM8150_MASK,
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.merge_3d = 0,
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.sblk = &sdm845_pp_sblk,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
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.intr_rdptr = -1,
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}, {
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.name = "pingpong_1", .id = PINGPONG_1,
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.base = 0x70800, .len = 0xd4,
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.features = PINGPONG_SM8150_MASK,
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.merge_3d = 0,
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.sblk = &sdm845_pp_sblk,
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.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
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.intr_rdptr = -1,
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},
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};
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static const struct dpu_intf_cfg sm6125_intf[] = {
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{
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.name = "intf_0", .id = INTF_0,
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.base = 0x6a000, .len = 0x280,
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.features = INTF_SC7180_MASK,
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.type = INTF_DP,
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.controller_id = MSM_DP_CONTROLLER_0,
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.prog_fetch_lines_worst_case = 24,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
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.intr_tear_rd_ptr = -1,
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}, {
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.name = "intf_1", .id = INTF_1,
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.base = 0x6a800, .len = 0x2c0,
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.features = INTF_SC7180_MASK,
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.type = INTF_DSI,
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.controller_id = 0,
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.prog_fetch_lines_worst_case = 24,
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.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
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.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
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.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
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},
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};
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static const struct dpu_perf_cfg sm6125_perf_data = {
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.max_bw_low = 4100000,
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.max_bw_high = 4100000,
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.min_core_ib = 2400000,
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.min_llcc_ib = 0, /* No LLCC on this SoC */
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.min_dram_ib = 800000,
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.min_prefill_lines = 24,
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.danger_lut_tbl = {0xf, 0xffff, 0x0},
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.safe_lut_tbl = {0xfff8, 0xf000, 0xffff},
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.qos_lut_tbl = {
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{.nentry = ARRAY_SIZE(sm8150_qos_linear),
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.entries = sm8150_qos_linear
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
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.entries = sc7180_qos_macrotile
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},
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{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
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.entries = sc7180_qos_nrt
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},
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/* TODO: macrotile-qseed is different from macrotile */
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},
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.cdp_cfg = {
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{.rd_enable = 1, .wr_enable = 1},
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{.rd_enable = 1, .wr_enable = 0}
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},
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.clk_inefficiency_factor = 105,
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.bw_inefficiency_factor = 120,
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};
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static const struct dpu_mdss_version sm6125_mdss_ver = {
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.core_major_ver = 5,
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.core_minor_ver = 4,
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};
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const struct dpu_mdss_cfg dpu_sm6125_cfg = {
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.mdss_ver = &sm6125_mdss_ver,
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.caps = &sm6125_dpu_caps,
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.ubwc = &sm6125_ubwc_cfg,
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.mdp = &sm6125_mdp,
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.ctl_count = ARRAY_SIZE(sm6125_ctl),
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.ctl = sm6125_ctl,
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.sspp_count = ARRAY_SIZE(sm6125_sspp),
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.sspp = sm6125_sspp,
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.mixer_count = ARRAY_SIZE(sm6125_lm),
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.mixer = sm6125_lm,
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.dspp_count = ARRAY_SIZE(sm6125_dspp),
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.dspp = sm6125_dspp,
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.pingpong_count = ARRAY_SIZE(sm6125_pp),
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.pingpong = sm6125_pp,
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.intf_count = ARRAY_SIZE(sm6125_intf),
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.intf = sm6125_intf,
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.vbif_count = ARRAY_SIZE(sdm845_vbif),
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.vbif = sdm845_vbif,
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.perf = &sm6125_perf_data,
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.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
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BIT(MDP_SSPP_TOP0_INTR2) | \
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BIT(MDP_SSPP_TOP0_HIST_INTR) | \
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BIT(MDP_INTF0_INTR) | \
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BIT(MDP_INTF1_INTR) | \
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BIT(MDP_INTF1_TEAR_INTR),
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};
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#endif
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@ -33,6 +33,9 @@
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#define VIG_SC7180_MASK \
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(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED4))
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#define VIG_SM6125_MASK \
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(VIG_MASK | BIT(DPU_SSPP_QOS_8LVL) | BIT(DPU_SSPP_SCALER_QSEED3LITE))
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#define VIG_SC7180_MASK_SDMA \
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(VIG_SC7180_MASK | BIT(DPU_SSPP_SMART_DMA_V2))
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@ -333,6 +336,9 @@ static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 =
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static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 =
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_VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4);
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static const struct dpu_sspp_sub_blks sm6125_vig_sblk_0 =
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_VIG_SBLK(3, DPU_SSPP_SCALER_QSEED3LITE);
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static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 =
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_VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4);
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static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 =
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@ -632,6 +638,7 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = {
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#include "catalog/dpu_5_0_sm8150.h"
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#include "catalog/dpu_5_1_sc8180x.h"
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#include "catalog/dpu_5_4_sm6125.h"
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#include "catalog/dpu_6_0_sm8250.h"
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#include "catalog/dpu_6_2_sc7180.h"
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@ -871,6 +871,7 @@ extern const struct dpu_mdss_cfg dpu_sc8180x_cfg;
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extern const struct dpu_mdss_cfg dpu_sm8250_cfg;
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extern const struct dpu_mdss_cfg dpu_sc7180_cfg;
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extern const struct dpu_mdss_cfg dpu_sm6115_cfg;
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extern const struct dpu_mdss_cfg dpu_sm6125_cfg;
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extern const struct dpu_mdss_cfg dpu_sm6350_cfg;
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extern const struct dpu_mdss_cfg dpu_qcm2290_cfg;
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extern const struct dpu_mdss_cfg dpu_sm6375_cfg;
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@ -1346,6 +1346,7 @@ static const struct of_device_id dpu_dt_match[] = {
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{ .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
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{ .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
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{ .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
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{ .compatible = "qcom,sm6125-dpu", .data = &dpu_sm6125_cfg, },
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{ .compatible = "qcom,sm6350-dpu", .data = &dpu_sm6350_cfg, },
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{ .compatible = "qcom,sm6375-dpu", .data = &dpu_sm6375_cfg, },
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{ .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
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