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drm/i915/selftests: Always flush before unpining after writing
Be consistent, and even when we know we had used a WC, flush the mapped object after writing into it. The flush understands the mapping type and will only clflush if !I915_MAP_WC, but will always insert a wmb [sfence] so that we can be sure that all writes are visible. v2: Add the unconditional wmb so we are know that we always flush the writes to memory/HW at that point. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20200511141304.599-1-chris@chris-wilson.co.uk
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parent
b0a997ae52
commit
9bad40a27d
7 changed files with 21 additions and 4 deletions
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@ -78,10 +78,12 @@ struct i915_vma *intel_emit_vma_fill_blt(struct intel_context *ce,
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} while (rem);
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*cmd = MI_BATCH_BUFFER_END;
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intel_gt_chipset_flush(ce->vm->gt);
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i915_gem_object_flush_map(pool->obj);
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i915_gem_object_unpin_map(pool->obj);
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intel_gt_chipset_flush(ce->vm->gt);
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batch = i915_vma_instance(pool->obj, ce->vm, NULL);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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@ -289,10 +291,12 @@ struct i915_vma *intel_emit_vma_copy_blt(struct intel_context *ce,
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} while (rem);
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*cmd = MI_BATCH_BUFFER_END;
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intel_gt_chipset_flush(ce->vm->gt);
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i915_gem_object_flush_map(pool->obj);
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i915_gem_object_unpin_map(pool->obj);
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intel_gt_chipset_flush(ce->vm->gt);
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batch = i915_vma_instance(pool->obj, ce->vm, NULL);
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if (IS_ERR(batch)) {
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err = PTR_ERR(batch);
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@ -391,6 +391,7 @@ void __i915_gem_object_flush_map(struct drm_i915_gem_object *obj,
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GEM_BUG_ON(range_overflows_t(typeof(obj->base.size),
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offset, size, obj->base.size));
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wmb(); /* let all previous writes be visible to coherent partners */
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obj->mm.dirty = true;
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if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE)
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@ -158,6 +158,8 @@ static int wc_set(struct context *ctx, unsigned long offset, u32 v)
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return PTR_ERR(map);
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map[offset / sizeof(*map)] = v;
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__i915_gem_object_flush_map(ctx->obj, offset, sizeof(*map));
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i915_gem_object_unpin_map(ctx->obj);
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return 0;
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@ -84,6 +84,7 @@ igt_emit_store_dw(struct i915_vma *vma,
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}
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*cmd = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(obj);
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i915_gem_object_unpin_map(obj);
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intel_gt_chipset_flush(vma->vm->gt);
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@ -54,6 +54,8 @@ static struct i915_vma *create_wally(struct intel_engine_cs *engine)
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*cs++ = STACK_MAGIC;
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*cs++ = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(obj);
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i915_gem_object_unpin_map(obj);
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vma->private = intel_context_create(engine); /* dummy residuals */
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@ -727,6 +727,7 @@ int live_rps_frequency_cs(void *arg)
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err_vma:
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*cancel = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(vma->obj);
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i915_gem_object_unpin_map(vma->obj);
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i915_vma_unpin(vma);
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i915_vma_put(vma);
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@ -868,6 +869,7 @@ int live_rps_frequency_srm(void *arg)
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err_vma:
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*cancel = MI_BATCH_BUFFER_END;
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i915_gem_object_flush_map(vma->obj);
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i915_gem_object_unpin_map(vma->obj);
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i915_vma_unpin(vma);
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i915_vma_put(vma);
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@ -816,10 +816,12 @@ static int recursive_batch_resolve(struct i915_vma *batch)
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return PTR_ERR(cmd);
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*cmd = MI_BATCH_BUFFER_END;
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intel_gt_chipset_flush(batch->vm->gt);
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__i915_gem_object_flush_map(batch->obj, 0, sizeof(*cmd));
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i915_gem_object_unpin_map(batch->obj);
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intel_gt_chipset_flush(batch->vm->gt);
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return 0;
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}
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@ -1060,9 +1062,12 @@ static int live_sequential_engines(void *arg)
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I915_MAP_WC);
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if (!IS_ERR(cmd)) {
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*cmd = MI_BATCH_BUFFER_END;
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intel_gt_chipset_flush(engine->gt);
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__i915_gem_object_flush_map(request[idx]->batch->obj,
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0, sizeof(*cmd));
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i915_gem_object_unpin_map(request[idx]->batch->obj);
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intel_gt_chipset_flush(engine->gt);
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}
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i915_vma_put(request[idx]->batch);
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