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KVM: PPC: Book3S HV: Work around POWER8 performance monitor bugs
This adds workarounds for two hardware bugs in the POWER8 performance monitor unit (PMU), both related to interrupt generation. The effect of these bugs is that PMU interrupts can get lost, leading to tools such as perf reporting fewer counts and samples than they should. The first bug relates to the PMAO (perf. mon. alert occurred) bit in MMCR0; setting it should cause an interrupt, but doesn't. The other bug relates to the PMAE (perf. mon. alert enable) bit in MMCR0. Setting PMAE when a counter is negative and counter negative conditions are enabled to cause alerts should cause an alert, but doesn't. The workaround for the first bug is to create conditions where a counter will overflow, whenever we are about to restore a MMCR0 value that has PMAO set (and PMAO_SYNC clear). The workaround for the second bug is to freeze all counters using MMCR2 before reading MMCR0. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Paul Mackerras
Alexander Graf
parent
6c576e74fd
commit
9bc01a9bc7
2 changed files with 64 additions and 7 deletions
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@ -670,18 +670,20 @@
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#define MMCR0_PROBLEM_DISABLE MMCR0_FCP
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#define MMCR0_FCM1 0x10000000UL /* freeze counters while MSR mark = 1 */
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#define MMCR0_FCM0 0x08000000UL /* freeze counters while MSR mark = 0 */
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#define MMCR0_PMXE 0x04000000UL /* performance monitor exception enable */
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#define MMCR0_FCECE 0x02000000UL /* freeze ctrs on enabled cond or event */
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#define MMCR0_PMXE ASM_CONST(0x04000000) /* perf mon exception enable */
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#define MMCR0_FCECE ASM_CONST(0x02000000) /* freeze ctrs on enabled cond or event */
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#define MMCR0_TBEE 0x00400000UL /* time base exception enable */
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#define MMCR0_BHRBA 0x00200000UL /* BHRB Access allowed in userspace */
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#define MMCR0_EBE 0x00100000UL /* Event based branch enable */
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#define MMCR0_PMCC 0x000c0000UL /* PMC control */
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#define MMCR0_PMCC_U6 0x00080000UL /* PMC1-6 are R/W by user (PR) */
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#define MMCR0_PMC1CE 0x00008000UL /* PMC1 count enable*/
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#define MMCR0_PMCjCE 0x00004000UL /* PMCj count enable*/
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#define MMCR0_PMCjCE ASM_CONST(0x00004000) /* PMCj count enable*/
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#define MMCR0_TRIGGER 0x00002000UL /* TRIGGER enable */
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#define MMCR0_PMAO_SYNC 0x00000800UL /* PMU interrupt is synchronous */
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#define MMCR0_PMAO 0x00000080UL /* performance monitor alert has occurred, set to 0 after handling exception */
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#define MMCR0_PMAO_SYNC ASM_CONST(0x00000800) /* PMU intr is synchronous */
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#define MMCR0_C56RUN ASM_CONST(0x00000100) /* PMC5/6 count when RUN=0 */
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/* performance monitor alert has occurred, set to 0 after handling exception */
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#define MMCR0_PMAO ASM_CONST(0x00000080)
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#define MMCR0_SHRFC 0x00000040UL /* SHRre freeze conditions between threads */
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#define MMCR0_FC56 0x00000010UL /* freeze counters 5 and 6 */
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#define MMCR0_FCTI 0x00000008UL /* freeze counters in tags inactive mode */
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@ -86,6 +86,12 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
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lbz r4, LPPACA_PMCINUSE(r3)
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cmpwi r4, 0
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beq 23f /* skip if not */
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BEGIN_FTR_SECTION
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ld r3, HSTATE_MMCR(r13)
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andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
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cmpwi r4, MMCR0_PMAO
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beql kvmppc_fix_pmao
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END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
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lwz r3, HSTATE_PMC(r13)
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lwz r4, HSTATE_PMC + 4(r13)
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lwz r5, HSTATE_PMC + 8(r13)
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@ -726,6 +732,12 @@ skip_tm:
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sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
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mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
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isync
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BEGIN_FTR_SECTION
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ld r3, VCPU_MMCR(r4)
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andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
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cmpwi r5, MMCR0_PMAO
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beql kvmppc_fix_pmao
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END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
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lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
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lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
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lwz r6, VCPU_PMC + 8(r4)
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@ -1324,6 +1336,30 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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25:
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/* Save PMU registers if requested */
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/* r8 and cr0.eq are live here */
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BEGIN_FTR_SECTION
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/*
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* POWER8 seems to have a hardware bug where setting
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* MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
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* when some counters are already negative doesn't seem
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* to cause a performance monitor alert (and hence interrupt).
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* The effect of this is that when saving the PMU state,
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* if there is no PMU alert pending when we read MMCR0
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* before freezing the counters, but one becomes pending
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* before we read the counters, we lose it.
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* To work around this, we need a way to freeze the counters
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* before reading MMCR0. Normally, freezing the counters
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* is done by writing MMCR0 (to set MMCR0[FC]) which
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* unavoidably writes MMCR0[PMA0] as well. On POWER8,
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* we can also freeze the counters using MMCR2, by writing
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* 1s to all the counter freeze condition bits (there are
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* 9 bits each for 6 counters).
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*/
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li r3, -1 /* set all freeze bits */
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clrrdi r3, r3, 10
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mfspr r10, SPRN_MMCR2
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mtspr SPRN_MMCR2, r3
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isync
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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li r3, 1
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sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
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mfspr r4, SPRN_MMCR0 /* save MMCR0 */
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@ -1347,6 +1383,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_206)
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std r4, VCPU_MMCR(r9)
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std r5, VCPU_MMCR + 8(r9)
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std r6, VCPU_MMCR + 16(r9)
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BEGIN_FTR_SECTION
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std r10, VCPU_MMCR + 24(r9)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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std r7, VCPU_SIAR(r9)
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std r8, VCPU_SDAR(r9)
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mfspr r3, SPRN_PMC1
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@ -1370,12 +1409,10 @@ BEGIN_FTR_SECTION
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stw r11, VCPU_PMC + 28(r9)
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_201)
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BEGIN_FTR_SECTION
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mfspr r4, SPRN_MMCR2
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mfspr r5, SPRN_SIER
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mfspr r6, SPRN_SPMC1
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mfspr r7, SPRN_SPMC2
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mfspr r8, SPRN_MMCRS
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std r4, VCPU_MMCR + 24(r9)
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std r5, VCPU_SIER(r9)
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stw r6, VCPU_PMC + 24(r9)
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stw r7, VCPU_PMC + 28(r9)
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@ -2311,3 +2348,21 @@ kvmppc_msr_interrupt:
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li r0, 1
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1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
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blr
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/*
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* This works around a hardware bug on POWER8E processors, where
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* writing a 1 to the MMCR0[PMAO] bit doesn't generate a
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* performance monitor interrupt. Instead, when we need to have
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* an interrupt pending, we have to arrange for a counter to overflow.
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*/
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kvmppc_fix_pmao:
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li r3, 0
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mtspr SPRN_MMCR2, r3
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lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
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ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
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mtspr SPRN_MMCR0, r3
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lis r3, 0x7fff
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ori r3, r3, 0xffff
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mtspr SPRN_PMC6, r3
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isync
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blr
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