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dt-bindings: ata: ahci-platform: Clarify common AHCI props constraints
Indeed in accordance with what is implemented in the AHCI platform driver and the way the AHCI DT nodes are defined in the DT files we can add the next AHCI DT properties constraints: AHCI CSR ID is fixed to 'ahci', PHY name is fixed to 'sata-phy', AHCI controller can't have more than 32 ports by design, AHCI controller can have up to 32 IRQ lines. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Reviewed-by: Hannes Reinecke <hare@suse.de> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
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1 changed files with 12 additions and 5 deletions
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@ -31,12 +31,16 @@ properties:
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reg-names:
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description: CSR space IDs
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contains:
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const: ahci
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interrupts:
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description:
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Generic AHCI state change interrupt. Can be implemented either as a
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single line attached to the controller or as a set of the signals
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indicating the particular port events.
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minItems: 1
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maxItems: 32
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ahci-supply:
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description: Power regulator for AHCI controller
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@ -52,14 +56,13 @@ properties:
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maxItems: 1
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phy-names:
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maxItems: 1
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const: sata-phy
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ports-implemented:
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$ref: '/schemas/types.yaml#/definitions/uint32'
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description:
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Mask that indicates which ports the HBA supports. Useful if PI is not
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programmed by the BIOS, which is true for some embedded SoC's.
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maximum: 0x1f
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patternProperties:
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"^sata-port@[0-9a-f]+$":
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@ -80,8 +83,12 @@ $defs:
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properties:
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reg:
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description: AHCI SATA port identifier
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maxItems: 1
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description:
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AHCI SATA port identifier. By design AHCI controller can't have
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more than 32 ports due to the CAP.NP fields and PI register size
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constraints.
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minimum: 0
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maximum: 31
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phys:
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description: Individual AHCI SATA port PHY
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@ -89,7 +96,7 @@ $defs:
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phy-names:
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description: AHCI SATA port PHY ID
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maxItems: 1
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const: sata-phy
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target-supply:
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description: Power regulator for SATA port target device
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