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ata_piix: kill ich6_sata_ahci and clean up
ich6_sata_ahci and ich6_sata are identical. Kill ich6_sata_ahci and drop _ahci postfixes from controller ids, which doesn't really mean anything at this point. Signed-off-by: Tejun Heo <htejun@gmail.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
This commit is contained in:
parent
5016d7d212
commit
9c0bf67505
1 changed files with 25 additions and 36 deletions
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@ -138,12 +138,11 @@ enum piix_controller_ids {
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ich_pata_100, /* ICH up to UDMA 100 */
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ich_pata_100, /* ICH up to UDMA 100 */
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ich5_sata,
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ich5_sata,
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ich6_sata,
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ich6_sata,
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ich6_sata_ahci,
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ich6m_sata,
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ich6m_sata_ahci,
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ich8_sata,
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ich8_sata_ahci,
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ich8_2port_sata,
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ich8_2port_sata,
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ich8m_apple_sata_ahci, /* locks up on second port enable */
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ich8m_apple_sata, /* locks up on second port enable */
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tolapai_sata_ahci,
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tolapai_sata,
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piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
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piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
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};
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};
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@ -235,27 +234,27 @@ static const struct pci_device_id piix_pci_tbl[] = {
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/* 82801FB/FW (ICH6/ICH6W) */
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/* 82801FB/FW (ICH6/ICH6W) */
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{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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{ 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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/* 82801FR/FRW (ICH6R/ICH6RW) */
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/* 82801FR/FRW (ICH6R/ICH6RW) */
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{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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{ 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
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/* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
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* Attach iff the controller is in IDE mode. */
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* Attach iff the controller is in IDE mode. */
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{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
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{ 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
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PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata_ahci },
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PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
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/* 82801GB/GR/GH (ICH7, identical to ICH6) */
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/* 82801GB/GR/GH (ICH7, identical to ICH6) */
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{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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{ 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
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/* 2801GBM/GHM (ICH7M, identical to ICH6M) */
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{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
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{ 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
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/* Enterprise Southbridge 2 (631xESB/632xESB) */
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/* Enterprise Southbridge 2 (631xESB/632xESB) */
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{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
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{ 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
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/* SATA Controller 1 IDE (ICH8) */
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/* SATA Controller 1 IDE (ICH8) */
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{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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/* SATA Controller 2 IDE (ICH8) */
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/* SATA Controller 2 IDE (ICH8) */
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{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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{ 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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/* Mobile SATA Controller IDE (ICH8M) */
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/* Mobile SATA Controller IDE (ICH8M) */
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{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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/* Mobile SATA Controller IDE (ICH8M), Apple */
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/* Mobile SATA Controller IDE (ICH8M), Apple */
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{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata_ahci },
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{ 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
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/* SATA Controller IDE (ICH9) */
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/* SATA Controller IDE (ICH9) */
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{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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/* SATA Controller IDE (ICH9) */
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/* SATA Controller IDE (ICH9) */
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{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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{ 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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/* SATA Controller IDE (ICH9) */
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/* SATA Controller IDE (ICH9) */
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@ -265,15 +264,15 @@ static const struct pci_device_id piix_pci_tbl[] = {
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/* SATA Controller IDE (ICH9M) */
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/* SATA Controller IDE (ICH9M) */
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{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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{ 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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/* SATA Controller IDE (ICH9M) */
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/* SATA Controller IDE (ICH9M) */
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{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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/* SATA Controller IDE (Tolapai) */
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/* SATA Controller IDE (Tolapai) */
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{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata_ahci },
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{ 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
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/* SATA Controller IDE (ICH10) */
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/* SATA Controller IDE (ICH10) */
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{ 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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/* SATA Controller IDE (ICH10) */
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/* SATA Controller IDE (ICH10) */
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{ 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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{ 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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/* SATA Controller IDE (ICH10) */
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/* SATA Controller IDE (ICH10) */
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{ 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_ahci },
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{ 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
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/* SATA Controller IDE (ICH10) */
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/* SATA Controller IDE (ICH10) */
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{ 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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{ 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
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@ -421,12 +420,11 @@ static const struct piix_map_db tolapai_map_db = {
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static const struct piix_map_db *piix_map_db_table[] = {
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static const struct piix_map_db *piix_map_db_table[] = {
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[ich5_sata] = &ich5_map_db,
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[ich5_sata] = &ich5_map_db,
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[ich6_sata] = &ich6_map_db,
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[ich6_sata] = &ich6_map_db,
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[ich6_sata_ahci] = &ich6_map_db,
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[ich6m_sata] = &ich6m_map_db,
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[ich6m_sata_ahci] = &ich6m_map_db,
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[ich8_sata] = &ich8_map_db,
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[ich8_sata_ahci] = &ich8_map_db,
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[ich8_2port_sata] = &ich8_2port_map_db,
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[ich8_2port_sata] = &ich8_2port_map_db,
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[ich8m_apple_sata_ahci] = &ich8m_apple_map_db,
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[ich8m_apple_sata] = &ich8m_apple_map_db,
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[tolapai_sata_ahci] = &tolapai_map_db,
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[tolapai_sata] = &tolapai_map_db,
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};
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};
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static struct ata_port_info piix_port_info[] = {
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static struct ata_port_info piix_port_info[] = {
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@ -492,7 +490,7 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &piix_sata_ops,
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.port_ops = &piix_sata_ops,
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},
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},
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[ich6_sata_ahci] =
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[ich6m_sata] =
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{
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{
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.flags = PIIX_SATA_FLAGS,
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.flags = PIIX_SATA_FLAGS,
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.pio_mask = 0x1f, /* pio0-4 */
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.pio_mask = 0x1f, /* pio0-4 */
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@ -501,16 +499,7 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &piix_sata_ops,
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.port_ops = &piix_sata_ops,
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},
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},
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[ich6m_sata_ahci] =
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[ich8_sata] =
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{
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.flags = PIIX_SATA_FLAGS,
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.pio_mask = 0x1f, /* pio0-4 */
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.mwdma_mask = 0x07, /* mwdma0-2 */
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.udma_mask = ATA_UDMA6,
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.port_ops = &piix_sata_ops,
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},
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[ich8_sata_ahci] =
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{
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{
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.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
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.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
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.pio_mask = 0x1f, /* pio0-4 */
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.pio_mask = 0x1f, /* pio0-4 */
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@ -528,7 +517,7 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &piix_sata_ops,
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.port_ops = &piix_sata_ops,
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},
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},
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[tolapai_sata_ahci] =
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[tolapai_sata] =
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{
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{
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.flags = PIIX_SATA_FLAGS,
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.flags = PIIX_SATA_FLAGS,
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.pio_mask = 0x1f, /* pio0-4 */
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.pio_mask = 0x1f, /* pio0-4 */
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@ -537,7 +526,7 @@ static struct ata_port_info piix_port_info[] = {
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.port_ops = &piix_sata_ops,
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.port_ops = &piix_sata_ops,
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},
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},
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[ich8m_apple_sata_ahci] =
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[ich8m_apple_sata] =
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{
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{
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.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
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.flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
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.pio_mask = 0x1f, /* pio0-4 */
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.pio_mask = 0x1f, /* pio0-4 */
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