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rtl8188eu : BIT() macro cleanup

Browse source 
Use the BIT(x) macro directly instead using multiple
BITX defines.

Signed-off-by: Anish Bhatt <anish@gatech.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Anish Bhatt 2015-10-18 22:51:41 -07:00 committed by Greg Kroah-Hartman
parent b0dcce5fbf
commit 9c68ed09fe
19 changed files with 485 additions and 557 deletions
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48
drivers/staging/rtl8188eu/core/rtw_efuse.c
View file

@ -396,7 +396,7 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e
memset((void *)tmpdata, 0xff, PGPKT_DATA_SIZE);
if (!(word_en&BIT0)) {
if (!(word_en & BIT(0))) {
tmpaddr = start_addr;
efuse_OneByteWrite(pAdapter, start_addr++, data[0]);
efuse_OneByteWrite(pAdapter, start_addr++, data[1]);
@ -404,9 +404,9 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e
efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[0]);
efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[1]);
if ((data[0] != tmpdata[0]) || (data[1] != tmpdata[1]))
badworden &= (~BIT0);
badworden &= (~BIT(0));
}
if (!(word_en&BIT1)) {
if (!(word_en & BIT(1))) {
tmpaddr = start_addr;
efuse_OneByteWrite(pAdapter, start_addr++, data[2]);
efuse_OneByteWrite(pAdapter, start_addr++, data[3]);
@ -414,9 +414,9 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e
efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[2]);
efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[3]);
if ((data[2] != tmpdata[2]) || (data[3] != tmpdata[3]))
badworden &= (~BIT1);
badworden &= (~BIT(1));
}
if (!(word_en&BIT2)) {
if (!(word_en & BIT(2))) {
tmpaddr = start_addr;
efuse_OneByteWrite(pAdapter, start_addr++, data[4]);
efuse_OneByteWrite(pAdapter, start_addr++, data[5]);
@ -424,9 +424,9 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e
efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[4]);
efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[5]);
if ((data[4] != tmpdata[4]) || (data[5] != tmpdata[5]))
badworden &= (~BIT2);
badworden &= (~BIT(2));
}
if (!(word_en&BIT3)) {
if (!(word_en & BIT(3))) {
tmpaddr = start_addr;
efuse_OneByteWrite(pAdapter, start_addr++, data[6]);
efuse_OneByteWrite(pAdapter, start_addr++, data[7]);
@ -434,7 +434,7 @@ u8 Efuse_WordEnableDataWrite(struct adapter *pAdapter, u16 efuse_addr, u8 word_e
efuse_OneByteRead(pAdapter, tmpaddr, &tmpdata[6]);
efuse_OneByteRead(pAdapter, tmpaddr+1, &tmpdata[7]);
if ((data[6] != tmpdata[6]) || (data[7] != tmpdata[7]))
badworden &= (~BIT3);
badworden &= (~BIT(3));
}
return badworden;
}
@ -738,18 +738,18 @@ static bool wordEnMatched(struct pgpkt *pTargetPkt, struct pgpkt *pCurPkt,
u8 match_word_en = 0x0F; /* default all words are disabled */
/* check if the same words are enabled both target and current PG packet */
if (((pTargetPkt->word_en & BIT0) == 0) &&
((pCurPkt->word_en & BIT0) == 0))
match_word_en &= ~BIT0; /* enable word 0 */
if (((pTargetPkt->word_en & BIT1) == 0) &&
((pCurPkt->word_en & BIT1) == 0))
match_word_en &= ~BIT1; /* enable word 1 */
if (((pTargetPkt->word_en & BIT2) == 0) &&
((pCurPkt->word_en & BIT2) == 0))
match_word_en &= ~BIT2; /* enable word 2 */
if (((pTargetPkt->word_en & BIT3) == 0) &&
((pCurPkt->word_en & BIT3) == 0))
match_word_en &= ~BIT3; /* enable word 3 */
if (((pTargetPkt->word_en & BIT(0)) == 0) &&
((pCurPkt->word_en & BIT(0)) == 0))
match_word_en &= ~BIT(0); /* enable word 0 */
if (((pTargetPkt->word_en & BIT(1)) == 0) &&
((pCurPkt->word_en & BIT(1)) == 0))
match_word_en &= ~BIT(1); /* enable word 1 */
if (((pTargetPkt->word_en & BIT(2)) == 0) &&
((pCurPkt->word_en & BIT(2)) == 0))
match_word_en &= ~BIT(2); /* enable word 2 */
if (((pTargetPkt->word_en & BIT(3)) == 0) &&
((pCurPkt->word_en & BIT(3)) == 0))
match_word_en &= ~BIT(3); /* enable word 3 */
*pWden = match_word_en;
@ -961,19 +961,19 @@ u8 efuse_OneByteWrite(struct adapter *pAdapter, u16 addr, u8 data)
*/
void efuse_WordEnableDataRead(u8 word_en, u8 *sourdata, u8 *targetdata)
{
if (!(word_en&BIT(0))) {
if (!(word_en & BIT(0))) {
targetdata[0] = sourdata[0];
targetdata[1] = sourdata[1];
}
if (!(word_en&BIT(1))) {
if (!(word_en & BIT(1))) {
targetdata[2] = sourdata[2];
targetdata[3] = sourdata[3];
}
if (!(word_en&BIT(2))) {
if (!(word_en & BIT(2))) {
targetdata[4] = sourdata[4];
targetdata[5] = sourdata[5];
}
if (!(word_en&BIT(3))) {
if (!(word_en & BIT(3))) {
targetdata[6] = sourdata[6];
targetdata[7] = sourdata[7];
}

2
drivers/staging/rtl8188eu/hal/bb_cfg.c
View file

@ -705,7 +705,7 @@ bool rtl88eu_phy_bb_config(struct adapter *adapt)
/* Enable BB and RF */
regval = usb_read16(adapt, REG_SYS_FUNC_EN);
usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval|BIT13|BIT0|BIT1));
usb_write16(adapt, REG_SYS_FUNC_EN, (u16)(regval | BIT(13) | BIT(0) | BIT(1)));
usb_write8(adapt, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);

24
drivers/staging/rtl8188eu/hal/odm.c
View file

@ -437,7 +437,7 @@ void odm_CommonInfoSelfInit(struct odm_dm_struct *pDM_Odm)
{
struct adapter *adapter = pDM_Odm->Adapter;
pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT9);
pDM_Odm->bCckHighPower = (bool)phy_query_bb_reg(adapter, 0x824, BIT(9));
pDM_Odm->RFPathRxEnable = (u8)phy_query_bb_reg(adapter, 0xc04, 0x0F);
ODM_InitDebugSetting(pDM_Odm);
@ -736,8 +736,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
return;
/* hold ofdm counter */
phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); /* hold page C counter */
phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); /* hold page D counter */
phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_HOLDC_11N, BIT(31), 1); /* hold page C counter */
phy_set_bb_reg(adapter, ODM_REG_OFDM_FA_RSTD_11N, BIT(31), 1); /* hold page D counter */
ret_value = phy_query_bb_reg(adapter, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
@ -760,8 +760,8 @@ void odm_FalseAlarmCounterStatistics(struct odm_dm_struct *pDM_Odm)
FalseAlmCnt->Cnt_BW_USC = (ret_value & 0xffff0000)>>16;
/* hold cck counter */
phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(12), 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_FA_RST_11N, BIT(14), 1);
ret_value = phy_query_bb_reg(adapter, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
FalseAlmCnt->Cnt_Cck_fail = ret_value;
@ -853,7 +853,7 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
}
if (pDM_PSTable->initialize == 0) {
pDM_PSTable->Reg874 = (phy_query_bb_reg(adapter, 0x874, bMaskDWord)&0x1CC000)>>14;
pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord)&BIT3)>>3;
pDM_PSTable->RegC70 = (phy_query_bb_reg(adapter, 0xc70, bMaskDWord) & BIT(3))>>3;
pDM_PSTable->Reg85C = (phy_query_bb_reg(adapter, 0x85c, bMaskDWord)&0xFF000000)>>24;
pDM_PSTable->RegA74 = (phy_query_bb_reg(adapter, 0xa74, bMaskDWord)&0xF000)>>12;
pDM_PSTable->initialize = 1;
@ -882,18 +882,18 @@ void ODM_RF_Saving(struct odm_dm_struct *pDM_Odm, u8 bForceInNormal)
if (pDM_PSTable->PreRFState != pDM_PSTable->CurRFState) {
if (pDM_PSTable->CurRFState == RF_Save) {
phy_set_bb_reg(adapter, 0x874, 0x1C0000, 0x2); /* Reg874[20:18]=3'b010 */
phy_set_bb_reg(adapter, 0xc70, BIT3, 0); /* RegC70[3]=1'b0 */
phy_set_bb_reg(adapter, 0xc70, BIT(3), 0); /* RegC70[3]=1'b0 */
phy_set_bb_reg(adapter, 0x85c, 0xFF000000, 0x63); /* Reg85C[31:24]=0x63 */
phy_set_bb_reg(adapter, 0x874, 0xC000, 0x2); /* Reg874[15:14]=2'b10 */
phy_set_bb_reg(adapter, 0xa74, 0xF000, 0x3); /* RegA75[7:4]=0x3 */
phy_set_bb_reg(adapter, 0x818, BIT28, 0x0); /* Reg818[28]=1'b0 */
phy_set_bb_reg(adapter, 0x818, BIT28, 0x1); /* Reg818[28]=1'b1 */
phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0); /* Reg818[28]=1'b0 */
phy_set_bb_reg(adapter, 0x818, BIT(28), 0x1); /* Reg818[28]=1'b1 */
} else {
phy_set_bb_reg(adapter, 0x874, 0x1CC000, pDM_PSTable->Reg874);
phy_set_bb_reg(adapter, 0xc70, BIT3, pDM_PSTable->RegC70);
phy_set_bb_reg(adapter, 0xc70, BIT(3), pDM_PSTable->RegC70);
phy_set_bb_reg(adapter, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
phy_set_bb_reg(adapter, 0xa74, 0xF000, pDM_PSTable->RegA74);
phy_set_bb_reg(adapter, 0x818, BIT28, 0x0);
phy_set_bb_reg(adapter, 0x818, BIT(28), 0x0);
}
pDM_PSTable->PreRFState = pDM_PSTable->CurRFState;
}
@ -1229,7 +1229,7 @@ void odm_TXPowerTrackingCheckCE(struct odm_dm_struct *pDM_Odm)
return;
if (!pDM_Odm->RFCalibrateInfo.TM_Trigger) { /* at least delay 1 sec */
phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
phy_set_rf_reg(Adapter, RF_PATH_A, RF_T_METER_88E, BIT(17) | BIT(16), 0x03);
pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
return;

4
drivers/staging/rtl8188eu/hal/odm_HWConfig.c
View file

@ -362,7 +362,7 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm,
}
}
pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0;
pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT(0);
} else {
RSSI_Ave = pPhyInfo->RxPWDBAll;
@ -391,7 +391,7 @@ static void odm_Process_RSSIForDM(struct odm_dm_struct *dm_odm,
pEntry->rssi_stat.ValidBit++;
for (i = 0; i < pEntry->rssi_stat.ValidBit; i++)
OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i) & BIT(0);
if (pEntry->rssi_stat.ValidBit == 64) {
Weighting = ((OFDM_pkt<<4) > 64) ? 64 : (OFDM_pkt<<4);

116
drivers/staging/rtl8188eu/hal/odm_RTL8188E.c
View file

@ -28,26 +28,26 @@ static void dm_rx_hw_antena_div_init(struct odm_dm_struct *dm_odm)
if (*(dm_odm->mp_mode) == 1) {
dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
return;
}
/* MAC Setting */
value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
value32|(BIT23|BIT25));
value32|(BIT(23) | BIT(25)));
/* Pin Settings */
phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 1);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);
phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 1);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
/* OFDM Settings */
phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
0x000000a0);
/* CCK Settings */
phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);
phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, 0xFFFF, 0x0201);
}
@ -59,37 +59,37 @@ static void dm_trx_hw_antenna_div_init(struct odm_dm_struct *dm_odm)
if (*(dm_odm->mp_mode) == 1) {
dm_odm->AntDivType = CGCS_RX_SW_ANTDIV;
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT5|BIT4|BIT3, 0);
BIT(5) | BIT(4) | BIT(3), 0);
return;
}
/* MAC Setting */
value32 = phy_query_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord);
phy_set_bb_reg(adapter, ODM_REG_ANTSEL_PIN_11N, bMaskDWord,
value32|(BIT23|BIT25));
value32|(BIT(23) | BIT(25)));
/* Pin Settings */
phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT9|BIT8, 0);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT10, 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT22, 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT31, 1);
phy_set_bb_reg(adapter, ODM_REG_PIN_CTRL_11N, BIT(9) | BIT(8), 0);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N, BIT(10), 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(22), 0);
phy_set_bb_reg(adapter, ODM_REG_LNA_SWITCH_11N, BIT(31), 1);
/* OFDM Settings */
phy_set_bb_reg(adapter, ODM_REG_ANTDIV_PARA1_11N, bMaskDWord,
0x000000a0);
/* CCK Settings */
phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT7, 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 1);
phy_set_bb_reg(adapter, ODM_REG_BB_PWR_SAV4_11N, BIT(7), 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA2_11N, BIT(4), 1);
/* Tx Settings */
phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT21, 0);
phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N, BIT(21), 0);
rtl88eu_dm_update_rx_idle_ant(dm_odm, MAIN_ANT);
/* antenna mapping table */
if (!dm_odm->bIsMPChip) { /* testchip */
phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N,
BIT10|BIT9|BIT8, 1);
BIT(10) | BIT(9) | BIT(8), 1);
phy_set_bb_reg(adapter, ODM_REG_RX_DEFUALT_A_11N,
BIT13|BIT12|BIT11, 2);
BIT(13) | BIT(12) | BIT(11), 2);
} else { /* MPchip */
phy_set_bb_reg(adapter, ODM_REG_ANT_MAPPING1_11N, bMaskDWord,
0x0201);
@ -118,40 +118,40 @@ static void dm_fast_training_init(struct odm_dm_struct *dm_odm)
/* MAC Setting */
value32 = phy_query_bb_reg(adapter, 0x4c, bMaskDWord);
phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT23|BIT25));
phy_set_bb_reg(adapter, 0x4c, bMaskDWord, value32|(BIT(23) | BIT(25)));
value32 = phy_query_bb_reg(adapter, 0x7B4, bMaskDWord);
phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT16|BIT17));
phy_set_bb_reg(adapter, 0x7b4, bMaskDWord, value32|(BIT(16) | BIT(17)));
/* Match MAC ADDR */
phy_set_bb_reg(adapter, 0x7b4, 0xFFFF, 0);
phy_set_bb_reg(adapter, 0x7b0, bMaskDWord, 0);
phy_set_bb_reg(adapter, 0x870, BIT9|BIT8, 0);
phy_set_bb_reg(adapter, 0x864, BIT10, 0);
phy_set_bb_reg(adapter, 0xb2c, BIT22, 0);
phy_set_bb_reg(adapter, 0xb2c, BIT31, 1);
phy_set_bb_reg(adapter, 0x870, BIT(9) | BIT(8), 0);
phy_set_bb_reg(adapter, 0x864, BIT(10), 0);
phy_set_bb_reg(adapter, 0xb2c, BIT(22), 0);
phy_set_bb_reg(adapter, 0xb2c, BIT(31), 1);
phy_set_bb_reg(adapter, 0xca4, bMaskDWord, 0x000000a0);
/* antenna mapping table */
if (AntCombination == 2) {
if (!dm_odm->bIsMPChip) { /* testchip */
phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 1);
phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 2);
phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 1);
phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 2);
} else { /* MPchip */
phy_set_bb_reg(adapter, 0x914, bMaskByte0, 1);
phy_set_bb_reg(adapter, 0x914, bMaskByte1, 2);
}
} else if (AntCombination == 7) {
if (!dm_odm->bIsMPChip) { /* testchip */
phy_set_bb_reg(adapter, 0x858, BIT10|BIT9|BIT8, 0);
phy_set_bb_reg(adapter, 0x858, BIT13|BIT12|BIT11, 1);
phy_set_bb_reg(adapter, 0x878, BIT16, 0);
phy_set_bb_reg(adapter, 0x858, BIT15|BIT14, 2);
phy_set_bb_reg(adapter, 0x878, BIT19|BIT18|BIT17, 3);
phy_set_bb_reg(adapter, 0x878, BIT22|BIT21|BIT20, 4);
phy_set_bb_reg(adapter, 0x878, BIT25|BIT24|BIT23, 5);
phy_set_bb_reg(adapter, 0x878, BIT28|BIT27|BIT26, 6);
phy_set_bb_reg(adapter, 0x878, BIT31|BIT30|BIT29, 7);
phy_set_bb_reg(adapter, 0x858, BIT(10) | BIT(9) | BIT(8), 0);
phy_set_bb_reg(adapter, 0x858, BIT(13) | BIT(12) | BIT(11), 1);
phy_set_bb_reg(adapter, 0x878, BIT(16), 0);
phy_set_bb_reg(adapter, 0x858, BIT(15) | BIT(14), 2);
phy_set_bb_reg(adapter, 0x878, BIT(19) | BIT(18) | BIT(17), 3);
phy_set_bb_reg(adapter, 0x878, BIT(22) | BIT(21) | BIT(20), 4);
phy_set_bb_reg(adapter, 0x878, BIT(25) | BIT(24) | BIT(23), 5);
phy_set_bb_reg(adapter, 0x878, BIT(28) | BIT(27) | BIT(26), 6);
phy_set_bb_reg(adapter, 0x878, BIT(31) | BIT(30) | BIT(29), 7);
} else { /* MPchip */
phy_set_bb_reg(adapter, 0x914, bMaskByte0, 0);
phy_set_bb_reg(adapter, 0x914, bMaskByte1, 1);
@ -165,13 +165,13 @@ static void dm_fast_training_init(struct odm_dm_struct *dm_odm)
}
/* Default Ant Setting when no fast training */
phy_set_bb_reg(adapter, 0x80c, BIT21, 1);
phy_set_bb_reg(adapter, 0x864, BIT5|BIT4|BIT3, 0);
phy_set_bb_reg(adapter, 0x864, BIT8|BIT7|BIT6, 1);
phy_set_bb_reg(adapter, 0x80c, BIT(21), 1);
phy_set_bb_reg(adapter, 0x864, BIT(5) | BIT(4) | BIT(3), 0);
phy_set_bb_reg(adapter, 0x864, BIT(8) | BIT(7) | BIT(6), 1);
/* Enter Traing state */
phy_set_bb_reg(adapter, 0x864, BIT2|BIT1|BIT0, (AntCombination-1));
phy_set_bb_reg(adapter, 0xc50, BIT7, 1);
phy_set_bb_reg(adapter, 0x864, BIT(2) | BIT(1) | BIT(0), (AntCombination-1));
phy_set_bb_reg(adapter, 0xc50, BIT(7), 1);
}
void rtl88eu_dm_antenna_div_init(struct odm_dm_struct *dm_odm)
@ -205,18 +205,18 @@ void rtl88eu_dm_update_rx_idle_ant(struct odm_dm_struct *dm_odm, u8 ant)
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV) {
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT5|BIT4|BIT3, default_ant);
BIT(5) | BIT(4) | BIT(3), default_ant);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT8|BIT7|BIT6, optional_ant);
BIT(8) | BIT(7) | BIT(6), optional_ant);
phy_set_bb_reg(adapter, ODM_REG_ANTSEL_CTRL_11N,
BIT14|BIT13|BIT12, default_ant);
BIT(14) | BIT(13) | BIT(12), default_ant);
phy_set_bb_reg(adapter, ODM_REG_RESP_TX_11N,
BIT6|BIT7, default_ant);
BIT(6) | BIT(7), default_ant);
} else if (dm_odm->AntDivType == CGCS_RX_HW_ANTDIV) {
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT5|BIT4|BIT3, default_ant);
BIT(5) | BIT(4) | BIT(3), default_ant);
phy_set_bb_reg(adapter, ODM_REG_RX_ANT_CTRL_11N,
BIT8|BIT7|BIT6, optional_ant);
BIT(8) | BIT(7) | BIT(6), optional_ant);
}
}
dm_fat_tbl->RxIdleAnt = ant;
@ -231,9 +231,9 @@ static void update_tx_ant_88eu(struct odm_dm_struct *dm_odm, u8 ant, u32 mac_id)
target_ant = MAIN_ANT_CG_TRX;
else
target_ant = AUX_ANT_CG_TRX;
dm_fat_tbl->antsel_a[mac_id] = target_ant&BIT0;
dm_fat_tbl->antsel_b[mac_id] = (target_ant&BIT1)>>1;
dm_fat_tbl->antsel_c[mac_id] = (target_ant&BIT2)>>2;
dm_fat_tbl->antsel_a[mac_id] = target_ant & BIT(0);
dm_fat_tbl->antsel_b[mac_id] = (target_ant & BIT(1))>>1;
dm_fat_tbl->antsel_c[mac_id] = (target_ant & BIT(2))>>2;
}
void rtl88eu_dm_set_tx_ant_by_tx_info(struct odm_dm_struct *dm_odm,
@ -344,12 +344,12 @@ void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm)
if (dm_fat_tbl->bBecomeLinked) {
ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("Need to Turn off HW AntDiv\n"));
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 0);
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 0);
phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
BIT15, 0);
BIT(15), 0);
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
BIT21, 0);
BIT(21), 0);
dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
}
return;
@ -357,12 +357,12 @@ void rtl88eu_dm_antenna_diversity(struct odm_dm_struct *dm_odm)
if (!dm_fat_tbl->bBecomeLinked) {
ODM_RT_TRACE(dm_odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
("Need to Turn on HW AntDiv\n"));
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT7, 1);
phy_set_bb_reg(adapter, ODM_REG_IGI_A_11N, BIT(7), 1);
phy_set_bb_reg(adapter, ODM_REG_CCK_ANTDIV_PARA1_11N,
BIT15, 1);
BIT(15), 1);
if (dm_odm->AntDivType == CG_TRX_HW_ANTDIV)
phy_set_bb_reg(adapter, ODM_REG_TX_ANT_CTRL_11N,
BIT21, 1);
BIT(21), 1);
dm_fat_tbl->bBecomeLinked = dm_odm->bLinked;
}
}

30
drivers/staging/rtl8188eu/hal/phy.c
View file

@ -97,9 +97,9 @@ static u32 rf_serial_read(struct adapter *adapt,
udelay(10);
if (rfpath == RF_PATH_A)
rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT8);
rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1, BIT(8));
else if (rfpath == RF_PATH_B)
rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, BIT8);
rfpi_enable = (u8)phy_query_bb_reg(adapt, rFPGA0_XB_HSSIParameter1, BIT(8));
if (rfpi_enable)
ret = phy_query_bb_reg(adapt, phyreg->rfLSSIReadBackPi,
@ -293,7 +293,7 @@ static void phy_set_bw_mode_callback(struct adapter *adapt)
(hal_data->nCur40MhzPrimeSC>>1));
phy_set_bb_reg(adapt, rOFDM1_LSTF, 0xC00,
hal_data->nCur40MhzPrimeSC);
phy_set_bb_reg(adapt, 0x818, (BIT26 | BIT27),
phy_set_bb_reg(adapt, 0x818, (BIT(26) | BIT(27)),
(hal_data->nCur40MhzPrimeSC == HAL_PRIME_CHNL_OFFSET_LOWER) ? 2 : 1);
break;
default:
@ -652,7 +652,7 @@ static u8 phy_path_a_iqk(struct adapter *adapt, bool config_pathb)
reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
if (!(reg_eac & BIT28) &&
if (!(reg_eac & BIT(28)) &&
(((reg_e94 & 0x03FF0000)>>16) != 0x142) &&
(((reg_e9c & 0x03FF0000)>>16) != 0x42))
result |= 0x01;
@ -705,7 +705,7 @@ static u8 phy_path_a_rx_iqk(struct adapter *adapt, bool configPathB)
reg_e94 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A, bMaskDWord);
reg_e9c = phy_query_bb_reg(adapt, rTx_Power_After_IQK_A, bMaskDWord);
if (!(reg_eac & BIT28) &&
if (!(reg_eac & BIT(28)) &&
(((reg_e94 & 0x03FF0000)>>16) != 0x142) &&
(((reg_e9c & 0x03FF0000)>>16) != 0x42))
result |= 0x01;
@ -753,7 +753,7 @@ static u8 phy_path_a_rx_iqk(struct adapter *adapt, bool configPathB)
phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x00000000);
phy_set_rf_reg(adapt, RF_PATH_A, 0xdf, bRFRegOffsetMask, 0x180);
if (!(reg_eac & BIT27) && /* if Tx is OK, check whether Rx is OK */
if (!(reg_eac & BIT(27)) && /* if Tx is OK, check whether Rx is OK */
(((reg_ea4 & 0x03FF0000)>>16) != 0x132) &&
(((reg_eac & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
@ -783,14 +783,14 @@ static u8 phy_path_b_iqk(struct adapter *adapt)
regec4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2, bMaskDWord);
regecc = phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2, bMaskDWord);
if (!(regeac & BIT31) &&
if (!(regeac & BIT(31)) &&
(((regeb4 & 0x03FF0000)>>16) != 0x142) &&
(((regebc & 0x03FF0000)>>16) != 0x42))
result |= 0x01;
else
return result;
if (!(regeac & BIT30) &&
if (!(regeac & BIT(30)) &&
(((regec4 & 0x03FF0000)>>16) != 0x132) &&
(((regecc & 0x03FF0000)>>16) != 0x36))
result |= 0x02;
@ -959,9 +959,9 @@ static void mac_setting_calibration(struct adapter *adapt, u32 *mac_reg, u32 *ba
usb_write8(adapt, mac_reg[i], 0x3F);
for (i = 1; i < (IQK_MAC_REG_NUM - 1); i++) {
usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT3)));
usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(3))));
}
usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT5)));
usb_write8(adapt, mac_reg[i], (u8)(backup[i]&(~BIT(5))));
}
static void path_a_standby(struct adapter *adapt)
@ -1117,15 +1117,15 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
}
/* BB setting */
phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT24, 0x00);
phy_set_bb_reg(adapt, rFPGA0_RFMOD, BIT(24), 0x00);
phy_set_bb_reg(adapt, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
phy_set_bb_reg(adapt, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
phy_set_bb_reg(adapt, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(10), 0x01);
phy_set_bb_reg(adapt, rFPGA0_XAB_RFInterfaceSW, BIT(26), 0x01);
phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);
phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);
if (is2t) {
phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord,

20
drivers/staging/rtl8188eu/hal/rtl8188e_cmd.c
View file

@ -149,7 +149,7 @@ void rtl8188e_Add_RateATid(struct adapter *pAdapter, u32 bitmap, u8 arg, u8 rssi
init_rate = get_highest_rate_idx(bitmap&0x0fffffff)&0x3f;
shortGIrate = (arg&BIT(5)) ? true : false;
shortGIrate = (arg & BIT(5)) ? true : false;
if (shortGIrate)
init_rate |= BIT(6);
@ -577,23 +577,23 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus)
/* Do not set TSF again here or vWiFi beacon DMA INT will not work. */
/* Set REG_CR bit 8. DMA beacon by SW. */
haldata->RegCR_1 |= BIT0;
haldata->RegCR_1 |= BIT(0);
usb_write8(adapt, REG_CR+1, haldata->RegCR_1);
/* Disable Hw protection for a time which revserd for Hw sending beacon. */
/* Fix download reserved page packet fail that access collision with the protection time. */
/* 2010.05.11. Added by tynli. */
usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)&(~BIT(3)));
usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)|BIT(4));
usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL) | BIT(4));
if (haldata->RegFwHwTxQCtrl&BIT6) {
if (haldata->RegFwHwTxQCtrl & BIT(6)) {
DBG_88E("HalDownloadRSVDPage(): There is an Adapter is sending beacon.\n");
bSendBeacon = true;
}
/* Set FWHW_TXQ_CTRL 0x422[6]=0 to tell Hw the packet is not a real beacon frame. */
usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl&(~BIT6)));
haldata->RegFwHwTxQCtrl &= (~BIT6);
usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl&(~BIT(6))));
haldata->RegFwHwTxQCtrl &= (~BIT(6));
/* Clear beacon valid check bit. */
rtw_hal_set_hwreg(adapt, HW_VAR_BCN_VALID, NULL);
@ -626,7 +626,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus)
/* */
/* Enable Bcn */
usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)|BIT(3));
usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL) | BIT(3));
usb_write8(adapt, REG_BCN_CTRL, usb_read8(adapt, REG_BCN_CTRL)&(~BIT(4)));
/* To make sure that if there exists an adapter which would like to send beacon. */
@ -635,8 +635,8 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus)
/* the beacon cannot be sent by HW. */
/* 2010.06.23. Added by tynli. */
if (bSendBeacon) {
usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl|BIT6));
haldata->RegFwHwTxQCtrl |= BIT6;
usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl | BIT(6)));
haldata->RegFwHwTxQCtrl |= BIT(6);
}
/* Update RSVD page location H2C to Fw. */
@ -647,7 +647,7 @@ void rtl8188e_set_FwJoinBssReport_cmd(struct adapter *adapt, u8 mstatus)
/* Do not enable HW DMA BCN or it will cause Pcie interface hang by timing issue. 2011.11.24. by tynli. */
/* Clear CR[8] or beacon packet will not be send to TxBuf anymore. */
haldata->RegCR_1 &= (~BIT0);
haldata->RegCR_1 &= (~BIT(0));
usb_write8(adapt, REG_CR+1, haldata->RegCR_1);
}
}

24
drivers/staging/rtl8188eu/hal/rtl8188e_hal_init.c
View file

@ -106,8 +106,8 @@ void _8051Reset88E(struct adapter *padapter)
u8 u1bTmp;
u1bTmp = usb_read8(padapter, REG_SYS_FUNC_EN+1);
usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT2));
usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT2));
usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp&(~BIT(2)));
usb_write8(padapter, REG_SYS_FUNC_EN+1, u1bTmp|(BIT(2)));
DBG_88E("=====> _8051Reset88E(): 8051 reset success .\n");
}
@ -184,10 +184,10 @@ static void hal_notch_filter_8188e(struct adapter *adapter, bool enable)
{
if (enable) {
DBG_88E("Enable notch filter\n");
usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT1);
usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) | BIT(1));
} else {
DBG_88E("Disable notch filter\n");
usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT1);
usb_write8(adapter, rOFDM0_RxDSP+1, usb_read8(adapter, rOFDM0_RxDSP+1) & ~BIT(1));
}
}
void rtl8188e_set_hal_ops(struct hal_ops *pHalFunc)
@ -372,7 +372,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G,
pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_HT20_DIFF;
} else {
pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
}
@ -380,7 +380,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G,
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_24G_OFDM_DIFF;
} else {
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
}
pwrInfo24G->CCK_Diff[rfPath][TxCount] = 0;
@ -390,7 +390,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G,
pwrInfo24G->BW40_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
} else {
pwrInfo24G->BW40_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->BW40_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->BW40_Diff[rfPath][TxCount] |= 0xF0;
}
@ -398,7 +398,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G,
pwrInfo24G->BW20_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
} else {
pwrInfo24G->BW20_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->BW20_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->BW20_Diff[rfPath][TxCount] |= 0xF0;
}
eeAddr++;
@ -407,7 +407,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G,
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
} else {
pwrInfo24G->OFDM_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0xf0)>>4;
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->OFDM_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->OFDM_Diff[rfPath][TxCount] |= 0xF0;
}
@ -415,7 +415,7 @@ static void Hal_ReadPowerValueFromPROM_8188E(struct txpowerinfo24g *pwrInfo24G,
pwrInfo24G->CCK_Diff[rfPath][TxCount] = EEPROM_DEFAULT_DIFF;
} else {
pwrInfo24G->CCK_Diff[rfPath][TxCount] = (PROMContent[eeAddr]&0x0f);
if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT3) /* 4bit sign number to 8 bit sign number */
if (pwrInfo24G->CCK_Diff[rfPath][TxCount] & BIT(3)) /* 4bit sign number to 8 bit sign number */
pwrInfo24G->CCK_Diff[rfPath][TxCount] |= 0xF0;
}
eeAddr++;
@ -485,13 +485,13 @@ void Hal_ReadPowerSavingMode88E(struct adapter *padapter, u8 *hwinfo, bool AutoL
/* hw power down mode selection , 0:rf-off / 1:power down */
if (padapter->registrypriv.hwpdn_mode == 2)
padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT4);
padapter->pwrctrlpriv.bHWPowerdown = (hwinfo[EEPROM_RF_FEATURE_OPTION_88E] & BIT(4));
else
padapter->pwrctrlpriv.bHWPowerdown = padapter->registrypriv.hwpdn_mode;
/* decide hw if support remote wakeup function */
/* if hw supported, 8051 (SIE) will generate WeakUP signal(D+/D- toggle) when autoresume */
padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT1) ? true : false;
padapter->pwrctrlpriv.bSupportRemoteWakeup = (hwinfo[EEPROM_USB_OPTIONAL_FUNCTION0] & BIT(1)) ? true : false;
DBG_88E("%s...bHWPwrPindetect(%x)-bHWPowerdown(%x) , bSupportRemoteWakeup(%x)\n", __func__,
padapter->pwrctrlpriv.bHWPwrPindetect, padapter->pwrctrlpriv.bHWPowerdown , padapter->pwrctrlpriv.bSupportRemoteWakeup);

6
drivers/staging/rtl8188eu/hal/rtl8188eu_led.c
View file

@ -36,7 +36,7 @@ void SwLedOn(struct adapter *padapter, struct LED_871x *pLed)
if (padapter->bSurpriseRemoved || padapter->bDriverStopped)
return;
LedCfg = usb_read8(padapter, REG_LEDCFG2);
usb_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0)|BIT5|BIT6); /* SW control led0 on. */
usb_write8(padapter, REG_LEDCFG2, (LedCfg&0xf0) | BIT(5) | BIT(6)); /* SW control led0 on. */
pLed->bLedOn = true;
}
@ -55,12 +55,12 @@ void SwLedOff(struct adapter *padapter, struct LED_871x *pLed)
if (pHalData->bLedOpenDrain) {
/* Open-drain arrangement for controlling the LED) */
LedCfg &= 0x90; /* Set to software control. */
usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3));
usb_write8(padapter, REG_LEDCFG2, (LedCfg | BIT(3)));
LedCfg = usb_read8(padapter, REG_MAC_PINMUX_CFG);
LedCfg &= 0xFE;
usb_write8(padapter, REG_MAC_PINMUX_CFG, LedCfg);
} else {
usb_write8(padapter, REG_LEDCFG2, (LedCfg|BIT3|BIT5|BIT6));
usb_write8(padapter, REG_LEDCFG2, (LedCfg | BIT(3) | BIT(5) | BIT(6)));
}
exit:
pLed->bLedOn = false;

56
drivers/staging/rtl8188eu/hal/usb_halinit.c
View file

@ -607,7 +607,7 @@ static void _InitBeaconParameters(struct adapter *Adapter)
static void _BeaconFunctionEnable(struct adapter *Adapter,
bool Enable, bool Linked)
{
usb_write8(Adapter, REG_BCN_CTRL, (BIT4 | BIT3 | BIT1));
usb_write8(Adapter, REG_BCN_CTRL, (BIT(4) | BIT(3) | BIT(1)));
usb_write8(Adapter, REG_RD_CTRL+1, 0x6F);
}
@ -632,8 +632,8 @@ static void _InitAntenna_Selection(struct adapter *Adapter)
return;
DBG_88E("==> %s ....\n", __func__);
usb_write32(Adapter, REG_LEDCFG0, usb_read32(Adapter, REG_LEDCFG0)|BIT23);
phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
usb_write32(Adapter, REG_LEDCFG0, usb_read32(Adapter, REG_LEDCFG0) | BIT(23));
phy_set_bb_reg(Adapter, rFPGA0_XAB_RFParameter, BIT(13), 0x01);
if (phy_query_bb_reg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300) == Antenna_A)
haldata->CurAntenna = Antenna_A;
@ -664,13 +664,13 @@ enum rt_rf_power_state RfOnOffDetect(struct adapter *adapt)
if (adapt->pwrctrlpriv.bHWPowerdown) {
val8 = usb_read8(adapt, REG_HSISR);
DBG_88E("pwrdown, 0x5c(BIT7)=%02x\n", val8);
rfpowerstate = (val8 & BIT7) ? rf_off : rf_on;
DBG_88E("pwrdown, 0x5c(BIT(7))=%02x\n", val8);
rfpowerstate = (val8 & BIT(7)) ? rf_off : rf_on;
} else { /* rf on/off */
usb_write8(adapt, REG_MAC_PINMUX_CFG, usb_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT3));
usb_write8(adapt, REG_MAC_PINMUX_CFG, usb_read8(adapt, REG_MAC_PINMUX_CFG)&~(BIT(3)));
val8 = usb_read8(adapt, REG_GPIO_IO_SEL);
DBG_88E("GPIO_IN=%02x\n", val8);
rfpowerstate = (val8 & BIT3) ? rf_on : rf_off;
rfpowerstate = (val8 & BIT(3)) ? rf_on : rf_off;
}
return rfpowerstate;
} /* HalDetectPwrDownMode */
@ -805,7 +805,7 @@ static u32 rtl8188eu_hal_init(struct adapter *Adapter)
/* Enable TX Report */
/* Enable Tx Report Timer */
value8 = usb_read8(Adapter, REG_TX_RPT_CTRL);
usb_write8(Adapter, REG_TX_RPT_CTRL, (value8|BIT1|BIT0));
usb_write8(Adapter, REG_TX_RPT_CTRL, (value8 | BIT(1) | BIT(0)));
/* Set MAX RPT MACID */
usb_write8(Adapter, REG_TX_RPT_CTRL+1, 2);/* FOR sta mode ,0: bc/mc ,1:AP */
/* Tx RPT Timer. Unit: 32us */
@ -898,7 +898,7 @@ HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_LCK);
usb_write8(Adapter, REG_USB_HRPWM, 0);
/* ack for xmit mgmt frames. */
usb_write32(Adapter, REG_FWHW_TXQ_CTRL, usb_read32(Adapter, REG_FWHW_TXQ_CTRL)|BIT(12));
usb_write32(Adapter, REG_FWHW_TXQ_CTRL, usb_read32(Adapter, REG_FWHW_TXQ_CTRL) | BIT(12));
exit:
HAL_INIT_PROFILE_TAG(HAL_INIT_STAGES_END);
@ -918,7 +918,7 @@ static void CardDisableRTL8188EU(struct adapter *Adapter)
/* Stop Tx Report Timer. 0x4EC[Bit1]=b'0 */
val8 = usb_read8(Adapter, REG_TX_RPT_CTRL);
usb_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT1));
usb_write8(Adapter, REG_TX_RPT_CTRL, val8&(~BIT(1)));
/* stop rx */
usb_write8(Adapter, REG_CR, 0x0);
@ -944,7 +944,7 @@ static void CardDisableRTL8188EU(struct adapter *Adapter)
/* YJ,add,111212 */
/* Disable 32k */
val8 = usb_read8(Adapter, REG_32K_CTRL);
usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT0));
usb_write8(Adapter, REG_32K_CTRL, val8&(~BIT(0)));
/* Card disable power action flow */
rtl88eu_pwrseqcmdparsing(Adapter, PWR_CUT_ALL_MSK,
@ -953,9 +953,9 @@ static void CardDisableRTL8188EU(struct adapter *Adapter)
/* Reset MCU IO Wrapper */
val8 = usb_read8(Adapter, REG_RSV_CTRL+1);
usb_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT3)));
usb_write8(Adapter, REG_RSV_CTRL+1, (val8&(~BIT(3))));
val8 = usb_read8(Adapter, REG_RSV_CTRL+1);
usb_write8(Adapter, REG_RSV_CTRL+1, val8|BIT3);
usb_write8(Adapter, REG_RSV_CTRL+1, val8 | BIT(3));
/* YJ,test add, 111207. For Power Consumption. */
val8 = usb_read8(Adapter, GPIO_IN);
@ -1171,10 +1171,10 @@ static void ResumeTxBeacon(struct adapter *adapt)
/* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
/* which should be read from register to a global variable. */
usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT6);
haldata->RegFwHwTxQCtrl |= BIT6;
usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) | BIT(6));
haldata->RegFwHwTxQCtrl |= BIT(6);
usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0xff);
haldata->RegReg542 |= BIT0;
haldata->RegReg542 |= BIT(0);
usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
}
@ -1185,10 +1185,10 @@ static void StopTxBeacon(struct adapter *adapt)
/* 2010.03.01. Marked by tynli. No need to call workitem beacause we record the value */
/* which should be read from register to a global variable. */
usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT6));
haldata->RegFwHwTxQCtrl &= (~BIT6);
usb_write8(adapt, REG_FWHW_TXQ_CTRL+2, (haldata->RegFwHwTxQCtrl) & (~BIT(6)));
haldata->RegFwHwTxQCtrl &= (~BIT(6));
usb_write8(adapt, REG_TBTT_PROHIBIT+1, 0x64);
haldata->RegReg542 &= ~(BIT0);
haldata->RegReg542 &= ~(BIT(0));
usb_write8(adapt, REG_TBTT_PROHIBIT+2, haldata->RegReg542);
/* todo: CheckFwRsvdPageContent(Adapter); 2010.06.23. Added by tynli. */
@ -1200,7 +1200,7 @@ static void hw_var_set_opmode(struct adapter *Adapter, u8 variable, u8 *val)
u8 mode = *((u8 *)val);
/* disable Port0 TSF update */
usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(4));
usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4));
/* set net_type */
val8 = usb_read8(Adapter, MSR)&0x0c;
@ -1378,7 +1378,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
usb_write32(Adapter, REG_TSFTR+4, tsf>>32);
/* enable related TSF function */
usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(3));
usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(3));
if (((pmlmeinfo->state&0x03) == WIFI_FW_ADHOC_STATE) || ((pmlmeinfo->state&0x03) == WIFI_FW_AP_STATE))
ResumeTxBeacon(Adapter);
@ -1403,10 +1403,10 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
/* reset TSF */
usb_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0)|BIT(1)));
usb_write8(Adapter, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
/* disable update TSF */
usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(4));
usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4));
break;
case HW_VAR_MLME_SITESURVEY:
if (*((u8 *)val)) { /* under sitesurvey */
@ -1418,7 +1418,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
usb_write16(Adapter, REG_RXFLTMAP2, 0x00);
/* disable update TSF */
usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL)|BIT(4));
usb_write8(Adapter, REG_BCN_CTRL, usb_read8(Adapter, REG_BCN_CTRL) | BIT(4));
} else { /* sitesurvey done */
struct mlme_ext_priv *pmlmeext = &Adapter->mlmeextpriv;
struct mlme_ext_info *pmlmeinfo = &(pmlmeext->mlmext_info);
@ -1578,7 +1578,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
}
break;
case HW_VAR_CAM_INVALID_ALL:
usb_write32(Adapter, RWCAM, BIT(31)|BIT(30));
usb_write32(Adapter, RWCAM, BIT(31) | BIT(30));
break;
case HW_VAR_CAM_WRITE:
{
@ -1795,7 +1795,7 @@ static void SetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
break;
case HW_VAR_BCN_VALID:
/* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2, write 1 to clear, Clear by sw */
usb_write8(Adapter, REG_TDECTRL+2, usb_read8(Adapter, REG_TDECTRL+2) | BIT0);
usb_write8(Adapter, REG_TDECTRL+2, usb_read8(Adapter, REG_TDECTRL+2) | BIT(0));
break;
default:
break;
@ -1815,7 +1815,7 @@ static void GetHwReg8188EU(struct adapter *Adapter, u8 variable, u8 *val)
break;
case HW_VAR_BCN_VALID:
/* BCN_VALID, BIT16 of REG_TDECTRL = BIT0 of REG_TDECTRL+2 */
val[0] = (BIT0 & usb_read8(Adapter, REG_TDECTRL+2)) ? true : false;
val[0] = (BIT(0) & usb_read8(Adapter, REG_TDECTRL+2)) ? true : false;
break;
case HW_VAR_DM_FLAG:
val[0] = podmpriv->SupportAbility;
@ -2052,7 +2052,7 @@ static void SetBeaconRelatedRegisters8188EUsb(struct adapter *adapt)
ResumeTxBeacon(adapt);
usb_write8(adapt, bcn_ctrl_reg, usb_read8(adapt, bcn_ctrl_reg)|BIT(1));
usb_write8(adapt, bcn_ctrl_reg, usb_read8(adapt, bcn_ctrl_reg) | BIT(1));
}
static void rtl8188eu_init_default_value(struct adapter *adapt)

14
drivers/staging/rtl8188eu/include/Hal8188EPhyCfg.h
View file

@ -87,13 +87,13 @@ enum rf_radio_path {
enum wireless_mode {
WIRELESS_MODE_UNKNOWN = 0x00,
WIRELESS_MODE_A = BIT2,
WIRELESS_MODE_B = BIT0,
WIRELESS_MODE_G = BIT1,
WIRELESS_MODE_AUTO = BIT5,
WIRELESS_MODE_N_24G = BIT3,
WIRELESS_MODE_N_5G = BIT4,
WIRELESS_MODE_AC = BIT6
WIRELESS_MODE_A = BIT(2),
WIRELESS_MODE_B = BIT(0),
WIRELESS_MODE_G = BIT(1),
WIRELESS_MODE_AUTO = BIT(5),
WIRELESS_MODE_N_24G = BIT(3),
WIRELESS_MODE_N_5G = BIT(4),
WIRELESS_MODE_AC = BIT(6)
};
enum phy_rate_tx_offset_area {

16
drivers/staging/rtl8188eu/include/hal_intf.h
View file

@ -25,10 +25,10 @@
#include <Hal8188EPhyCfg.h>
enum RTL871X_HCI_TYPE {
RTW_PCIE = BIT0,
RTW_USB = BIT1,
RTW_SDIO = BIT2,
RTW_GSPI = BIT3,
RTW_PCIE = BIT(0),
RTW_USB = BIT(1),
RTW_SDIO = BIT(2),
RTW_GSPI = BIT(3),
};
enum _CHIP_TYPE {
@ -226,10 +226,10 @@ enum rt_eeprom_type {
};
#define RF_CHANGE_BY_INIT 0
#define RF_CHANGE_BY_IPS BIT28
#define RF_CHANGE_BY_PS BIT29
#define RF_CHANGE_BY_HW BIT30
#define RF_CHANGE_BY_SW BIT31
#define RF_CHANGE_BY_IPS BIT(28)
#define RF_CHANGE_BY_PS BIT(29)
#define RF_CHANGE_BY_HW BIT(30)
#define RF_CHANGE_BY_SW BIT(31)
enum hardware_type {
HARDWARE_TYPE_RTL8188EU,

90
drivers/staging/rtl8188eu/include/odm.h
View file

@ -414,31 +414,31 @@ enum odm_common_info_def {
enum odm_ability_def {
/* BB ODM section BIT 0-15 */
ODM_BB_DIG = BIT0,
ODM_BB_RA_MASK = BIT1,
ODM_BB_DYNAMIC_TXPWR = BIT2,
ODM_BB_FA_CNT = BIT3,
ODM_BB_RSSI_MONITOR = BIT4,
ODM_BB_CCK_PD = BIT5,
ODM_BB_ANT_DIV = BIT6,
ODM_BB_PWR_SAVE = BIT7,
ODM_BB_PWR_TRA = BIT8,
ODM_BB_RATE_ADAPTIVE = BIT9,
ODM_BB_PATH_DIV = BIT10,
ODM_BB_PSD = BIT11,
ODM_BB_RXHP = BIT12,
ODM_BB_DIG = BIT(0),
ODM_BB_RA_MASK = BIT(1),
ODM_BB_DYNAMIC_TXPWR = BIT(2),
ODM_BB_FA_CNT = BIT(3),
ODM_BB_RSSI_MONITOR = BIT(4),
ODM_BB_CCK_PD = BIT(5),
ODM_BB_ANT_DIV = BIT(6),
ODM_BB_PWR_SAVE = BIT(7),
ODM_BB_PWR_TRA = BIT(8),
ODM_BB_RATE_ADAPTIVE = BIT(9),
ODM_BB_PATH_DIV = BIT(10),
ODM_BB_PSD = BIT(11),
ODM_BB_RXHP = BIT(12),
/* MAC DM section BIT 16-23 */
ODM_MAC_EDCA_TURBO = BIT16,
ODM_MAC_EARLY_MODE = BIT17,
ODM_MAC_EDCA_TURBO = BIT(16),
ODM_MAC_EARLY_MODE = BIT(17),
/* RF ODM section BIT 24-31 */
ODM_RF_TX_PWR_TRACK = BIT24,
ODM_RF_RX_GAIN_TRACK = BIT25,
ODM_RF_CALIBRATION = BIT26,
ODM_RF_TX_PWR_TRACK = BIT(24),
ODM_RF_RX_GAIN_TRACK = BIT(25),
ODM_RF_CALIBRATION = BIT(26),
};
#define ODM_RTL8188E BIT4
#define ODM_RTL8188E BIT(4)
/* ODM_CMNINFO_CUT_VER */
enum odm_cut_version {
@ -460,14 +460,14 @@ enum odm_fab_Version {
/* ODM_CMNINFO_RF_TYPE */
/* For example 1T2R (A+AB = BIT0|BIT4|BIT5) */
enum odm_rf_path {
ODM_RF_TX_A = BIT0,
ODM_RF_TX_B = BIT1,
ODM_RF_TX_C = BIT2,
ODM_RF_TX_D = BIT3,
ODM_RF_RX_A = BIT4,
ODM_RF_RX_B = BIT5,
ODM_RF_RX_C = BIT6,
ODM_RF_RX_D = BIT7,
ODM_RF_TX_A = BIT(0),
ODM_RF_TX_B = BIT(1),
ODM_RF_TX_C = BIT(2),
ODM_RF_TX_D = BIT(3),
ODM_RF_RX_A = BIT(4),
ODM_RF_RX_B = BIT(5),
ODM_RF_RX_C = BIT(6),
ODM_RF_RX_D = BIT(7),
};
enum odm_rf_type {
@ -498,33 +498,33 @@ enum odm_bt_coexist {
/* ODM_CMNINFO_OP_MODE */
enum odm_operation_mode {
ODM_NO_LINK = BIT0,
ODM_LINK = BIT1,
ODM_SCAN = BIT2,
ODM_POWERSAVE = BIT3,
ODM_AP_MODE = BIT4,
ODM_CLIENT_MODE = BIT5,
ODM_AD_HOC = BIT6,
ODM_WIFI_DIRECT = BIT7,
ODM_WIFI_DISPLAY = BIT8,
ODM_NO_LINK = BIT(0),
ODM_LINK = BIT(1),
ODM_SCAN = BIT(2),
ODM_POWERSAVE = BIT(3),
ODM_AP_MODE = BIT(4),
ODM_CLIENT_MODE = BIT(5),
ODM_AD_HOC = BIT(6),
ODM_WIFI_DIRECT = BIT(7),
ODM_WIFI_DISPLAY = BIT(8),
};
/* ODM_CMNINFO_WM_MODE */
enum odm_wireless_mode {
ODM_WM_UNKNOW = 0x0,
ODM_WM_B = BIT0,
ODM_WM_G = BIT1,
ODM_WM_A = BIT2,
ODM_WM_N24G = BIT3,
ODM_WM_N5G = BIT4,
ODM_WM_AUTO = BIT5,
ODM_WM_AC = BIT6,
ODM_WM_B = BIT(0),
ODM_WM_G = BIT(1),
ODM_WM_A = BIT(2),
ODM_WM_N24G = BIT(3),
ODM_WM_N5G = BIT(4),
ODM_WM_AUTO = BIT(5),
ODM_WM_AC = BIT(6),
};
/* ODM_CMNINFO_BAND */
enum odm_band_type {
ODM_BAND_2_4G = BIT0,
ODM_BAND_5G = BIT1,
ODM_BAND_2_4G = BIT(0),
ODM_BAND_5G = BIT(1),
};
/* ODM_CMNINFO_SEC_CHNL_OFFSET */

42
drivers/staging/rtl8188eu/include/odm_debug.h
View file

@ -57,30 +57,30 @@
/* Define the tracing components */
/* BB Functions */
#define ODM_COMP_DIG BIT0
#define ODM_COMP_RA_MASK BIT1
#define ODM_COMP_DYNAMIC_TXPWR BIT2
#define ODM_COMP_FA_CNT BIT3
#define ODM_COMP_RSSI_MONITOR BIT4
#define ODM_COMP_CCK_PD BIT5
#define ODM_COMP_ANT_DIV BIT6
#define ODM_COMP_PWR_SAVE BIT7
#define ODM_COMP_PWR_TRA BIT8
#define ODM_COMP_RATE_ADAPTIVE BIT9
#define ODM_COMP_PATH_DIV BIT10
#define ODM_COMP_PSD BIT11
#define ODM_COMP_DYNAMIC_PRICCA BIT12
#define ODM_COMP_RXHP BIT13
#define ODM_COMP_DIG BIT(0)
#define ODM_COMP_RA_MASK BIT(1)
#define ODM_COMP_DYNAMIC_TXPWR BIT(2)
#define ODM_COMP_FA_CNT BIT(3)
#define ODM_COMP_RSSI_MONITOR BIT(4)
#define ODM_COMP_CCK_PD BIT(5)
#define ODM_COMP_ANT_DIV BIT(6)
#define ODM_COMP_PWR_SAVE BIT(7)
#define ODM_COMP_PWR_TRA BIT(8)
#define ODM_COMP_RATE_ADAPTIVE BIT(9)
#define ODM_COMP_PATH_DIV BIT(10)
#define ODM_COMP_PSD BIT(11)
#define ODM_COMP_DYNAMIC_PRICCA BIT(12)
#define ODM_COMP_RXHP BIT(13)
/* MAC Functions */
#define ODM_COMP_EDCA_TURBO BIT16
#define ODM_COMP_EARLY_MODE BIT17
#define ODM_COMP_EDCA_TURBO BIT(16)
#define ODM_COMP_EARLY_MODE BIT(17)
/* RF Functions */
#define ODM_COMP_TX_PWR_TRACK BIT24
#define ODM_COMP_RX_GAIN_TRACK BIT25
#define ODM_COMP_CALIBRATION BIT26
#define ODM_COMP_TX_PWR_TRACK BIT(24)
#define ODM_COMP_RX_GAIN_TRACK BIT(25)
#define ODM_COMP_CALIBRATION BIT(26)
/* Common Functions */
#define ODM_COMP_COMMON BIT30
#define ODM_COMP_INIT BIT31
#define ODM_COMP_COMMON BIT(30)
#define ODM_COMP_INIT BIT(31)
/*------------------------Export Marco Definition---------------------------*/
#define RT_PRINTK(fmt, args...) \

2
drivers/staging/rtl8188eu/include/odm_reg.h
View file

@ -112,7 +112,7 @@
/* Bitmap Definition */
/* */
#define BIT_FA_RESET BIT0
#define BIT_FA_RESET BIT(0)

39
drivers/staging/rtl8188eu/include/osdep_service.h
View file

@ -75,45 +75,6 @@ static inline int rtw_netif_queue_stopped(struct net_device *pnetdev)
netif_tx_queue_stopped(netdev_get_tx_queue(pnetdev, 3));
}
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
#define BIT32 0x0100000000
#define BIT33 0x0200000000
#define BIT34 0x0400000000
#define BIT35 0x0800000000
#define BIT36 0x1000000000
int RTW_STATUS_CODE(int error_code);
#define rtw_update_mem_stat(flag, sz) do {} while (0)

84
drivers/staging/rtl8188eu/include/pwrseq.h
View file

@ -65,31 +65,31 @@
* comment here
*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/* wait till 0x04[17] = 1 power ready*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0|BIT1, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0) | BIT(1), 0}, \
/* 0x02[1:0] = 0 reset BB*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
/*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
/* 0x04[15] = 0 disable HWPDN (control by DRV)*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4) | BIT(3), 0}, \
/*0x04[12:11] = 2b'00 disable WL suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*0x04[8] = 1 polling until return 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(0), 0}, \
/*wait till 0x04[8] = 0*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
/*LDO normal mode*/ \
{0x0074, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
/*SDIO Driving*/
#define RTL8188E_TRANS_ACT_TO_CARDEMU \
@ -102,13 +102,13 @@
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, \
/*0x1F[7:0] = 0 turn off RF*/ \
{0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
/*LDO Sleep mode*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
/*0x04[9] = 1 turn off MAC by HW state machine*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(1), 0}, \
/*wait till 0x04[9] = 0 polling until return 0 to disable*/
#define RTL8188E_TRANS_CARDEMU_TO_SUS \
@ -119,28 +119,28 @@
*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \
PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
/* 0x04[12:11] = 2b'01enable WL suspend */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3) | BIT(4)}, \
/* 0x04[12:11] = 2b'11enable WL suspend for PCIe */ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, 0xFF, BIT7}, \
PWR_CMD_WRITE, 0xFF, BIT(7)}, \
/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT4, 0}, \
PWR_CMD_WRITE, BIT(4), 0}, \
/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT4, BIT4}, \
PWR_CMD_WRITE, BIT(4), BIT(4)}, \
/*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, \
/*wait power state to suspend*/
#define RTL8188E_TRANS_SUS_TO_CARDEMU \
@ -150,13 +150,13 @@
* comments here
*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/*wait power state to suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
/*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
@ -166,11 +166,11 @@
* comments here
*/ \
{0x0026, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
/*0x24[23] = 2b'01 schmit trigger */ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT3|BIT4, BIT3}, \
PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
/*0x04[12:11] = 2b'01 enable WL suspend*/ \
{0x0007, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
@ -178,16 +178,16 @@
/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
{0x0041, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, \
PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, \
PWR_CMD_WRITE, BIT4, 0}, \
PWR_CMD_WRITE, BIT(4), 0}, \
/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
{0xfe10, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
/*Set USB suspend enable local register 0xfe10[4]=1 */ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, BIT0}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), BIT(0)}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, 0}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), 0}, \
/*wait power state to suspend*/
#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
@ -197,13 +197,13 @@
* comments here
*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT0, 0}, \
PWR_BASEADDR_SDIO, PWR_CMD_WRITE, BIT(0), 0}, \
/*Set SDIO suspend local register*/ \
{0x0086, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT1, BIT1}, \
PWR_BASEADDR_SDIO, PWR_CMD_POLLING, BIT(1), BIT(1)}, \
/*wait power state to suspend*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
/*0x04[12:11] = 2b'01enable WL suspend*/
#define RTL8188E_TRANS_CARDEMU_TO_PDN \
@ -213,10 +213,10 @@
* comments here
*/ \
{0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
/* 0x04[16] = 0*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
/* 0x04[15] = 1*/
#define RTL8188E_TRANS_PDN_TO_CARDEMU \
@ -226,7 +226,7 @@
* comments here
*/ \
{0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(7), 0}, \
/* 0x04[15] = 0*/
/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
@ -251,7 +251,7 @@
PWR_BASEADDR_MAC, PWR_CMD_POLLING, 0xFF, 0}, \
/*Should be zero if no packet is transmitting*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(0), 0}, \
/*CCK and OFDM are disabled,and clock are gated*/ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, \
@ -259,9 +259,9 @@
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0x3F},/*Reset MAC TRX*/ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*check if removed later*/\
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), 0},/*check if removed later*/\
{0x0553, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT5, BIT5}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
/*Respond TxOK to scheduler*/
@ -280,22 +280,22 @@
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, /*Delay*/ \
{0x0008, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(4), 0}, \
/* 0x08[4] = 0 switch TSF to 40M */ \
{0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT(7), 0}, \
/* Polling 0x109[7]=0 TSF in 40M */ \
{0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \
/* 0x29[7:6] = 2b'00 enable BB clock */ \
{0x0101, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
/* 0x101[1] = 1 */ \
{0x0100, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0xFF}, \
/* 0x100[7:0] = 0xFF enable WMAC TRX */ \
{0x0002, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT1|BIT0}, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
/* 0x02[1:0] = 2b'11 enable BB macro */ \
{0x0522, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, \
PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/

411
drivers/staging/rtl8188eu/include/rtl8188e_spec.h
View file

@ -19,39 +19,6 @@
#ifndef __RTL8188E_SPEC_H__
#define __RTL8188E_SPEC_H__
#define BIT0 0x00000001
#define BIT1 0x00000002
#define BIT2 0x00000004
#define BIT3 0x00000008
#define BIT4 0x00000010
#define BIT5 0x00000020
#define BIT6 0x00000040
#define BIT7 0x00000080
#define BIT8 0x00000100
#define BIT9 0x00000200
#define BIT10 0x00000400
#define BIT11 0x00000800
#define BIT12 0x00001000
#define BIT13 0x00002000
#define BIT14 0x00004000
#define BIT15 0x00008000
#define BIT16 0x00010000
#define BIT17 0x00020000
#define BIT18 0x00040000
#define BIT19 0x00080000
#define BIT20 0x00100000
#define BIT21 0x00200000
#define BIT22 0x00400000
#define BIT23 0x00800000
#define BIT24 0x01000000
#define BIT25 0x02000000
#define BIT26 0x04000000
#define BIT27 0x08000000
#define BIT28 0x10000000
#define BIT29 0x20000000
#define BIT30 0x40000000
#define BIT31 0x80000000
/* 8192C Regsiter offset definition */
#define HAL_PS_TIMER_INT_DELAY 50 /* 50 microseconds */
@ -477,14 +444,14 @@
#define MAX_MSS_DENSITY_1T 0x0A
/* EEPROM enable when set 1 */
#define CmdEEPROM_En BIT5
#define CmdEEPROM_En BIT(5)
/* System EEPROM select, 0: boot from E-FUSE, 1: The EEPROM used is 9346 */
#define CmdEERPOMSEL BIT4
#define Cmd9346CR_9356SEL BIT4
#define CmdEERPOMSEL BIT(4)
#define Cmd9346CR_9356SEL BIT(4)
/* 8192C GPIO MUX Configuration Register (offset 0x40, 4 byte) */
#define GPIOSEL_GPIO 0
#define GPIOSEL_ENBT BIT5
#define GPIOSEL_ENBT BIT(5)
/* 8192C GPIO PIN Control Register (offset 0x44, 4 byte) */
/* GPIO pins input value */
@ -497,18 +464,18 @@
#define GPIO_MOD (REG_GPIO_PIN_CTRL+3)
/* 8723/8188E Host System Interrupt Mask Register (offset 0x58, 32 byte) */
#define HSIMR_GPIO12_0_INT_EN BIT0
#define HSIMR_SPS_OCP_INT_EN BIT5
#define HSIMR_RON_INT_EN BIT6
#define HSIMR_PDN_INT_EN BIT7
#define HSIMR_GPIO9_INT_EN BIT25
#define HSIMR_GPIO12_0_INT_EN BIT(0)
#define HSIMR_SPS_OCP_INT_EN BIT(5)
#define HSIMR_RON_INT_EN BIT(6)
#define HSIMR_PDN_INT_EN BIT(7)
#define HSIMR_GPIO9_INT_EN BIT(25)
/* 8723/8188E Host System Interrupt Status Register (offset 0x5C, 32 byte) */
#define HSISR_GPIO12_0_INT BIT0
#define HSISR_SPS_OCP_INT BIT5
#define HSISR_RON_INT_EN BIT6
#define HSISR_PDNINT BIT7
#define HSISR_GPIO9_INT BIT25
#define HSISR_GPIO12_0_INT BIT(0)
#define HSISR_SPS_OCP_INT BIT(5)
#define HSISR_RON_INT_EN BIT(6)
#define HSISR_PDNINT BIT(7)
#define HSISR_GPIO9_INT BIT(25)
/* 8192C (MSR) Media Status Register (Offset 0x4C, 8 bits) */
/*
@ -533,51 +500,51 @@ Default: 00b.
/* 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits) */
/* IOL config for REG_FDHM0(Reg0x88) */
#define CMD_INIT_LLT BIT0
#define CMD_READ_EFUSE_MAP BIT1
#define CMD_EFUSE_PATCH BIT2
#define CMD_IOCONFIG BIT3
#define CMD_INIT_LLT_ERR BIT4
#define CMD_READ_EFUSE_MAP_ERR BIT5
#define CMD_EFUSE_PATCH_ERR BIT6
#define CMD_IOCONFIG_ERR BIT7
#define CMD_INIT_LLT BIT(0)
#define CMD_READ_EFUSE_MAP BIT(1)
#define CMD_EFUSE_PATCH BIT(2)
#define CMD_IOCONFIG BIT(3)
#define CMD_INIT_LLT_ERR BIT(4)
#define CMD_READ_EFUSE_MAP_ERR BIT(5)
#define CMD_EFUSE_PATCH_ERR BIT(6)
#define CMD_IOCONFIG_ERR BIT(7)
/* 6. Adaptive Control Registers (Offset: 0x0160 - 0x01CF) */
/* 8192C Response Rate Set Register (offset 0x181, 24bits) */
#define RRSR_1M BIT0
#define RRSR_2M BIT1
#define RRSR_5_5M BIT2
#define RRSR_11M BIT3
#define RRSR_6M BIT4
#define RRSR_9M BIT5
#define RRSR_12M BIT6
#define RRSR_18M BIT7
#define RRSR_24M BIT8
#define RRSR_36M BIT9
#define RRSR_48M BIT10
#define RRSR_54M BIT11
#define RRSR_MCS0 BIT12
#define RRSR_MCS1 BIT13
#define RRSR_MCS2 BIT14
#define RRSR_MCS3 BIT15
#define RRSR_MCS4 BIT16
#define RRSR_MCS5 BIT17
#define RRSR_MCS6 BIT18
#define RRSR_MCS7 BIT19
#define RRSR_1M BIT(0)
#define RRSR_2M BIT(1)
#define RRSR_5_5M BIT(2)
#define RRSR_11M BIT(3)
#define RRSR_6M BIT(4)
#define RRSR_9M BIT(5)
#define RRSR_12M BIT(6)
#define RRSR_18M BIT(7)
#define RRSR_24M BIT(8)
#define RRSR_36M BIT(9)
#define RRSR_48M BIT(10)
#define RRSR_54M BIT(11)
#define RRSR_MCS0 BIT(12)
#define RRSR_MCS1 BIT(13)
#define RRSR_MCS2 BIT(14)
#define RRSR_MCS3 BIT(15)
#define RRSR_MCS4 BIT(16)
#define RRSR_MCS5 BIT(17)
#define RRSR_MCS6 BIT(18)
#define RRSR_MCS7 BIT(19)
/* 8192C Response Rate Set Register (offset 0x1BF, 8bits) */
/* WOL bit information */
#define HAL92C_WOL_PTK_UPDATE_EVENT BIT0
#define HAL92C_WOL_GTK_UPDATE_EVENT BIT1
#define HAL92C_WOL_PTK_UPDATE_EVENT BIT(0)
#define HAL92C_WOL_GTK_UPDATE_EVENT BIT(1)
/* 8192C BW_OPMODE bits (Offset 0x203, 8bit) */
#define BW_OPMODE_20MHZ BIT2
#define BW_OPMODE_5G BIT1
#define BW_OPMODE_20MHZ BIT(2)
#define BW_OPMODE_5G BIT(1)
/* 8192C CAM Config Setting (offset 0x250, 1 byte) */
#define CAM_VALID BIT15
#define CAM_VALID BIT(15)
#define CAM_NOTVALID 0x0000
#define CAM_USEDK BIT5
#define CAM_USEDK BIT(5)
#define CAM_CONTENT_COUNT 8
@ -594,69 +561,69 @@ Default: 00b.
#define CAM_CONFIG_USEDK true
#define CAM_CONFIG_NO_USEDK false
#define CAM_WRITE BIT16
#define CAM_WRITE BIT(16)
#define CAM_READ 0x00000000
#define CAM_POLLINIG BIT31
#define CAM_POLLINIG BIT(31)
#define SCR_UseDK 0x01
#define SCR_TxSecEnable 0x02
#define SCR_RxSecEnable 0x04
/* 10. Power Save Control Registers (Offset: 0x0260 - 0x02DF) */
#define WOW_PMEN BIT0 /* Power management Enable. */
#define WOW_WOMEN BIT1 /* WoW function on or off. */
#define WOW_MAGIC BIT2 /* Magic packet */
#define WOW_UWF BIT3 /* Unicast Wakeup frame. */
#define WOW_PMEN BIT(0) /* Power management Enable. */
#define WOW_WOMEN BIT(1) /* WoW function on or off. */
#define WOW_MAGIC BIT(2) /* Magic packet */
#define WOW_UWF BIT(3) /* Unicast Wakeup frame. */
/* 12. Host Interrupt Status Registers (Offset: 0x0300 - 0x030F) */
/* 8188 IMR/ISR bits */
#define IMR_DISABLED_88E 0x0
/* IMR DW0(0x0060-0063) Bit 0-31 */
#define IMR_TXCCK_88E BIT30 /* TXRPT interrupt when CCX bit of the packet is set */
#define IMR_PSTIMEOUT_88E BIT29 /* Power Save Time Out Interrupt */
#define IMR_GTINT4_88E BIT28 /* When GTIMER4 expires, this bit is set to 1 */
#define IMR_GTINT3_88E BIT27 /* When GTIMER3 expires, this bit is set to 1 */
#define IMR_TBDER_88E BIT26 /* Transmit Beacon0 Error */
#define IMR_TBDOK_88E BIT25 /* Transmit Beacon0 OK */
#define IMR_TSF_BIT32_TOGGLE_88E BIT24 /* TSF Timer BIT32 toggle indication interrupt */
#define IMR_BCNDMAINT0_88E BIT20 /* Beacon DMA Interrupt 0 */
#define IMR_BCNDERR0_88E BIT16 /* Beacon Queue DMA Error 0 */
#define IMR_HSISR_IND_ON_INT_88E BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
#define IMR_BCNDMAINT_E_88E BIT14 /* Beacon DMA Interrupt Extension for Win7 */
#define IMR_ATIMEND_88E BIT12 /* CTWidnow End or ATIM Window End */
#define IMR_HISR1_IND_INT_88E BIT11 /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */
#define IMR_C2HCMD_88E BIT10 /* CPU to Host Command INT Status, Write 1 clear */
#define IMR_CPWM2_88E BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
#define IMR_CPWM_88E BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
#define IMR_HIGHDOK_88E BIT7 /* High Queue DMA OK */
#define IMR_MGNTDOK_88E BIT6 /* Management Queue DMA OK */
#define IMR_BKDOK_88E BIT5 /* AC_BK DMA OK */
#define IMR_BEDOK_88E BIT4 /* AC_BE DMA OK */
#define IMR_VIDOK_88E BIT3 /* AC_VI DMA OK */
#define IMR_VODOK_88E BIT2 /* AC_VO DMA OK */
#define IMR_RDU_88E BIT1 /* Rx Descriptor Unavailable */
#define IMR_ROK_88E BIT0 /* Receive DMA OK */
#define IMR_TXCCK_88E BIT(30) /* TXRPT interrupt when CCX bit of the packet is set */
#define IMR_PSTIMEOUT_88E BIT(29) /* Power Save Time Out Interrupt */
#define IMR_GTINT4_88E BIT(28) /* When GTIMER4 expires, this bit is set to 1 */
#define IMR_GTINT3_88E BIT(27) /* When GTIMER3 expires, this bit is set to 1 */
#define IMR_TBDER_88E BIT(26) /* Transmit Beacon0 Error */
#define IMR_TBDOK_88E BIT(25) /* Transmit Beacon0 OK */
#define IMR_TSF_BIT32_TOGGLE_88E BIT(24) /* TSF Timer BIT32 toggle indication interrupt */
#define IMR_BCNDMAINT0_88E BIT(20) /* Beacon DMA Interrupt 0 */
#define IMR_BCNDERR0_88E BIT(16) /* Beacon Queue DMA Error 0 */
#define IMR_HSISR_IND_ON_INT_88E BIT(15) /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
#define IMR_BCNDMAINT_E_88E BIT(14) /* Beacon DMA Interrupt Extension for Win7 */
#define IMR_ATIMEND_88E BIT(12) /* CTWidnow End or ATIM Window End */
#define IMR_HISR1_IND_INT_88E BIT(11) /* HISR1 Indicator (HISR1 & HIMR1 is true, this bit is set to 1) */
#define IMR_C2HCMD_88E BIT(10) /* CPU to Host Command INT Status, Write 1 clear */
#define IMR_CPWM2_88E BIT(9) /* CPU power Mode exchange INT Status, Write 1 clear */
#define IMR_CPWM_88E BIT(8) /* CPU power Mode exchange INT Status, Write 1 clear */
#define IMR_HIGHDOK_88E BIT(7) /* High Queue DMA OK */
#define IMR_MGNTDOK_88E BIT(6) /* Management Queue DMA OK */
#define IMR_BKDOK_88E BIT(5) /* AC_BK DMA OK */
#define IMR_BEDOK_88E BIT(4) /* AC_BE DMA OK */
#define IMR_VIDOK_88E BIT(3) /* AC_VI DMA OK */
#define IMR_VODOK_88E BIT(2) /* AC_VO DMA OK */
#define IMR_RDU_88E BIT(1) /* Rx Descriptor Unavailable */
#define IMR_ROK_88E BIT(0) /* Receive DMA OK */
/* IMR DW1(0x00B4-00B7) Bit 0-31 */
#define IMR_BCNDMAINT7_88E BIT27 /* Beacon DMA Interrupt 7 */
#define IMR_BCNDMAINT6_88E BIT26 /* Beacon DMA Interrupt 6 */
#define IMR_BCNDMAINT5_88E BIT25 /* Beacon DMA Interrupt 5 */
#define IMR_BCNDMAINT4_88E BIT24 /* Beacon DMA Interrupt 4 */
#define IMR_BCNDMAINT3_88E BIT23 /* Beacon DMA Interrupt 3 */
#define IMR_BCNDMAINT2_88E BIT22 /* Beacon DMA Interrupt 2 */
#define IMR_BCNDMAINT1_88E BIT21 /* Beacon DMA Interrupt 1 */
#define IMR_BCNDERR7_88E BIT20 /* Beacon DMA Error Int 7 */
#define IMR_BCNDERR6_88E BIT19 /* Beacon DMA Error Int 6 */
#define IMR_BCNDERR5_88E BIT18 /* Beacon DMA Error Int 5 */
#define IMR_BCNDERR4_88E BIT17 /* Beacon DMA Error Int 4 */
#define IMR_BCNDERR3_88E BIT16 /* Beacon DMA Error Int 3 */
#define IMR_BCNDERR2_88E BIT15 /* Beacon DMA Error Int 2 */
#define IMR_BCNDERR1_88E BIT14 /* Beacon DMA Error Int 1 */
#define IMR_ATIMEND_E_88E BIT13 /* ATIM Window End Ext for Win7 */
#define IMR_TXERR_88E BIT11 /* Tx Err Flag Int Status, write 1 clear. */
#define IMR_RXERR_88E BIT10 /* Rx Err Flag INT Status, Write 1 clear */
#define IMR_TXFOVW_88E BIT9 /* Transmit FIFO Overflow */
#define IMR_RXFOVW_88E BIT8 /* Receive FIFO Overflow */
#define IMR_BCNDMAINT7_88E BIT(27) /* Beacon DMA Interrupt 7 */
#define IMR_BCNDMAINT6_88E BIT(26) /* Beacon DMA Interrupt 6 */
#define IMR_BCNDMAINT5_88E BIT(25) /* Beacon DMA Interrupt 5 */
#define IMR_BCNDMAINT4_88E BIT(24) /* Beacon DMA Interrupt 4 */
#define IMR_BCNDMAINT3_88E BIT(23) /* Beacon DMA Interrupt 3 */
#define IMR_BCNDMAINT2_88E BIT(22) /* Beacon DMA Interrupt 2 */
#define IMR_BCNDMAINT1_88E BIT(21) /* Beacon DMA Interrupt 1 */
#define IMR_BCNDERR7_88E BIT(20) /* Beacon DMA Error Int 7 */
#define IMR_BCNDERR6_88E BIT(19) /* Beacon DMA Error Int 6 */
#define IMR_BCNDERR5_88E BIT(18) /* Beacon DMA Error Int 5 */
#define IMR_BCNDERR4_88E BIT(17) /* Beacon DMA Error Int 4 */
#define IMR_BCNDERR3_88E BIT(16) /* Beacon DMA Error Int 3 */
#define IMR_BCNDERR2_88E BIT(15) /* Beacon DMA Error Int 2 */
#define IMR_BCNDERR1_88E BIT(14) /* Beacon DMA Error Int 1 */
#define IMR_ATIMEND_E_88E BIT(13) /* ATIM Window End Ext for Win7 */
#define IMR_TXERR_88E BIT(11) /* Tx Err Flag Int Status, write 1 clear. */
#define IMR_RXERR_88E BIT(10) /* Rx Err Flag INT Status, Write 1 clear */
#define IMR_TXFOVW_88E BIT(9) /* Transmit FIFO Overflow */
#define IMR_RXFOVW_88E BIT(8) /* Receive FIFO Overflow */
#define HAL_NIC_UNPLUG_ISR 0xFFFFFFFF /* The value when the NIC is unplugged for PCI. */
@ -692,40 +659,40 @@ Current IOREG MAP
/* the correct arragement is VO - Bit0, VI - Bit1, BE - Bit2,
* and BK - Bit3. */
/* 8723 and 88E may be not correct either in the earlier version. */
#define StopBecon BIT6
#define StopHigh BIT5
#define StopMgt BIT4
#define StopBK BIT3
#define StopBE BIT2
#define StopVI BIT1
#define StopVO BIT0
#define StopBecon BIT(6)
#define StopHigh BIT(5)
#define StopMgt BIT(4)
#define StopBK BIT(3)
#define StopBE BIT(2)
#define StopVI BIT(1)
#define StopVO BIT(0)
/* 8192C (RCR) Receive Configuration Register(Offset 0x608, 32 bits) */
#define RCR_APPFCS BIT31 /* WMAC append FCS after payload */
#define RCR_APP_MIC BIT30
#define RCR_APP_PHYSTS BIT28
#define RCR_APP_ICV BIT29
#define RCR_APP_PHYST_RXFF BIT28
#define RCR_APP_BA_SSN BIT27 /* Accept BA SSN */
#define RCR_ENMBID BIT24 /* Enable Multiple BssId. */
#define RCR_LSIGEN BIT23
#define RCR_MFBEN BIT22
#define RCR_HTC_LOC_CTRL BIT14 /* MFC<--HTC=1 MFC-->HTC=0 */
#define RCR_AMF BIT13 /* Accept management type frame */
#define RCR_ACF BIT12 /* Accept control type frame */
#define RCR_ADF BIT11 /* Accept data type frame */
#define RCR_AICV BIT9 /* Accept ICV error packet */
#define RCR_ACRC32 BIT8 /* Accept CRC32 error packet */
#define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet
#define RCR_APPFCS BIT(31) /* WMAC append FCS after payload */
#define RCR_APP_MIC BIT(30)
#define RCR_APP_PHYSTS BIT(28)
#define RCR_APP_ICV BIT(29)
#define RCR_APP_PHYST_RXFF BIT(28)
#define RCR_APP_BA_SSN BIT(27) /* Accept BA SSN */
#define RCR_ENMBID BIT(24) /* Enable Multiple BssId. */
#define RCR_LSIGEN BIT(23)
#define RCR_MFBEN BIT(22)
#define RCR_HTC_LOC_CTRL BIT(14) /* MFC<--HTC=1 MFC-->HTC=0 */
#define RCR_AMF BIT(13) /* Accept management type frame */
#define RCR_ACF BIT(12) /* Accept control type frame */
#define RCR_ADF BIT(11) /* Accept data type frame */
#define RCR_AICV BIT(9) /* Accept ICV error packet */
#define RCR_ACRC32 BIT(8) /* Accept CRC32 error packet */
#define RCR_CBSSID_BCN BIT(7) /* Accept BSSID match packet
* (Rx beacon, probe rsp) */
#define RCR_CBSSID_DATA BIT6 /* Accept BSSID match (Data)*/
#define RCR_CBSSID_DATA BIT(6) /* Accept BSSID match (Data)*/
#define RCR_CBSSID RCR_CBSSID_DATA /* Accept BSSID match */
#define RCR_APWRMGT BIT5 /* Accept power management pkt*/
#define RCR_ADD3 BIT4 /* Accept address 3 match pkt */
#define RCR_AB BIT3 /* Accept broadcast packet */
#define RCR_AM BIT2 /* Accept multicast packet */
#define RCR_APM BIT1 /* Accept physical match pkt */
#define RCR_AAP BIT0 /* Accept all unicast packet */
#define RCR_APWRMGT BIT(5) /* Accept power management pkt*/
#define RCR_ADD3 BIT(4) /* Accept address 3 match pkt */
#define RCR_AB BIT(3) /* Accept broadcast packet */
#define RCR_AM BIT(2) /* Accept multicast packet */
#define RCR_APM BIT(1) /* Accept physical match pkt */
#define RCR_AAP BIT(0) /* Accept all unicast packet */
#define RCR_MXDMA_OFFSET 8
#define RCR_FIFO_OFFSET 13
@ -1193,56 +1160,56 @@ Current IOREG MAP
#define SDIO_HIMR_DISABLED 0
/* RTL8188E SDIO Host Interrupt Mask Register */
#define SDIO_HIMR_RX_REQUEST_MSK BIT0
#define SDIO_HIMR_AVAL_MSK BIT1
#define SDIO_HIMR_TXERR_MSK BIT2
#define SDIO_HIMR_RXERR_MSK BIT3
#define SDIO_HIMR_TXFOVW_MSK BIT4
#define SDIO_HIMR_RXFOVW_MSK BIT5
#define SDIO_HIMR_TXBCNOK_MSK BIT6
#define SDIO_HIMR_TXBCNERR_MSK BIT7
#define SDIO_HIMR_BCNERLY_INT_MSK BIT16
#define SDIO_HIMR_C2HCMD_MSK BIT17
#define SDIO_HIMR_CPWM1_MSK BIT18
#define SDIO_HIMR_CPWM2_MSK BIT19
#define SDIO_HIMR_HSISR_IND_MSK BIT20
#define SDIO_HIMR_GTINT3_IND_MSK BIT21
#define SDIO_HIMR_GTINT4_IND_MSK BIT22
#define SDIO_HIMR_PSTIMEOUT_MSK BIT23
#define SDIO_HIMR_OCPINT_MSK BIT24
#define SDIO_HIMR_ATIMEND_MSK BIT25
#define SDIO_HIMR_ATIMEND_E_MSK BIT26
#define SDIO_HIMR_CTWEND_MSK BIT27
#define SDIO_HIMR_RX_REQUEST_MSK BIT(0)
#define SDIO_HIMR_AVAL_MSK BIT(1)
#define SDIO_HIMR_TXERR_MSK BIT(2)
#define SDIO_HIMR_RXERR_MSK BIT(3)
#define SDIO_HIMR_TXFOVW_MSK BIT(4)
#define SDIO_HIMR_RXFOVW_MSK BIT(5)
#define SDIO_HIMR_TXBCNOK_MSK BIT(6)
#define SDIO_HIMR_TXBCNERR_MSK BIT(7)
#define SDIO_HIMR_BCNERLY_INT_MSK BIT(16)
#define SDIO_HIMR_C2HCMD_MSK BIT(17)
#define SDIO_HIMR_CPWM1_MSK BIT(18)
#define SDIO_HIMR_CPWM2_MSK BIT(19)
#define SDIO_HIMR_HSISR_IND_MSK BIT(20)
#define SDIO_HIMR_GTINT3_IND_MSK BIT(21)
#define SDIO_HIMR_GTINT4_IND_MSK BIT(22)
#define SDIO_HIMR_PSTIMEOUT_MSK BIT(23)
#define SDIO_HIMR_OCPINT_MSK BIT(24)
#define SDIO_HIMR_ATIMEND_MSK BIT(25)
#define SDIO_HIMR_ATIMEND_E_MSK BIT(26)
#define SDIO_HIMR_CTWEND_MSK BIT(27)
/* RTL8188E SDIO Specific */
#define SDIO_HIMR_MCU_ERR_MSK BIT28
#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT29
#define SDIO_HIMR_MCU_ERR_MSK BIT(28)
#define SDIO_HIMR_TSF_BIT32_TOGGLE_MSK BIT(29)
/* SDIO Host Interrupt Service Routine */
#define SDIO_HISR_RX_REQUEST BIT0
#define SDIO_HISR_AVAL BIT1
#define SDIO_HISR_TXERR BIT2
#define SDIO_HISR_RXERR BIT3
#define SDIO_HISR_TXFOVW BIT4
#define SDIO_HISR_RXFOVW BIT5
#define SDIO_HISR_TXBCNOK BIT6
#define SDIO_HISR_TXBCNERR BIT7
#define SDIO_HISR_BCNERLY_INT BIT16
#define SDIO_HISR_C2HCMD BIT17
#define SDIO_HISR_CPWM1 BIT18
#define SDIO_HISR_CPWM2 BIT19
#define SDIO_HISR_HSISR_IND BIT20
#define SDIO_HISR_GTINT3_IND BIT21
#define SDIO_HISR_GTINT4_IND BIT22
#define SDIO_HISR_PSTIME BIT23
#define SDIO_HISR_OCPINT BIT24
#define SDIO_HISR_ATIMEND BIT25
#define SDIO_HISR_ATIMEND_E BIT26
#define SDIO_HISR_CTWEND BIT27
#define SDIO_HISR_RX_REQUEST BIT(0)
#define SDIO_HISR_AVAL BIT(1)
#define SDIO_HISR_TXERR BIT(2)
#define SDIO_HISR_RXERR BIT(3)
#define SDIO_HISR_TXFOVW BIT(4)
#define SDIO_HISR_RXFOVW BIT(5)
#define SDIO_HISR_TXBCNOK BIT(6)
#define SDIO_HISR_TXBCNERR BIT(7)
#define SDIO_HISR_BCNERLY_INT BIT(16)
#define SDIO_HISR_C2HCMD BIT(17)
#define SDIO_HISR_CPWM1 BIT(18)
#define SDIO_HISR_CPWM2 BIT(19)
#define SDIO_HISR_HSISR_IND BIT(20)
#define SDIO_HISR_GTINT3_IND BIT(21)
#define SDIO_HISR_GTINT4_IND BIT(22)
#define SDIO_HISR_PSTIME BIT(23)
#define SDIO_HISR_OCPINT BIT(24)
#define SDIO_HISR_ATIMEND BIT(25)
#define SDIO_HISR_ATIMEND_E BIT(26)
#define SDIO_HISR_CTWEND BIT(27)
/* RTL8188E SDIO Specific */
#define SDIO_HISR_MCU_ERR BIT28
#define SDIO_HISR_TSF_BIT32_TOGGLE BIT29
#define SDIO_HISR_MCU_ERR BIT(28)
#define SDIO_HISR_TSF_BIT32_TOGGLE BIT(29)
#define MASK_SDIO_HISR_CLEAR \
(SDIO_HISR_TXERR | SDIO_HISR_RXERR | SDIO_HISR_TXFOVW |\
@ -1252,8 +1219,8 @@ Current IOREG MAP
SDIO_HISR_PSTIMEOUT | SDIO_HISR_OCPINT)
/* SDIO HCI Suspend Control Register */
#define HCI_RESUME_PWR_RDY BIT1
#define HCI_SUS_CTRL BIT0
#define HCI_RESUME_PWR_RDY BIT(1)
#define HCI_SUS_CTRL BIT(0)
/* SDIO Tx FIFO related */
/* The number of Tx FIFO free page */
@ -1287,33 +1254,33 @@ Current IOREG MAP
/* 2REG_MULTI_FUNC_CTRL(For RTL8723 Only) */
/* Enable GPIO[9] as WiFi HW PDn source */
#define WL_HWPDN_EN BIT0
#define WL_HWPDN_EN BIT(0)
/* WiFi HW PDn polarity control */
#define WL_HWPDN_SL BIT1
#define WL_HWPDN_SL BIT(1)
/* WiFi function enable */
#define WL_FUNC_EN BIT2
#define WL_FUNC_EN BIT(2)
/* Enable GPIO[9] as WiFi RF HW PDn source */
#define WL_HWROF_EN BIT3
#define WL_HWROF_EN BIT(3)
/* Enable GPIO[11] as BT HW PDn source */
#define BT_HWPDN_EN BIT16
#define BT_HWPDN_EN BIT(16)
/* BT HW PDn polarity control */
#define BT_HWPDN_SL BIT17
#define BT_HWPDN_SL BIT(17)
/* BT function enable */
#define BT_FUNC_EN BIT18
#define BT_FUNC_EN BIT(18)
/* Enable GPIO[11] as BT/GPS RF HW PDn source */
#define BT_HWROF_EN BIT19
#define BT_HWROF_EN BIT(19)
/* Enable GPIO[10] as GPS HW PDn source */
#define GPS_HWPDN_EN BIT20
#define GPS_HWPDN_EN BIT(20)
/* GPS HW PDn polarity control */
#define GPS_HWPDN_SL BIT21
#define GPS_HWPDN_SL BIT(21)
/* GPS function enable */
#define GPS_FUNC_EN BIT22
#define GPS_FUNC_EN BIT(22)
/* 3 REG_LIFECTRL_CTRL */
#define HAL92C_EN_PKT_LIFE_TIME_BK BIT3
#define HAL92C_EN_PKT_LIFE_TIME_BE BIT2
#define HAL92C_EN_PKT_LIFE_TIME_VI BIT1
#define HAL92C_EN_PKT_LIFE_TIME_VO BIT0
#define HAL92C_EN_PKT_LIFE_TIME_BK BIT(3)
#define HAL92C_EN_PKT_LIFE_TIME_BE BIT(2)
#define HAL92C_EN_PKT_LIFE_TIME_VI BIT(1)
#define HAL92C_EN_PKT_LIFE_TIME_VO BIT(0)
#define HAL92C_MSDU_LIFE_TIME_UNIT 128 /* in us */
@ -1323,7 +1290,7 @@ Current IOREG MAP
#define POLLING_LLT_THRESHOLD 20
#define POLLING_READY_TIMEOUT_COUNT 1000
/* GPIO BIT */
#define HAL_8192C_HW_GPIO_WPS_BIT BIT2
#define HAL_8192C_HW_GPIO_WPS_BIT BIT(2)
/* 8192C EEPROM/EFUSE share register definition. */

14
drivers/staging/rtl8188eu/include/rtw_sreset.h
View file

@ -30,13 +30,13 @@ struct sreset_priv {
#include <rtl8188e_hal.h>
#define WIFI_STATUS_SUCCESS 0
#define USB_VEN_REQ_CMD_FAIL BIT0
#define USB_READ_PORT_FAIL BIT1
#define USB_WRITE_PORT_FAIL BIT2
#define WIFI_MAC_TXDMA_ERROR BIT3
#define WIFI_TX_HANG BIT4
#define WIFI_RX_HANG BIT5
#define WIFI_IF_NOT_EXIST BIT6
#define USB_VEN_REQ_CMD_FAIL BIT(0)
#define USB_READ_PORT_FAIL BIT(1)
#define USB_WRITE_PORT_FAIL BIT(2)
#define WIFI_MAC_TXDMA_ERROR BIT(3)
#define WIFI_TX_HANG BIT(4)
#define WIFI_RX_HANG BIT(5)
#define WIFI_IF_NOT_EXIST BIT(6)
void sreset_init_value(struct adapter *padapter);
u8 sreset_get_wifi_status(struct adapter *padapter);