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microblaze: Fix unaligned issue on MMU system with BS=0 DIV=1
Unaligned code use shift for finding register operand. There is used BSRLI(r8,r8,2) macro which is expand for BS=0, DIV=1 by ori rD, r0, (1 << imm); \ idivu rD, rD, rA but if rD is equal rA then ori instruction rewrite value which should be devide. The patch remove this macro which use idivu instruction because idivu takes 32/34 cycles. The highest shifting is 20 which takes 20 cycles. Signed-off-by: Michal Simek <monstr@monstr.eu>
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1 changed files with 0 additions and 4 deletions
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@ -147,10 +147,6 @@
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#if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
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#if CONFIG_XILINX_MICROBLAZE0_USE_BARREL > 0
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#define BSRLI(rD, rA, imm) \
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#define BSRLI(rD, rA, imm) \
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bsrli rD, rA, imm
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bsrli rD, rA, imm
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#elif CONFIG_XILINX_MICROBLAZE0_USE_DIV > 0
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#define BSRLI(rD, rA, imm) \
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ori rD, r0, (1 << imm); \
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idivu rD, rD, rA
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#else
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#else
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#define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
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#define BSRLI(rD, rA, imm) BSRLI ## imm (rD, rA)
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/* Only the used shift constants defined here - add more if needed */
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/* Only the used shift constants defined here - add more if needed */
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