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drm/amd/display: treat memory as a single-channel for asymmetric memory v2
Previous change had been reverted since it caused hang.
Remake change to avoid defect.
[Why]
1. Driver use umachannelnumber to calculate watermarks for stutter.
In asymmetric memory config, the actual bandwidth is less than
dual-channel. The bandwidth should be the same as single-channel.
2. We found single rank dimm need additional delay time for stutter.
[How]
Get information from each DIMM. Treat memory config as a single-channel
for asymmetric memory in bandwidth calculating.
Add additional delay time for single rank dimm.
Fixes: b8720ed0b8
("drm/amd/display: System black screen hangs on driver load")
Signed-off-by: Hugo Hu <hugo.hu@amd.com>
Reviewed-by: Sung Lee <Sung.Lee@amd.com>
Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
parent
8a20c97329
commit
9c82354e89
2 changed files with 48 additions and 2 deletions
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@ -769,6 +769,43 @@ static struct wm_table ddr4_wm_table_rn = {
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}
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}
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};
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};
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static struct wm_table ddr4_1R_wm_table_rn = {
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.entries = {
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{
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.wm_inst = WM_A,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 13.90,
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.sr_enter_plus_exit_time_us = 14.80,
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.valid = true,
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},
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{
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.wm_inst = WM_B,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 13.90,
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.sr_enter_plus_exit_time_us = 14.80,
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.valid = true,
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},
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{
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.wm_inst = WM_C,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 13.90,
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.sr_enter_plus_exit_time_us = 14.80,
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.valid = true,
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},
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{
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.wm_inst = WM_D,
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.wm_type = WM_TYPE_PSTATE_CHG,
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.pstate_latency_us = 11.72,
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.sr_exit_time_us = 13.90,
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.sr_enter_plus_exit_time_us = 14.80,
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.valid = true,
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},
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}
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};
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static struct wm_table lpddr4_wm_table_rn = {
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static struct wm_table lpddr4_wm_table_rn = {
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.entries = {
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.entries = {
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{
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{
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@ -953,8 +990,12 @@ void rn_clk_mgr_construct(
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} else {
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} else {
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if (is_green_sardine)
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if (is_green_sardine)
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rn_bw_params.wm_table = ddr4_wm_table_gs;
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rn_bw_params.wm_table = ddr4_wm_table_gs;
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else
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else {
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rn_bw_params.wm_table = ddr4_wm_table_rn;
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if (ctx->dc->config.is_single_rank_dimm)
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rn_bw_params.wm_table = ddr4_1R_wm_table_rn;
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else
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rn_bw_params.wm_table = ddr4_wm_table_rn;
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}
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}
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}
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/* Saved clocks configured at boot for debug purposes */
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/* Saved clocks configured at boot for debug purposes */
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rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
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rn_dump_clk_registers(&clk_mgr->base.boot_snapshot, &clk_mgr->base, &log_info);
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@ -972,6 +1013,9 @@ void rn_clk_mgr_construct(
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if (status == PP_SMU_RESULT_OK &&
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if (status == PP_SMU_RESULT_OK &&
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ctx->dc_bios && ctx->dc_bios->integrated_info) {
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ctx->dc_bios && ctx->dc_bios->integrated_info) {
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rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
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rn_clk_mgr_helper_populate_bw_params (clk_mgr->base.bw_params, &clock_table, ctx->dc_bios->integrated_info);
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/* treat memory config as single channel if memory is asymmetrics. */
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if (ctx->dc->config.is_asymmetric_memory)
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clk_mgr->base.bw_params->num_channels = 1;
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}
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}
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}
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}
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@ -308,6 +308,8 @@ struct dc_config {
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#endif
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#endif
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uint64_t vblank_alignment_dto_params;
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uint64_t vblank_alignment_dto_params;
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uint8_t vblank_alignment_max_frame_time_diff;
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uint8_t vblank_alignment_max_frame_time_diff;
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bool is_asymmetric_memory;
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bool is_single_rank_dimm;
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};
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};
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enum visual_confirm {
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enum visual_confirm {
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