mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-23 01:10:04 +00:00
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into devel-stable
Conflicts: arch/arm/mm/Kconfig
This commit is contained in:
commit
9ced9f03d1
130 changed files with 6318 additions and 2367 deletions
|
@ -715,7 +715,8 @@ config ARCH_S5P64X0
|
|||
select GENERIC_GPIO
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||||
select HAVE_CLK
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||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
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||||
select ARCH_USES_GETTIMEOFFSET
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||||
select GENERIC_CLOCKEVENTS
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||||
select HAVE_SCHED_CLOCK
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||||
select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C_RTC if RTC_CLASS
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||||
help
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||||
|
@ -753,15 +754,16 @@ config ARCH_S5PV210
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|||
select HAVE_CLK
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select ARM_L1_CACHE_SHIFT_6
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select ARCH_HAS_CPUFREQ
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select ARCH_USES_GETTIMEOFFSET
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||||
select GENERIC_CLOCKEVENTS
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select HAVE_SCHED_CLOCK
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C_RTC if RTC_CLASS
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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help
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||||
Samsung S5PV210/S5PC110 series based systems
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config ARCH_S5PV310
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bool "Samsung S5PV310/S5PC210"
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config ARCH_EXYNOS4
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bool "Samsung EXYNOS4"
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select CPU_V7
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select ARCH_SPARSEMEM_ENABLE
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select GENERIC_GPIO
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@ -772,7 +774,7 @@ config ARCH_S5PV310
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select HAVE_S3C2410_I2C if I2C
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select HAVE_S3C2410_WATCHDOG if WATCHDOG
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help
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Samsung S5PV310 series based systems
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Samsung EXYNOS4 series based systems
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config ARCH_SHARK
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bool "Shark"
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@ -991,7 +993,7 @@ source "arch/arm/mach-s5pc100/Kconfig"
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source "arch/arm/mach-s5pv210/Kconfig"
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source "arch/arm/mach-s5pv310/Kconfig"
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source "arch/arm/mach-exynos4/Kconfig"
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source "arch/arm/mach-shmobile/Kconfig"
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@ -1278,7 +1280,7 @@ config SMP
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depends on GENERIC_CLOCKEVENTS
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depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
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MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
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ARCH_S5PV310 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
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ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
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ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
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select USE_GENERIC_SMP_HELPERS
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select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
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@ -1366,7 +1368,7 @@ config LOCAL_TIMERS
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bool "Use local timer interrupts"
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depends on SMP
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default y
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select HAVE_ARM_TWD if !ARCH_MSM_SCORPIONMP
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select HAVE_ARM_TWD if (!ARCH_MSM_SCORPIONMP && !EXYNOS4_MCT)
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help
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Enable support for local timers on SMP platforms, rather then the
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legacy IPI broadcast method. Local timers allows the system
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@ -1378,7 +1380,7 @@ source kernel/Kconfig.preempt
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config HZ
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int
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default 200 if ARCH_EBSA110 || ARCH_S3C2410 || ARCH_S5P64X0 || \
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ARCH_S5P6442 || ARCH_S5PV210 || ARCH_S5PV310
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ARCH_S5P6442 || ARCH_S5PV210 || ARCH_EXYNOS4
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default OMAP_32K_TIMER_HZ if ARCH_OMAP && OMAP_32K_TIMER
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default AT91_TIMER_HZ if ARCH_AT91
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default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
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|
|
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@ -178,7 +178,7 @@ machine-$(CONFIG_ARCH_S5P64X0) := s5p64x0
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machine-$(CONFIG_ARCH_S5P6442) := s5p6442
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machine-$(CONFIG_ARCH_S5PC100) := s5pc100
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machine-$(CONFIG_ARCH_S5PV210) := s5pv210
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machine-$(CONFIG_ARCH_S5PV310) := s5pv310
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machine-$(CONFIG_ARCH_EXYNOS4) := exynos4
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machine-$(CONFIG_ARCH_SA1100) := sa1100
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machine-$(CONFIG_ARCH_SHARK) := shark
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machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
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|
|
70
arch/arm/configs/exynos4_defconfig
Normal file
70
arch/arm/configs/exynos4_defconfig
Normal file
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@ -0,0 +1,70 @@
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|||
CONFIG_EXPERIMENTAL=y
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CONFIG_BLK_DEV_INITRD=y
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CONFIG_KALLSYMS_ALL=y
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CONFIG_MODULES=y
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CONFIG_MODULE_UNLOAD=y
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# CONFIG_BLK_DEV_BSG is not set
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CONFIG_ARCH_EXYNOS4=y
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CONFIG_S3C_LOWLEVEL_UART_PORT=1
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CONFIG_MACH_SMDKC210=y
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CONFIG_MACH_SMDKV310=y
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CONFIG_MACH_UNIVERSAL_C210=y
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CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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CONFIG_SMP=y
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CONFIG_NR_CPUS=2
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CONFIG_HOTPLUG_CPU=y
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CONFIG_PREEMPT=y
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CONFIG_AEABI=y
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CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x41000000,8M console=ttySAC1,115200 init=/linuxrc mem=256M"
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CONFIG_VFP=y
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CONFIG_NEON=y
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
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CONFIG_BLK_DEV_LOOP=y
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CONFIG_BLK_DEV_RAM=y
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CONFIG_BLK_DEV_RAM_SIZE=8192
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CONFIG_SCSI=y
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CONFIG_BLK_DEV_SD=y
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CONFIG_CHR_DEV_SG=y
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CONFIG_INPUT_EVDEV=y
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# CONFIG_INPUT_KEYBOARD is not set
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# CONFIG_INPUT_MOUSE is not set
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CONFIG_INPUT_TOUCHSCREEN=y
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CONFIG_SERIAL_8250=y
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CONFIG_SERIAL_SAMSUNG=y
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CONFIG_SERIAL_SAMSUNG_CONSOLE=y
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CONFIG_HW_RANDOM=y
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CONFIG_I2C=y
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# CONFIG_HWMON is not set
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# CONFIG_MFD_SUPPORT is not set
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||||
# CONFIG_HID_SUPPORT is not set
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||||
# CONFIG_USB_SUPPORT is not set
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CONFIG_EXT2_FS=y
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CONFIG_MSDOS_FS=y
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||||
CONFIG_VFAT_FS=y
|
||||
CONFIG_TMPFS=y
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CONFIG_TMPFS_POSIX_ACL=y
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CONFIG_CRAMFS=y
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CONFIG_ROMFS_FS=y
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CONFIG_PARTITION_ADVANCED=y
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CONFIG_BSD_DISKLABEL=y
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CONFIG_SOLARIS_X86_PARTITION=y
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CONFIG_NLS_CODEPAGE_437=y
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CONFIG_NLS_ASCII=y
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||||
CONFIG_NLS_ISO8859_1=y
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CONFIG_MAGIC_SYSRQ=y
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CONFIG_DEBUG_KERNEL=y
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CONFIG_DETECT_HUNG_TASK=y
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CONFIG_DEBUG_RT_MUTEXES=y
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CONFIG_DEBUG_SPINLOCK=y
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CONFIG_DEBUG_MUTEXES=y
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CONFIG_DEBUG_SPINLOCK_SLEEP=y
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CONFIG_DEBUG_INFO=y
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# CONFIG_RCU_CPU_STALL_DETECTOR is not set
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CONFIG_SYSCTL_SYSCALL_CHECK=y
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CONFIG_DEBUG_USER=y
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||||
CONFIG_DEBUG_ERRORS=y
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||||
CONFIG_DEBUG_LL=y
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||||
CONFIG_EARLY_PRINTK=y
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||||
CONFIG_DEBUG_S3C_UART=1
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CONFIG_CRC_CCITT=y
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|
@ -10,6 +10,8 @@ CONFIG_S3C_BOOT_ERROR_RESET=y
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|||
CONFIG_S3C_LOWLEVEL_UART_PORT=1
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CONFIG_MACH_SMDK6440=y
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CONFIG_MACH_SMDK6450=y
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||||
CONFIG_NO_HZ=y
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CONFIG_HIGH_RES_TIMERS=y
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||||
CONFIG_CPU_32v6K=y
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||||
CONFIG_AEABI=y
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||||
CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
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||||
|
|
|
@ -13,6 +13,8 @@ CONFIG_MACH_AQUILA=y
|
|||
CONFIG_MACH_GONI=y
|
||||
CONFIG_MACH_SMDKC110=y
|
||||
CONFIG_MACH_SMDKV210=y
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||||
CONFIG_NO_HZ=y
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||||
CONFIG_HIGH_RES_TIMERS=y
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||||
CONFIG_VMSPLIT_2G=y
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||||
CONFIG_PREEMPT=y
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||||
CONFIG_AEABI=y
|
||||
|
|
195
arch/arm/mach-exynos4/Kconfig
Normal file
195
arch/arm/mach-exynos4/Kconfig
Normal file
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@ -0,0 +1,195 @@
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|||
# arch/arm/mach-exynos4/Kconfig
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||||
#
|
||||
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
# http://www.samsung.com/
|
||||
#
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||||
# Licensed under GPLv2
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||||
|
||||
# Configuration options for the EXYNOS4
|
||||
|
||||
if ARCH_EXYNOS4
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||||
config CPU_EXYNOS4210
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bool
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||||
select S3C_PL330_DMA
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||||
help
|
||||
Enable EXYNOS4210 CPU support
|
||||
|
||||
config EXYNOS4_MCT
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||||
bool "Kernel timer support by MCT"
|
||||
help
|
||||
Use MCT (Multi Core Timer) as kernel timers
|
||||
|
||||
config EXYNOS4_DEV_PD
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bool
|
||||
help
|
||||
Compile in platform device definitions for Power Domain
|
||||
|
||||
config EXYNOS4_DEV_SYSMMU
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bool
|
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help
|
||||
Common setup code for SYSTEM MMU in EXYNOS4
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|
||||
config EXYNOS4_SETUP_I2C1
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bool
|
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help
|
||||
Common setup code for i2c bus 1.
|
||||
|
||||
config EXYNOS4_SETUP_I2C2
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bool
|
||||
help
|
||||
Common setup code for i2c bus 2.
|
||||
|
||||
config EXYNOS4_SETUP_I2C3
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bool
|
||||
help
|
||||
Common setup code for i2c bus 3.
|
||||
|
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config EXYNOS4_SETUP_I2C4
|
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bool
|
||||
help
|
||||
Common setup code for i2c bus 4.
|
||||
|
||||
config EXYNOS4_SETUP_I2C5
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bool
|
||||
help
|
||||
Common setup code for i2c bus 5.
|
||||
|
||||
config EXYNOS4_SETUP_I2C6
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bool
|
||||
help
|
||||
Common setup code for i2c bus 6.
|
||||
|
||||
config EXYNOS4_SETUP_I2C7
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bool
|
||||
help
|
||||
Common setup code for i2c bus 7.
|
||||
|
||||
config EXYNOS4_SETUP_KEYPAD
|
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bool
|
||||
help
|
||||
Common setup code for keypad.
|
||||
|
||||
config EXYNOS4_SETUP_SDHCI
|
||||
bool
|
||||
select EXYNOS4_SETUP_SDHCI_GPIO
|
||||
help
|
||||
Internal helper functions for EXYNOS4 based SDHCI systems.
|
||||
|
||||
config EXYNOS4_SETUP_SDHCI_GPIO
|
||||
bool
|
||||
help
|
||||
Common setup code for SDHCI gpio.
|
||||
|
||||
config EXYNOS4_SETUP_FIMC
|
||||
bool
|
||||
help
|
||||
Common setup code for the camera interfaces.
|
||||
|
||||
# machine support
|
||||
|
||||
menu "EXYNOS4 Machines"
|
||||
|
||||
config MACH_SMDKC210
|
||||
bool "SMDKC210"
|
||||
select CPU_EXYNOS4210
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select EXYNOS4_DEV_PD
|
||||
select EXYNOS4_DEV_SYSMMU
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
help
|
||||
Machine support for Samsung SMDKC210
|
||||
|
||||
config MACH_SMDKV310
|
||||
bool "SMDKV310"
|
||||
select CPU_EXYNOS4210
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select SAMSUNG_DEV_KEYPAD
|
||||
select EXYNOS4_DEV_PD
|
||||
select EXYNOS4_DEV_SYSMMU
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_KEYPAD
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
help
|
||||
Machine support for Samsung SMDKV310
|
||||
|
||||
config MACH_ARMLEX4210
|
||||
bool "ARMLEX4210"
|
||||
select CPU_EXYNOS4210
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select EXYNOS4_DEV_SYSMMU
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select SATA_AHCI_PLATFORM
|
||||
help
|
||||
Machine support for Samsung ARMLEX4210 based on EXYNOS4210
|
||||
|
||||
config MACH_UNIVERSAL_C210
|
||||
bool "Mobile UNIVERSAL_C210 Board"
|
||||
select CPU_EXYNOS4210
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C5
|
||||
select S5P_DEV_ONENAND
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_I2C5
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
help
|
||||
Machine support for Samsung Mobile Universal S5PC210 Reference
|
||||
Board.
|
||||
|
||||
config MACH_NURI
|
||||
bool "Mobile NURI Board"
|
||||
select CPU_EXYNOS4210
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_I2C5
|
||||
select EXYNOS4_SETUP_I2C1
|
||||
select EXYNOS4_SETUP_I2C5
|
||||
select EXYNOS4_SETUP_SDHCI
|
||||
select SAMSUNG_DEV_PWM
|
||||
help
|
||||
Machine support for Samsung Mobile NURI Board.
|
||||
|
||||
endmenu
|
||||
|
||||
comment "Configuration for HSMMC bus width"
|
||||
|
||||
menu "Use 8-bit bus width"
|
||||
|
||||
config EXYNOS4_SDHCI_CH0_8BIT
|
||||
bool "Channel 0 with 8-bit bus"
|
||||
help
|
||||
Support HSMMC Channel 0 8-bit bus.
|
||||
If selected, Channel 1 is disabled.
|
||||
|
||||
config EXYNOS4_SDHCI_CH2_8BIT
|
||||
bool "Channel 2 with 8-bit bus"
|
||||
help
|
||||
Support HSMMC Channel 2 8-bit bus.
|
||||
If selected, Channel 3 is disabled.
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
56
arch/arm/mach-exynos4/Makefile
Normal file
56
arch/arm/mach-exynos4/Makefile
Normal file
|
@ -0,0 +1,56 @@
|
|||
# arch/arm/mach-exynos4/Makefile
|
||||
#
|
||||
# Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
# http://www.samsung.com/
|
||||
#
|
||||
# Licensed under GPLv2
|
||||
|
||||
obj-y :=
|
||||
obj-m :=
|
||||
obj-n :=
|
||||
obj- :=
|
||||
|
||||
# Core support for EXYNOS4 system
|
||||
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += cpu.o init.o clock.o irq-combiner.o
|
||||
obj-$(CONFIG_CPU_EXYNOS4210) += setup-i2c0.o gpiolib.o irq-eint.o dma.o
|
||||
obj-$(CONFIG_PM) += pm.o sleep.o
|
||||
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
|
||||
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
|
||||
ifeq ($(CONFIG_EXYNOS4_MCT),y)
|
||||
obj-y += mct.o
|
||||
else
|
||||
obj-y += time.o
|
||||
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
|
||||
endif
|
||||
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
||||
# machine support
|
||||
|
||||
obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
|
||||
obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
|
||||
obj-$(CONFIG_MACH_ARMLEX4210) += mach-armlex4210.o
|
||||
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
|
||||
obj-$(CONFIG_MACH_NURI) += mach-nuri.o
|
||||
|
||||
# device support
|
||||
|
||||
obj-y += dev-audio.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_PD) += dev-pd.o
|
||||
obj-$(CONFIG_EXYNOS4_DEV_SYSMMU) += dev-sysmmu.o
|
||||
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_FIMC) += setup-fimc.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C1) += setup-i2c1.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C2) += setup-i2c2.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C3) += setup-i2c3.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C4) += setup-i2c4.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C5) += setup-i2c5.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C6) += setup-i2c6.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_I2C7) += setup-i2c7.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
|
||||
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
|
||||
obj-$(CONFIG_SATA_AHCI_PLATFORM) += dev-ahci.o
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/clock.c
|
||||
/* linux/arch/arm/mach-exynos4/clock.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - Clock support
|
||||
* EXYNOS4 - Clock support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -23,6 +23,7 @@
|
|||
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/sysmmu.h>
|
||||
|
||||
static struct clk clk_sclk_hdmi27m = {
|
||||
.name = "sclk_hdmi27m",
|
||||
|
@ -46,72 +47,82 @@ static struct clk clk_sclk_usbphy1 = {
|
|||
.id = -1,
|
||||
};
|
||||
|
||||
static int s5pv310_clksrc_mask_top_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clksrc_mask_top_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_TOP, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clksrc_mask_cam_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_CAM, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clksrc_mask_lcd0_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD0, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clksrc_mask_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clksrc_mask_fsys_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_FSYS, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clksrc_mask_peril0_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL0, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clksrc_mask_peril1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKSRC_MASK_PERIL1, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clk_ip_cam_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clk_ip_mfc_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_MFC, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clk_ip_cam_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_CAM, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clk_ip_image_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clk_ip_tv_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_TV, clk, enable);
|
||||
}
|
||||
|
||||
static int exynos4_clk_ip_image_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_IMAGE, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clk_ip_lcd0_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_LCD0, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clk_ip_lcd1_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_LCD1, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clk_ip_fsys_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clk_ip_fsys_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_FSYS, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clk_ip_peril_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clk_ip_peril_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_PERIL, clk, enable);
|
||||
}
|
||||
|
||||
static int s5pv310_clk_ip_perir_ctrl(struct clk *clk, int enable)
|
||||
static int exynos4_clk_ip_perir_ctrl(struct clk *clk, int enable)
|
||||
{
|
||||
return s5p_gatectrl(S5P_CLKGATE_IP_PERIR, clk, enable);
|
||||
}
|
||||
|
@ -358,7 +369,7 @@ static struct clksrc_clk clk_vpllsrc = {
|
|||
.clk = {
|
||||
.name = "vpll_src",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clksrc_mask_top_ctrl,
|
||||
.enable = exynos4_clksrc_mask_top_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_vpllsrc,
|
||||
|
@ -389,239 +400,322 @@ static struct clk init_clocks_off[] = {
|
|||
.name = "timers",
|
||||
.id = -1,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1<<24),
|
||||
}, {
|
||||
.name = "csis",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clk_ip_cam_ctrl,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "csis",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clk_ip_cam_ctrl,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}, {
|
||||
.name = "fimc",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clk_ip_cam_ctrl,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "fimc",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clk_ip_cam_ctrl,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 1),
|
||||
}, {
|
||||
.name = "fimc",
|
||||
.id = 2,
|
||||
.enable = s5pv310_clk_ip_cam_ctrl,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 2),
|
||||
}, {
|
||||
.name = "fimc",
|
||||
.id = 3,
|
||||
.enable = s5pv310_clk_ip_cam_ctrl,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "fimd",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clk_ip_lcd0_ctrl,
|
||||
.enable = exynos4_clk_ip_lcd0_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "fimd",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clk_ip_lcd1_ctrl,
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "sataphy",
|
||||
.id = -1,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.id = 0,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.id = 1,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 6),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.id = 2,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 7),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.id = 3,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.id = 4,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 9),
|
||||
}, {
|
||||
.name = "sata",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl,
|
||||
.parent = &clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "pdma",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "pdma",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 1),
|
||||
}, {
|
||||
.name = "adc",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 15),
|
||||
}, {
|
||||
.name = "keypad",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_perir_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
}, {
|
||||
.name = "rtc",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clk_ip_perir_ctrl,
|
||||
.enable = exynos4_clk_ip_perir_ctrl,
|
||||
.ctrlbit = (1 << 15),
|
||||
}, {
|
||||
.name = "watchdog",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clk_ip_perir_ctrl,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = exynos4_clk_ip_perir_ctrl,
|
||||
.ctrlbit = (1 << 14),
|
||||
}, {
|
||||
.name = "usbhost",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl ,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl ,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "otg",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clk_ip_fsys_ctrl,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 13),
|
||||
}, {
|
||||
.name = "spi",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
}, {
|
||||
.name = "spi",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 17),
|
||||
}, {
|
||||
.name = "spi",
|
||||
.id = 2,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 18),
|
||||
}, {
|
||||
.name = "iis",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 19),
|
||||
}, {
|
||||
.name = "iis",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
}, {
|
||||
.name = "iis",
|
||||
.id = 2,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 21),
|
||||
}, {
|
||||
.name = "ac97",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 27),
|
||||
}, {
|
||||
.name = "fimg2d",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clk_ip_image_ctrl,
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 0,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 6),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 1,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 7),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 2,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 3,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 9),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 4,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 5,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 11),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 6,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "i2c",
|
||||
.id = 7,
|
||||
.parent = &clk_aclk_100.clk,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 13),
|
||||
},
|
||||
}, {
|
||||
.name = "SYSMMU_MDMA",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMC0",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 7),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMC1",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMC2",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 9),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMC3",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 10),
|
||||
}, {
|
||||
.name = "SYSMMU_JPEG",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_cam_ctrl,
|
||||
.ctrlbit = (1 << 11),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMD0",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_lcd0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "SYSMMU_FIMD1",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "SYSMMU_PCIe",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 18),
|
||||
}, {
|
||||
.name = "SYSMMU_G2D",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "SYSMMU_ROTATOR",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_image_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "SYSMMU_TV",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_tv_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "SYSMMU_MFC_L",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_mfc_ctrl,
|
||||
.ctrlbit = (1 << 1),
|
||||
}, {
|
||||
.name = "SYSMMU_MFC_R",
|
||||
.id = -1,
|
||||
.enable = exynos4_clk_ip_mfc_ctrl,
|
||||
.ctrlbit = (1 << 2),
|
||||
}
|
||||
};
|
||||
|
||||
static struct clk init_clocks[] = {
|
||||
{
|
||||
.name = "uart",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 1),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 2,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 2),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 3,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 4,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
}, {
|
||||
.name = "uart",
|
||||
.id = 5,
|
||||
.enable = s5pv310_clk_ip_peril_ctrl,
|
||||
.enable = exynos4_clk_ip_peril_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}
|
||||
};
|
||||
|
@ -746,7 +840,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "uclk1",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clksrc_mask_peril0_ctrl,
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -756,7 +850,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "uclk1",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clksrc_mask_peril0_ctrl,
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -766,7 +860,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "uclk1",
|
||||
.id = 2,
|
||||
.enable = s5pv310_clksrc_mask_peril0_ctrl,
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -776,7 +870,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "uclk1",
|
||||
.id = 3,
|
||||
.enable = s5pv310_clksrc_mask_peril0_ctrl,
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -786,7 +880,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_pwm",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clksrc_mask_peril0_ctrl,
|
||||
.enable = exynos4_clksrc_mask_peril0_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -796,7 +890,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_csis",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clksrc_mask_cam_ctrl,
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -806,7 +900,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_csis",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clksrc_mask_cam_ctrl,
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 28),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -816,7 +910,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clksrc_mask_cam_ctrl,
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -826,7 +920,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_cam",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clksrc_mask_cam_ctrl,
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -836,7 +930,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clksrc_mask_cam_ctrl,
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -846,7 +940,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clksrc_mask_cam_ctrl,
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -856,7 +950,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.id = 2,
|
||||
.enable = s5pv310_clksrc_mask_cam_ctrl,
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -866,7 +960,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_fimc",
|
||||
.id = 3,
|
||||
.enable = s5pv310_clksrc_mask_cam_ctrl,
|
||||
.enable = exynos4_clksrc_mask_cam_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -876,7 +970,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clksrc_mask_lcd0_ctrl,
|
||||
.enable = exynos4_clksrc_mask_lcd0_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -886,7 +980,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_fimd",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clksrc_mask_lcd1_ctrl,
|
||||
.enable = exynos4_clksrc_mask_lcd1_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -896,7 +990,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_sata",
|
||||
.id = -1,
|
||||
.enable = s5pv310_clksrc_mask_fsys_ctrl,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &clkset_mout_corebus,
|
||||
|
@ -906,7 +1000,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
.id = 0,
|
||||
.enable = s5pv310_clksrc_mask_peril1_ctrl,
|
||||
.enable = exynos4_clksrc_mask_peril1_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -916,7 +1010,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
.id = 1,
|
||||
.enable = s5pv310_clksrc_mask_peril1_ctrl,
|
||||
.enable = exynos4_clksrc_mask_peril1_ctrl,
|
||||
.ctrlbit = (1 << 20),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -926,7 +1020,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.clk = {
|
||||
.name = "sclk_spi",
|
||||
.id = 2,
|
||||
.enable = s5pv310_clksrc_mask_peril1_ctrl,
|
||||
.enable = exynos4_clksrc_mask_peril1_ctrl,
|
||||
.ctrlbit = (1 << 24),
|
||||
},
|
||||
.sources = &clkset_group,
|
||||
|
@ -945,7 +1039,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.name = "sclk_mmc",
|
||||
.id = 0,
|
||||
.parent = &clk_dout_mmc0.clk,
|
||||
.enable = s5pv310_clksrc_mask_fsys_ctrl,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
},
|
||||
.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 8, .size = 8 },
|
||||
|
@ -954,7 +1048,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.name = "sclk_mmc",
|
||||
.id = 1,
|
||||
.parent = &clk_dout_mmc1.clk,
|
||||
.enable = s5pv310_clksrc_mask_fsys_ctrl,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
},
|
||||
.reg_div = { .reg = S5P_CLKDIV_FSYS1, .shift = 24, .size = 8 },
|
||||
|
@ -963,7 +1057,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.name = "sclk_mmc",
|
||||
.id = 2,
|
||||
.parent = &clk_dout_mmc2.clk,
|
||||
.enable = s5pv310_clksrc_mask_fsys_ctrl,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
},
|
||||
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 8, .size = 8 },
|
||||
|
@ -972,7 +1066,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.name = "sclk_mmc",
|
||||
.id = 3,
|
||||
.parent = &clk_dout_mmc3.clk,
|
||||
.enable = s5pv310_clksrc_mask_fsys_ctrl,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
},
|
||||
.reg_div = { .reg = S5P_CLKDIV_FSYS2, .shift = 24, .size = 8 },
|
||||
|
@ -981,7 +1075,7 @@ static struct clksrc_clk clksrcs[] = {
|
|||
.name = "sclk_mmc",
|
||||
.id = 4,
|
||||
.parent = &clk_dout_mmc4.clk,
|
||||
.enable = s5pv310_clksrc_mask_fsys_ctrl,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 16),
|
||||
},
|
||||
.reg_div = { .reg = S5P_CLKDIV_FSYS3, .shift = 8, .size = 8 },
|
||||
|
@ -1022,16 +1116,16 @@ static struct clksrc_clk *sysclks[] = {
|
|||
|
||||
static int xtal_rate;
|
||||
|
||||
static unsigned long s5pv310_fout_apll_get_rate(struct clk *clk)
|
||||
static unsigned long exynos4_fout_apll_get_rate(struct clk *clk)
|
||||
{
|
||||
return s5p_get_pll45xx(xtal_rate, __raw_readl(S5P_APLL_CON0), pll_4508);
|
||||
}
|
||||
|
||||
static struct clk_ops s5pv310_fout_apll_ops = {
|
||||
.get_rate = s5pv310_fout_apll_get_rate,
|
||||
static struct clk_ops exynos4_fout_apll_ops = {
|
||||
.get_rate = exynos4_fout_apll_get_rate,
|
||||
};
|
||||
|
||||
void __init_or_cpufreq s5pv310_setup_clocks(void)
|
||||
void __init_or_cpufreq exynos4_setup_clocks(void)
|
||||
{
|
||||
struct clk *xtal_clk;
|
||||
unsigned long apll;
|
||||
|
@ -1070,12 +1164,12 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
|
|||
vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
|
||||
__raw_readl(S5P_VPLL_CON1), pll_4650);
|
||||
|
||||
clk_fout_apll.ops = &s5pv310_fout_apll_ops;
|
||||
clk_fout_apll.ops = &exynos4_fout_apll_ops;
|
||||
clk_fout_mpll.rate = mpll;
|
||||
clk_fout_epll.rate = epll;
|
||||
clk_fout_vpll.rate = vpll;
|
||||
|
||||
printk(KERN_INFO "S5PV310: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
|
||||
printk(KERN_INFO "EXYNOS4: PLL settings, A=%ld, M=%ld, E=%ld V=%ld",
|
||||
apll, mpll, epll, vpll);
|
||||
|
||||
armclk = clk_get_rate(&clk_armclk.clk);
|
||||
|
@ -1086,7 +1180,7 @@ void __init_or_cpufreq s5pv310_setup_clocks(void)
|
|||
aclk_160 = clk_get_rate(&clk_aclk_160.clk);
|
||||
aclk_133 = clk_get_rate(&clk_aclk_133.clk);
|
||||
|
||||
printk(KERN_INFO "S5PV310: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
|
||||
printk(KERN_INFO "EXYNOS4: ARMCLK=%ld, DMC=%ld, ACLK200=%ld\n"
|
||||
"ACLK100=%ld, ACLK160=%ld, ACLK133=%ld\n",
|
||||
armclk, sclk_dmc, aclk_200,
|
||||
aclk_100, aclk_160, aclk_133);
|
||||
|
@ -1103,7 +1197,7 @@ static struct clk *clks[] __initdata = {
|
|||
/* Nothing here yet */
|
||||
};
|
||||
|
||||
void __init s5pv310_register_clocks(void)
|
||||
void __init exynos4_register_clocks(void)
|
||||
{
|
||||
int ptr;
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/* linux/arch/arm/mach-s5pv310/cpu.c
|
||||
/* linux/arch/arm/mach-exynos4/cpu.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -19,8 +19,10 @@
|
|||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/s5pv310.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/fimc-core.h>
|
||||
|
||||
#include <mach/regs-irq.h>
|
||||
|
||||
|
@ -29,55 +31,60 @@ extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
|
|||
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
|
||||
|
||||
/* Initial IO mappings */
|
||||
static struct map_desc s5pv310_iodesc[] __initdata = {
|
||||
static struct map_desc exynos4_iodesc[] __initdata = {
|
||||
{
|
||||
.virtual = (unsigned long)S5P_VA_SYSTIMER,
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSTIMER),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SYSRAM,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_SYSRAM),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_SYSRAM),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_CMU,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_CMU),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_CMU),
|
||||
.length = SZ_128K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_PMU,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_PMU),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_PMU),
|
||||
.length = SZ_64K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_COMBINER_BASE,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_COMBINER),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_COMBINER),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_COREPERI_BASE,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_COREPERI),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_COREPERI),
|
||||
.length = SZ_8K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_L2CC,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_L2CC),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_L2CC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_GPIO1,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_GPIO1),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_GPIO2,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_GPIO2),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_GPIO3,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_GPIO3),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
|
||||
.length = SZ_256,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_DMC0,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_DMC0),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
}, {
|
||||
|
@ -87,13 +94,13 @@ static struct map_desc s5pv310_iodesc[] __initdata = {
|
|||
.type = MT_DEVICE,
|
||||
}, {
|
||||
.virtual = (unsigned long)S5P_VA_SROMC,
|
||||
.pfn = __phys_to_pfn(S5PV310_PA_SROMC),
|
||||
.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
|
||||
.length = SZ_4K,
|
||||
.type = MT_DEVICE,
|
||||
},
|
||||
};
|
||||
|
||||
static void s5pv310_idle(void)
|
||||
static void exynos4_idle(void)
|
||||
{
|
||||
if (!need_resched())
|
||||
cpu_do_idle();
|
||||
|
@ -101,32 +108,38 @@ static void s5pv310_idle(void)
|
|||
local_irq_enable();
|
||||
}
|
||||
|
||||
/* s5pv310_map_io
|
||||
/*
|
||||
* exynos4_map_io
|
||||
*
|
||||
* register the standard cpu IO areas
|
||||
*/
|
||||
void __init s5pv310_map_io(void)
|
||||
*/
|
||||
void __init exynos4_map_io(void)
|
||||
{
|
||||
iotable_init(s5pv310_iodesc, ARRAY_SIZE(s5pv310_iodesc));
|
||||
iotable_init(exynos4_iodesc, ARRAY_SIZE(exynos4_iodesc));
|
||||
|
||||
/* initialize device information early */
|
||||
s5pv310_default_sdhci0();
|
||||
s5pv310_default_sdhci1();
|
||||
s5pv310_default_sdhci2();
|
||||
s5pv310_default_sdhci3();
|
||||
exynos4_default_sdhci0();
|
||||
exynos4_default_sdhci1();
|
||||
exynos4_default_sdhci2();
|
||||
exynos4_default_sdhci3();
|
||||
|
||||
s3c_fimc_setname(0, "exynos4-fimc");
|
||||
s3c_fimc_setname(1, "exynos4-fimc");
|
||||
s3c_fimc_setname(2, "exynos4-fimc");
|
||||
s3c_fimc_setname(3, "exynos4-fimc");
|
||||
}
|
||||
|
||||
void __init s5pv310_init_clocks(int xtal)
|
||||
void __init exynos4_init_clocks(int xtal)
|
||||
{
|
||||
printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
|
||||
|
||||
s3c24xx_register_baseclocks(xtal);
|
||||
s5p_register_clocks(xtal);
|
||||
s5pv310_register_clocks();
|
||||
s5pv310_setup_clocks();
|
||||
exynos4_register_clocks();
|
||||
exynos4_setup_clocks();
|
||||
}
|
||||
|
||||
void __init s5pv310_init_irq(void)
|
||||
void __init exynos4_init_irq(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
|
@ -148,29 +161,29 @@ void __init s5pv310_init_irq(void)
|
|||
}
|
||||
|
||||
/* The parameters of s5p_init_irq() are for VIC init.
|
||||
* Theses parameters should be NULL and 0 because S5PV310
|
||||
* Theses parameters should be NULL and 0 because EXYNOS4
|
||||
* uses GIC instead of VIC.
|
||||
*/
|
||||
s5p_init_irq(NULL, 0);
|
||||
}
|
||||
|
||||
struct sysdev_class s5pv310_sysclass = {
|
||||
.name = "s5pv310-core",
|
||||
struct sysdev_class exynos4_sysclass = {
|
||||
.name = "exynos4-core",
|
||||
};
|
||||
|
||||
static struct sys_device s5pv310_sysdev = {
|
||||
.cls = &s5pv310_sysclass,
|
||||
static struct sys_device exynos4_sysdev = {
|
||||
.cls = &exynos4_sysclass,
|
||||
};
|
||||
|
||||
static int __init s5pv310_core_init(void)
|
||||
static int __init exynos4_core_init(void)
|
||||
{
|
||||
return sysdev_class_register(&s5pv310_sysclass);
|
||||
return sysdev_class_register(&exynos4_sysclass);
|
||||
}
|
||||
|
||||
core_initcall(s5pv310_core_init);
|
||||
core_initcall(exynos4_core_init);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
static int __init s5pv310_l2x0_cache_init(void)
|
||||
static int __init exynos4_l2x0_cache_init(void)
|
||||
{
|
||||
/* TAG, Data Latency Control: 2cycle */
|
||||
__raw_writel(0x110, S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL);
|
||||
|
@ -188,15 +201,15 @@ static int __init s5pv310_l2x0_cache_init(void)
|
|||
return 0;
|
||||
}
|
||||
|
||||
early_initcall(s5pv310_l2x0_cache_init);
|
||||
early_initcall(exynos4_l2x0_cache_init);
|
||||
#endif
|
||||
|
||||
int __init s5pv310_init(void)
|
||||
int __init exynos4_init(void)
|
||||
{
|
||||
printk(KERN_INFO "S5PV310: Initializing architecture\n");
|
||||
printk(KERN_INFO "EXYNOS4: Initializing architecture\n");
|
||||
|
||||
/* set idle function */
|
||||
pm_idle = s5pv310_idle;
|
||||
pm_idle = exynos4_idle;
|
||||
|
||||
return sysdev_register(&s5pv310_sysdev);
|
||||
return sysdev_register(&exynos4_sysdev);
|
||||
}
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/cpufreq.c
|
||||
/* linux/arch/arm/mach-exynos4/cpufreq.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - CPU frequency scaling support
|
||||
* EXYNOS4 - CPU frequency scaling support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -31,15 +31,13 @@ static struct clk *moutcore;
|
|||
static struct clk *mout_mpll;
|
||||
static struct clk *mout_apll;
|
||||
|
||||
#ifdef CONFIG_REGULATOR
|
||||
static struct regulator *arm_regulator;
|
||||
static struct regulator *int_regulator;
|
||||
#endif
|
||||
|
||||
static struct cpufreq_freqs freqs;
|
||||
static unsigned int memtype;
|
||||
|
||||
enum s5pv310_memory_type {
|
||||
enum exynos4_memory_type {
|
||||
DDR2 = 4,
|
||||
LPDDR2,
|
||||
DDR3,
|
||||
|
@ -49,7 +47,7 @@ enum cpufreq_level_index {
|
|||
L0, L1, L2, L3, CPUFREQ_LEVEL_END,
|
||||
};
|
||||
|
||||
static struct cpufreq_frequency_table s5pv310_freq_table[] = {
|
||||
static struct cpufreq_frequency_table exynos4_freq_table[] = {
|
||||
{L0, 1000*1000},
|
||||
{L1, 800*1000},
|
||||
{L2, 400*1000},
|
||||
|
@ -160,7 +158,7 @@ struct cpufreq_voltage_table {
|
|||
unsigned int int_volt;
|
||||
};
|
||||
|
||||
static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
|
||||
static struct cpufreq_voltage_table exynos4_volt_table[CPUFREQ_LEVEL_END] = {
|
||||
{
|
||||
.index = L0,
|
||||
.arm_volt = 1200000,
|
||||
|
@ -180,7 +178,7 @@ static struct cpufreq_voltage_table s5pv310_volt_table[CPUFREQ_LEVEL_END] = {
|
|||
},
|
||||
};
|
||||
|
||||
static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
|
||||
static unsigned int exynos4_apll_pms_table[CPUFREQ_LEVEL_END] = {
|
||||
/* APLL FOUT L0: 1000MHz */
|
||||
((250 << 16) | (6 << 8) | 1),
|
||||
|
||||
|
@ -194,17 +192,17 @@ static unsigned int s5pv310_apll_pms_table[CPUFREQ_LEVEL_END] = {
|
|||
((200 << 16) | (6 << 8) | 4),
|
||||
};
|
||||
|
||||
int s5pv310_verify_speed(struct cpufreq_policy *policy)
|
||||
int exynos4_verify_speed(struct cpufreq_policy *policy)
|
||||
{
|
||||
return cpufreq_frequency_table_verify(policy, s5pv310_freq_table);
|
||||
return cpufreq_frequency_table_verify(policy, exynos4_freq_table);
|
||||
}
|
||||
|
||||
unsigned int s5pv310_getspeed(unsigned int cpu)
|
||||
unsigned int exynos4_getspeed(unsigned int cpu)
|
||||
{
|
||||
return clk_get_rate(cpu_clk) / 1000;
|
||||
}
|
||||
|
||||
void s5pv310_set_clkdiv(unsigned int div_index)
|
||||
void exynos4_set_clkdiv(unsigned int div_index)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
|
@ -321,7 +319,7 @@ void s5pv310_set_clkdiv(unsigned int div_index)
|
|||
} while (tmp & 0x11);
|
||||
}
|
||||
|
||||
static void s5pv310_set_apll(unsigned int index)
|
||||
static void exynos4_set_apll(unsigned int index)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
|
@ -340,7 +338,7 @@ static void s5pv310_set_apll(unsigned int index)
|
|||
/* 3. Change PLL PMS values */
|
||||
tmp = __raw_readl(S5P_APLL_CON0);
|
||||
tmp &= ~((0x3ff << 16) | (0x3f << 8) | (0x7 << 0));
|
||||
tmp |= s5pv310_apll_pms_table[index];
|
||||
tmp |= exynos4_apll_pms_table[index];
|
||||
__raw_writel(tmp, S5P_APLL_CON0);
|
||||
|
||||
/* 4. wait_lock_time */
|
||||
|
@ -357,99 +355,95 @@ static void s5pv310_set_apll(unsigned int index)
|
|||
} while (tmp != (0x1 << S5P_CLKSRC_CPU_MUXCORE_SHIFT));
|
||||
}
|
||||
|
||||
static void s5pv310_set_frequency(unsigned int old_index, unsigned int new_index)
|
||||
static void exynos4_set_frequency(unsigned int old_index, unsigned int new_index)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
if (old_index > new_index) {
|
||||
/* The frequency changing to L0 needs to change apll */
|
||||
if (freqs.new == s5pv310_freq_table[L0].frequency) {
|
||||
if (freqs.new == exynos4_freq_table[L0].frequency) {
|
||||
/* 1. Change the system clock divider values */
|
||||
s5pv310_set_clkdiv(new_index);
|
||||
exynos4_set_clkdiv(new_index);
|
||||
|
||||
/* 2. Change the apll m,p,s value */
|
||||
s5pv310_set_apll(new_index);
|
||||
exynos4_set_apll(new_index);
|
||||
} else {
|
||||
/* 1. Change the system clock divider values */
|
||||
s5pv310_set_clkdiv(new_index);
|
||||
exynos4_set_clkdiv(new_index);
|
||||
|
||||
/* 2. Change just s value in apll m,p,s value */
|
||||
tmp = __raw_readl(S5P_APLL_CON0);
|
||||
tmp &= ~(0x7 << 0);
|
||||
tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
|
||||
tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
|
||||
__raw_writel(tmp, S5P_APLL_CON0);
|
||||
}
|
||||
}
|
||||
|
||||
else if (old_index < new_index) {
|
||||
/* The frequency changing from L0 needs to change apll */
|
||||
if (freqs.old == s5pv310_freq_table[L0].frequency) {
|
||||
if (freqs.old == exynos4_freq_table[L0].frequency) {
|
||||
/* 1. Change the apll m,p,s value */
|
||||
s5pv310_set_apll(new_index);
|
||||
exynos4_set_apll(new_index);
|
||||
|
||||
/* 2. Change the system clock divider values */
|
||||
s5pv310_set_clkdiv(new_index);
|
||||
exynos4_set_clkdiv(new_index);
|
||||
} else {
|
||||
/* 1. Change just s value in apll m,p,s value */
|
||||
tmp = __raw_readl(S5P_APLL_CON0);
|
||||
tmp &= ~(0x7 << 0);
|
||||
tmp |= (s5pv310_apll_pms_table[new_index] & 0x7);
|
||||
tmp |= (exynos4_apll_pms_table[new_index] & 0x7);
|
||||
__raw_writel(tmp, S5P_APLL_CON0);
|
||||
|
||||
/* 2. Change the system clock divider values */
|
||||
s5pv310_set_clkdiv(new_index);
|
||||
exynos4_set_clkdiv(new_index);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static int s5pv310_target(struct cpufreq_policy *policy,
|
||||
static int exynos4_target(struct cpufreq_policy *policy,
|
||||
unsigned int target_freq,
|
||||
unsigned int relation)
|
||||
{
|
||||
unsigned int index, old_index;
|
||||
unsigned int arm_volt, int_volt;
|
||||
|
||||
freqs.old = s5pv310_getspeed(policy->cpu);
|
||||
freqs.old = exynos4_getspeed(policy->cpu);
|
||||
|
||||
if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
|
||||
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
|
||||
freqs.old, relation, &old_index))
|
||||
return -EINVAL;
|
||||
|
||||
if (cpufreq_frequency_table_target(policy, s5pv310_freq_table,
|
||||
if (cpufreq_frequency_table_target(policy, exynos4_freq_table,
|
||||
target_freq, relation, &index))
|
||||
return -EINVAL;
|
||||
|
||||
freqs.new = s5pv310_freq_table[index].frequency;
|
||||
freqs.new = exynos4_freq_table[index].frequency;
|
||||
freqs.cpu = policy->cpu;
|
||||
|
||||
if (freqs.new == freqs.old)
|
||||
return 0;
|
||||
|
||||
/* get the voltage value */
|
||||
arm_volt = s5pv310_volt_table[index].arm_volt;
|
||||
int_volt = s5pv310_volt_table[index].int_volt;
|
||||
arm_volt = exynos4_volt_table[index].arm_volt;
|
||||
int_volt = exynos4_volt_table[index].int_volt;
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
|
||||
|
||||
/* control regulator */
|
||||
if (freqs.new > freqs.old) {
|
||||
/* Voltage up */
|
||||
#ifdef CONFIG_REGULATOR
|
||||
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
|
||||
regulator_set_voltage(int_regulator, int_volt, int_volt);
|
||||
#endif
|
||||
}
|
||||
|
||||
/* Clock Configuration Procedure */
|
||||
s5pv310_set_frequency(old_index, index);
|
||||
exynos4_set_frequency(old_index, index);
|
||||
|
||||
/* control regulator */
|
||||
if (freqs.new < freqs.old) {
|
||||
/* Voltage down */
|
||||
#ifdef CONFIG_REGULATOR
|
||||
regulator_set_voltage(arm_regulator, arm_volt, arm_volt);
|
||||
regulator_set_voltage(int_regulator, int_volt, int_volt);
|
||||
#endif
|
||||
}
|
||||
|
||||
cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
|
||||
|
@ -458,52 +452,52 @@ static int s5pv310_target(struct cpufreq_policy *policy,
|
|||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int s5pv310_cpufreq_suspend(struct cpufreq_policy *policy,
|
||||
static int exynos4_cpufreq_suspend(struct cpufreq_policy *policy,
|
||||
pm_message_t pmsg)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int s5pv310_cpufreq_resume(struct cpufreq_policy *policy)
|
||||
static int exynos4_cpufreq_resume(struct cpufreq_policy *policy)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
static int s5pv310_cpufreq_cpu_init(struct cpufreq_policy *policy)
|
||||
static int exynos4_cpufreq_cpu_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
policy->cur = policy->min = policy->max = s5pv310_getspeed(policy->cpu);
|
||||
policy->cur = policy->min = policy->max = exynos4_getspeed(policy->cpu);
|
||||
|
||||
cpufreq_frequency_table_get_attr(s5pv310_freq_table, policy->cpu);
|
||||
cpufreq_frequency_table_get_attr(exynos4_freq_table, policy->cpu);
|
||||
|
||||
/* set the transition latency value */
|
||||
policy->cpuinfo.transition_latency = 100000;
|
||||
|
||||
/*
|
||||
* S5PV310 multi-core processors has 2 cores
|
||||
* EXYNOS4 multi-core processors has 2 cores
|
||||
* that the frequency cannot be set independently.
|
||||
* Each cpu is bound to the same speed.
|
||||
* So the affected cpu is all of the cpus.
|
||||
*/
|
||||
cpumask_setall(policy->cpus);
|
||||
|
||||
return cpufreq_frequency_table_cpuinfo(policy, s5pv310_freq_table);
|
||||
return cpufreq_frequency_table_cpuinfo(policy, exynos4_freq_table);
|
||||
}
|
||||
|
||||
static struct cpufreq_driver s5pv310_driver = {
|
||||
static struct cpufreq_driver exynos4_driver = {
|
||||
.flags = CPUFREQ_STICKY,
|
||||
.verify = s5pv310_verify_speed,
|
||||
.target = s5pv310_target,
|
||||
.get = s5pv310_getspeed,
|
||||
.init = s5pv310_cpufreq_cpu_init,
|
||||
.name = "s5pv310_cpufreq",
|
||||
.verify = exynos4_verify_speed,
|
||||
.target = exynos4_target,
|
||||
.get = exynos4_getspeed,
|
||||
.init = exynos4_cpufreq_cpu_init,
|
||||
.name = "exynos4_cpufreq",
|
||||
#ifdef CONFIG_PM
|
||||
.suspend = s5pv310_cpufreq_suspend,
|
||||
.resume = s5pv310_cpufreq_resume,
|
||||
.suspend = exynos4_cpufreq_suspend,
|
||||
.resume = exynos4_cpufreq_resume,
|
||||
#endif
|
||||
};
|
||||
|
||||
static int __init s5pv310_cpufreq_init(void)
|
||||
static int __init exynos4_cpufreq_init(void)
|
||||
{
|
||||
cpu_clk = clk_get(NULL, "armclk");
|
||||
if (IS_ERR(cpu_clk))
|
||||
|
@ -521,7 +515,6 @@ static int __init s5pv310_cpufreq_init(void)
|
|||
if (IS_ERR(mout_apll))
|
||||
goto out;
|
||||
|
||||
#ifdef CONFIG_REGULATOR
|
||||
arm_regulator = regulator_get(NULL, "vdd_arm");
|
||||
if (IS_ERR(arm_regulator)) {
|
||||
printk(KERN_ERR "failed to get resource %s\n", "vdd_arm");
|
||||
|
@ -533,7 +526,6 @@ static int __init s5pv310_cpufreq_init(void)
|
|||
printk(KERN_ERR "failed to get resource %s\n", "vdd_int");
|
||||
goto out;
|
||||
}
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check DRAM type.
|
||||
|
@ -550,7 +542,7 @@ static int __init s5pv310_cpufreq_init(void)
|
|||
printk(KERN_DEBUG "%s: memtype= 0x%x\n", __func__, memtype);
|
||||
}
|
||||
|
||||
return cpufreq_register_driver(&s5pv310_driver);
|
||||
return cpufreq_register_driver(&exynos4_driver);
|
||||
|
||||
out:
|
||||
if (!IS_ERR(cpu_clk))
|
||||
|
@ -565,16 +557,14 @@ static int __init s5pv310_cpufreq_init(void)
|
|||
if (!IS_ERR(mout_apll))
|
||||
clk_put(mout_apll);
|
||||
|
||||
#ifdef CONFIG_REGULATOR
|
||||
if (!IS_ERR(arm_regulator))
|
||||
regulator_put(arm_regulator);
|
||||
|
||||
if (!IS_ERR(int_regulator))
|
||||
regulator_put(int_regulator);
|
||||
#endif
|
||||
|
||||
printk(KERN_ERR "%s: failed initialization\n", __func__);
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
late_initcall(s5pv310_cpufreq_init);
|
||||
late_initcall(exynos4_cpufreq_init);
|
263
arch/arm/mach-exynos4/dev-ahci.c
Normal file
263
arch/arm/mach-exynos4/dev-ahci.c
Normal file
|
@ -0,0 +1,263 @@
|
|||
/* linux/arch/arm/mach-exynos4/dev-ahci.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - AHCI support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/ahci_platform.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
/* PHY Control Register */
|
||||
#define SATA_CTRL0 0x0
|
||||
/* PHY Link Control Register */
|
||||
#define SATA_CTRL1 0x4
|
||||
/* PHY Status Register */
|
||||
#define SATA_PHY_STATUS 0x8
|
||||
|
||||
#define SATA_CTRL0_RX_DATA_VALID(x) (x << 27)
|
||||
#define SATA_CTRL0_SPEED_MODE (1 << 26)
|
||||
#define SATA_CTRL0_M_PHY_CAL (1 << 19)
|
||||
#define SATA_CTRL0_PHY_CMU_RST_N (1 << 10)
|
||||
#define SATA_CTRL0_M_PHY_LN_RST_N (1 << 9)
|
||||
#define SATA_CTRL0_PHY_POR_N (1 << 8)
|
||||
|
||||
#define SATA_CTRL1_RST_PMALIVE_N (1 << 8)
|
||||
#define SATA_CTRL1_RST_RXOOB_N (1 << 7)
|
||||
#define SATA_CTRL1_RST_RX_N (1 << 6)
|
||||
#define SATA_CTRL1_RST_TX_N (1 << 5)
|
||||
|
||||
#define SATA_PHY_STATUS_CMU_OK (1 << 18)
|
||||
#define SATA_PHY_STATUS_LANE_OK (1 << 16)
|
||||
|
||||
#define LANE0 0x200
|
||||
#define COM_LANE 0xA00
|
||||
|
||||
#define HOST_PORTS_IMPL 0xC
|
||||
#define SCLK_SATA_FREQ (67 * MHZ)
|
||||
|
||||
static void __iomem *phy_base, *phy_ctrl;
|
||||
|
||||
struct phy_reg {
|
||||
u8 reg;
|
||||
u8 val;
|
||||
};
|
||||
|
||||
/* SATA PHY setup */
|
||||
static const struct phy_reg exynos4_sataphy_cmu[] = {
|
||||
{ 0x00, 0x06 }, { 0x02, 0x80 }, { 0x22, 0xa0 }, { 0x23, 0x42 },
|
||||
{ 0x2e, 0x04 }, { 0x2f, 0x50 }, { 0x30, 0x70 }, { 0x31, 0x02 },
|
||||
{ 0x32, 0x25 }, { 0x33, 0x40 }, { 0x34, 0x01 }, { 0x35, 0x40 },
|
||||
{ 0x61, 0x2e }, { 0x63, 0x5e }, { 0x65, 0x42 }, { 0x66, 0xd1 },
|
||||
{ 0x67, 0x20 }, { 0x68, 0x28 }, { 0x69, 0x78 }, { 0x6a, 0x04 },
|
||||
{ 0x6b, 0xc8 }, { 0x6c, 0x06 },
|
||||
};
|
||||
|
||||
static const struct phy_reg exynos4_sataphy_lane[] = {
|
||||
{ 0x00, 0x02 }, { 0x05, 0x10 }, { 0x06, 0x84 }, { 0x07, 0x04 },
|
||||
{ 0x08, 0xe0 }, { 0x10, 0x23 }, { 0x13, 0x05 }, { 0x14, 0x30 },
|
||||
{ 0x15, 0x00 }, { 0x17, 0x70 }, { 0x18, 0xf2 }, { 0x19, 0x1e },
|
||||
{ 0x1a, 0x18 }, { 0x1b, 0x0d }, { 0x1c, 0x08 }, { 0x50, 0x60 },
|
||||
{ 0x51, 0x0f },
|
||||
};
|
||||
|
||||
static const struct phy_reg exynos4_sataphy_comlane[] = {
|
||||
{ 0x01, 0x20 }, { 0x03, 0x40 }, { 0x04, 0x3c }, { 0x05, 0x7d },
|
||||
{ 0x06, 0x1d }, { 0x07, 0xcf }, { 0x08, 0x05 }, { 0x09, 0x63 },
|
||||
{ 0x0a, 0x29 }, { 0x0b, 0xc4 }, { 0x0c, 0x01 }, { 0x0d, 0x03 },
|
||||
{ 0x0e, 0x28 }, { 0x0f, 0x98 }, { 0x10, 0x19 }, { 0x13, 0x80 },
|
||||
{ 0x14, 0xf0 }, { 0x15, 0xd0 }, { 0x39, 0xa0 }, { 0x3a, 0xa0 },
|
||||
{ 0x3b, 0xa0 }, { 0x3c, 0xa0 }, { 0x3d, 0xa0 }, { 0x3e, 0xa0 },
|
||||
{ 0x3f, 0xa0 }, { 0x40, 0x42 }, { 0x42, 0x80 }, { 0x43, 0x58 },
|
||||
{ 0x45, 0x44 }, { 0x46, 0x5c }, { 0x47, 0x86 }, { 0x48, 0x8d },
|
||||
{ 0x49, 0xd0 }, { 0x4a, 0x09 }, { 0x4b, 0x90 }, { 0x4c, 0x07 },
|
||||
{ 0x4d, 0x40 }, { 0x51, 0x20 }, { 0x52, 0x32 }, { 0x7f, 0xd8 },
|
||||
{ 0x80, 0x1a }, { 0x81, 0xff }, { 0x82, 0x11 }, { 0x83, 0x00 },
|
||||
{ 0x87, 0xf0 }, { 0x87, 0xff }, { 0x87, 0xff }, { 0x87, 0xff },
|
||||
{ 0x87, 0xff }, { 0x8c, 0x1c }, { 0x8d, 0xc2 }, { 0x8e, 0xc3 },
|
||||
{ 0x8f, 0x3f }, { 0x90, 0x0a }, { 0x96, 0xf8 },
|
||||
};
|
||||
|
||||
static int wait_for_phy_ready(void __iomem *reg, unsigned long bit)
|
||||
{
|
||||
unsigned long timeout;
|
||||
|
||||
/* wait for maximum of 3 sec */
|
||||
timeout = jiffies + msecs_to_jiffies(3000);
|
||||
while (!(__raw_readl(reg) & bit)) {
|
||||
if (time_after(jiffies, timeout))
|
||||
return -1;
|
||||
cpu_relax();
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int ahci_phy_init(void __iomem *mmio)
|
||||
{
|
||||
int i, ctrl0;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_cmu); i++)
|
||||
__raw_writeb(exynos4_sataphy_cmu[i].val,
|
||||
phy_base + (exynos4_sataphy_cmu[i].reg * 4));
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_lane); i++)
|
||||
__raw_writeb(exynos4_sataphy_lane[i].val,
|
||||
phy_base + (LANE0 + exynos4_sataphy_lane[i].reg) * 4);
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(exynos4_sataphy_comlane); i++)
|
||||
__raw_writeb(exynos4_sataphy_comlane[i].val,
|
||||
phy_base + (COM_LANE + exynos4_sataphy_comlane[i].reg) * 4);
|
||||
|
||||
__raw_writeb(0x07, phy_base);
|
||||
|
||||
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
|
||||
ctrl0 |= SATA_CTRL0_PHY_CMU_RST_N;
|
||||
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
|
||||
SATA_PHY_STATUS_CMU_OK) < 0) {
|
||||
printk(KERN_ERR "PHY CMU not ready\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
__raw_writeb(0x03, phy_base + (COM_LANE * 4));
|
||||
|
||||
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
|
||||
ctrl0 |= SATA_CTRL0_M_PHY_LN_RST_N;
|
||||
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
if (wait_for_phy_ready(phy_ctrl + SATA_PHY_STATUS,
|
||||
SATA_PHY_STATUS_LANE_OK) < 0) {
|
||||
printk(KERN_ERR "PHY LANE not ready\n");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
ctrl0 = __raw_readl(phy_ctrl + SATA_CTRL0);
|
||||
ctrl0 |= SATA_CTRL0_M_PHY_CAL;
|
||||
__raw_writel(ctrl0, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int exynos4_ahci_init(struct device *dev, void __iomem *mmio)
|
||||
{
|
||||
struct clk *clk_sata, *clk_sataphy, *clk_sclk_sata;
|
||||
int val, ret;
|
||||
|
||||
phy_base = ioremap(EXYNOS4_PA_SATAPHY, SZ_64K);
|
||||
if (!phy_base) {
|
||||
dev_err(dev, "failed to allocate memory for SATA PHY\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
phy_ctrl = ioremap(EXYNOS4_PA_SATAPHY_CTRL, SZ_16);
|
||||
if (!phy_ctrl) {
|
||||
dev_err(dev, "failed to allocate memory for SATA PHY CTRL\n");
|
||||
ret = -ENOMEM;
|
||||
goto err1;
|
||||
}
|
||||
|
||||
clk_sata = clk_get(dev, "sata");
|
||||
if (IS_ERR(clk_sata)) {
|
||||
dev_err(dev, "failed to get sata clock\n");
|
||||
ret = PTR_ERR(clk_sata);
|
||||
clk_sata = NULL;
|
||||
goto err2;
|
||||
|
||||
}
|
||||
clk_enable(clk_sata);
|
||||
|
||||
clk_sataphy = clk_get(dev, "sataphy");
|
||||
if (IS_ERR(clk_sataphy)) {
|
||||
dev_err(dev, "failed to get sataphy clock\n");
|
||||
ret = PTR_ERR(clk_sataphy);
|
||||
clk_sataphy = NULL;
|
||||
goto err3;
|
||||
}
|
||||
clk_enable(clk_sataphy);
|
||||
|
||||
clk_sclk_sata = clk_get(dev, "sclk_sata");
|
||||
if (IS_ERR(clk_sclk_sata)) {
|
||||
dev_err(dev, "failed to get sclk_sata\n");
|
||||
ret = PTR_ERR(clk_sclk_sata);
|
||||
clk_sclk_sata = NULL;
|
||||
goto err4;
|
||||
}
|
||||
clk_enable(clk_sclk_sata);
|
||||
clk_set_rate(clk_sclk_sata, SCLK_SATA_FREQ);
|
||||
|
||||
__raw_writel(S5P_PMU_SATA_PHY_CONTROL_EN, S5P_PMU_SATA_PHY_CONTROL);
|
||||
|
||||
/* Enable PHY link control */
|
||||
val = SATA_CTRL1_RST_PMALIVE_N | SATA_CTRL1_RST_RXOOB_N |
|
||||
SATA_CTRL1_RST_RX_N | SATA_CTRL1_RST_TX_N;
|
||||
__raw_writel(val, phy_ctrl + SATA_CTRL1);
|
||||
|
||||
/* Set communication speed as 3Gbps and enable PHY power */
|
||||
val = SATA_CTRL0_RX_DATA_VALID(3) | SATA_CTRL0_SPEED_MODE |
|
||||
SATA_CTRL0_PHY_POR_N;
|
||||
__raw_writel(val, phy_ctrl + SATA_CTRL0);
|
||||
|
||||
/* Port0 is available */
|
||||
__raw_writel(0x1, mmio + HOST_PORTS_IMPL);
|
||||
|
||||
return ahci_phy_init(mmio);
|
||||
|
||||
err4:
|
||||
clk_disable(clk_sataphy);
|
||||
clk_put(clk_sataphy);
|
||||
err3:
|
||||
clk_disable(clk_sata);
|
||||
clk_put(clk_sata);
|
||||
err2:
|
||||
iounmap(phy_ctrl);
|
||||
err1:
|
||||
iounmap(phy_base);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct ahci_platform_data exynos4_ahci_pdata = {
|
||||
.init = exynos4_ahci_init,
|
||||
};
|
||||
|
||||
static struct resource exynos4_ahci_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_SATA,
|
||||
.end = EXYNOS4_PA_SATA + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_SATA,
|
||||
.end = IRQ_SATA,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
};
|
||||
|
||||
static u64 exynos4_ahci_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device exynos4_device_ahci = {
|
||||
.name = "ahci",
|
||||
.id = -1,
|
||||
.resource = exynos4_ahci_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_ahci_resource),
|
||||
.dev = {
|
||||
.platform_data = &exynos4_ahci_pdata,
|
||||
.dma_mask = &exynos4_ahci_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
|
@ -1,4 +1,7 @@
|
|||
/* linux/arch/arm/mach-s5pv310/dev-audio.c
|
||||
/* linux/arch/arm/mach-exynos4/dev-audio.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co. Ltd
|
||||
* Jaswinder Singh <jassi.brar@samsung.com>
|
||||
|
@ -24,18 +27,18 @@ static const char *rclksrc[] = {
|
|||
[1] = "i2sclk",
|
||||
};
|
||||
|
||||
static int s5pv310_cfg_i2s(struct platform_device *pdev)
|
||||
static int exynos4_cfg_i2s(struct platform_device *pdev)
|
||||
{
|
||||
/* configure GPIO for i2s port */
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 7, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 7, S3C_GPIO_SFN(2));
|
||||
break;
|
||||
case 1:
|
||||
s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(2));
|
||||
break;
|
||||
case 2:
|
||||
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(4));
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(4));
|
||||
break;
|
||||
default:
|
||||
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
|
||||
|
@ -46,7 +49,7 @@ static int s5pv310_cfg_i2s(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static struct s3c_audio_pdata i2sv5_pdata = {
|
||||
.cfg_gpio = s5pv310_cfg_i2s,
|
||||
.cfg_gpio = exynos4_cfg_i2s,
|
||||
.type = {
|
||||
.i2s = {
|
||||
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
|
||||
|
@ -56,10 +59,10 @@ static struct s3c_audio_pdata i2sv5_pdata = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct resource s5pv310_i2s0_resource[] = {
|
||||
static struct resource exynos4_i2s0_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_I2S0,
|
||||
.end = S5PV310_PA_I2S0 + 0x100 - 1,
|
||||
.start = EXYNOS4_PA_I2S0,
|
||||
.end = EXYNOS4_PA_I2S0 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -79,11 +82,11 @@ static struct resource s5pv310_i2s0_resource[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct platform_device s5pv310_device_i2s0 = {
|
||||
struct platform_device exynos4_device_i2s0 = {
|
||||
.name = "samsung-i2s",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_i2s0_resource),
|
||||
.resource = s5pv310_i2s0_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_i2s0_resource),
|
||||
.resource = exynos4_i2s0_resource,
|
||||
.dev = {
|
||||
.platform_data = &i2sv5_pdata,
|
||||
},
|
||||
|
@ -95,7 +98,7 @@ static const char *rclksrc_v3[] = {
|
|||
};
|
||||
|
||||
static struct s3c_audio_pdata i2sv3_pdata = {
|
||||
.cfg_gpio = s5pv310_cfg_i2s,
|
||||
.cfg_gpio = exynos4_cfg_i2s,
|
||||
.type = {
|
||||
.i2s = {
|
||||
.quirks = QUIRK_NO_MUXPSR,
|
||||
|
@ -104,10 +107,10 @@ static struct s3c_audio_pdata i2sv3_pdata = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct resource s5pv310_i2s1_resource[] = {
|
||||
static struct resource exynos4_i2s1_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_I2S1,
|
||||
.end = S5PV310_PA_I2S1 + 0x100 - 1,
|
||||
.start = EXYNOS4_PA_I2S1,
|
||||
.end = EXYNOS4_PA_I2S1 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -122,20 +125,20 @@ static struct resource s5pv310_i2s1_resource[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct platform_device s5pv310_device_i2s1 = {
|
||||
struct platform_device exynos4_device_i2s1 = {
|
||||
.name = "samsung-i2s",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_i2s1_resource),
|
||||
.resource = s5pv310_i2s1_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_i2s1_resource),
|
||||
.resource = exynos4_i2s1_resource,
|
||||
.dev = {
|
||||
.platform_data = &i2sv3_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource s5pv310_i2s2_resource[] = {
|
||||
static struct resource exynos4_i2s2_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_I2S2,
|
||||
.end = S5PV310_PA_I2S2 + 0x100 - 1,
|
||||
.start = EXYNOS4_PA_I2S2,
|
||||
.end = EXYNOS4_PA_I2S2 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -150,11 +153,11 @@ static struct resource s5pv310_i2s2_resource[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct platform_device s5pv310_device_i2s2 = {
|
||||
struct platform_device exynos4_device_i2s2 = {
|
||||
.name = "samsung-i2s",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_i2s2_resource),
|
||||
.resource = s5pv310_i2s2_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_i2s2_resource),
|
||||
.resource = exynos4_i2s2_resource,
|
||||
.dev = {
|
||||
.platform_data = &i2sv3_pdata,
|
||||
},
|
||||
|
@ -162,17 +165,17 @@ struct platform_device s5pv310_device_i2s2 = {
|
|||
|
||||
/* PCM Controller platform_devices */
|
||||
|
||||
static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
static int exynos4_pcm_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
switch (pdev->id) {
|
||||
case 0:
|
||||
s3c_gpio_cfgpin_range(S5PV310_GPZ(0), 5, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPZ(0), 5, S3C_GPIO_SFN(3));
|
||||
break;
|
||||
case 1:
|
||||
s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(3));
|
||||
break;
|
||||
case 2:
|
||||
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 5, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 5, S3C_GPIO_SFN(3));
|
||||
break;
|
||||
default:
|
||||
printk(KERN_DEBUG "Invalid PCM Controller number!");
|
||||
|
@ -183,13 +186,13 @@ static int s5pv310_pcm_cfg_gpio(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
static struct s3c_audio_pdata s3c_pcm_pdata = {
|
||||
.cfg_gpio = s5pv310_pcm_cfg_gpio,
|
||||
.cfg_gpio = exynos4_pcm_cfg_gpio,
|
||||
};
|
||||
|
||||
static struct resource s5pv310_pcm0_resource[] = {
|
||||
static struct resource exynos4_pcm0_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_PCM0,
|
||||
.end = S5PV310_PA_PCM0 + 0x100 - 1,
|
||||
.start = EXYNOS4_PA_PCM0,
|
||||
.end = EXYNOS4_PA_PCM0 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -204,20 +207,20 @@ static struct resource s5pv310_pcm0_resource[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct platform_device s5pv310_device_pcm0 = {
|
||||
struct platform_device exynos4_device_pcm0 = {
|
||||
.name = "samsung-pcm",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_pcm0_resource),
|
||||
.resource = s5pv310_pcm0_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pcm0_resource),
|
||||
.resource = exynos4_pcm0_resource,
|
||||
.dev = {
|
||||
.platform_data = &s3c_pcm_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource s5pv310_pcm1_resource[] = {
|
||||
static struct resource exynos4_pcm1_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_PCM1,
|
||||
.end = S5PV310_PA_PCM1 + 0x100 - 1,
|
||||
.start = EXYNOS4_PA_PCM1,
|
||||
.end = EXYNOS4_PA_PCM1 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -232,20 +235,20 @@ static struct resource s5pv310_pcm1_resource[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct platform_device s5pv310_device_pcm1 = {
|
||||
struct platform_device exynos4_device_pcm1 = {
|
||||
.name = "samsung-pcm",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_pcm1_resource),
|
||||
.resource = s5pv310_pcm1_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pcm1_resource),
|
||||
.resource = exynos4_pcm1_resource,
|
||||
.dev = {
|
||||
.platform_data = &s3c_pcm_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource s5pv310_pcm2_resource[] = {
|
||||
static struct resource exynos4_pcm2_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_PCM2,
|
||||
.end = S5PV310_PA_PCM2 + 0x100 - 1,
|
||||
.start = EXYNOS4_PA_PCM2,
|
||||
.end = EXYNOS4_PA_PCM2 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -260,11 +263,11 @@ static struct resource s5pv310_pcm2_resource[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct platform_device s5pv310_device_pcm2 = {
|
||||
struct platform_device exynos4_device_pcm2 = {
|
||||
.name = "samsung-pcm",
|
||||
.id = 2,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_pcm2_resource),
|
||||
.resource = s5pv310_pcm2_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pcm2_resource),
|
||||
.resource = exynos4_pcm2_resource,
|
||||
.dev = {
|
||||
.platform_data = &s3c_pcm_pdata,
|
||||
},
|
||||
|
@ -272,15 +275,15 @@ struct platform_device s5pv310_device_pcm2 = {
|
|||
|
||||
/* AC97 Controller platform devices */
|
||||
|
||||
static int s5pv310_ac97_cfg_gpio(struct platform_device *pdev)
|
||||
static int exynos4_ac97_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
return s3c_gpio_cfgpin_range(S5PV310_GPC0(0), 5, S3C_GPIO_SFN(4));
|
||||
return s3c_gpio_cfgpin_range(EXYNOS4_GPC0(0), 5, S3C_GPIO_SFN(4));
|
||||
}
|
||||
|
||||
static struct resource s5pv310_ac97_resource[] = {
|
||||
static struct resource exynos4_ac97_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_AC97,
|
||||
.end = S5PV310_PA_AC97 + 0x100 - 1,
|
||||
.start = EXYNOS4_PA_AC97,
|
||||
.end = EXYNOS4_PA_AC97 + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -306,36 +309,36 @@ static struct resource s5pv310_ac97_resource[] = {
|
|||
};
|
||||
|
||||
static struct s3c_audio_pdata s3c_ac97_pdata = {
|
||||
.cfg_gpio = s5pv310_ac97_cfg_gpio,
|
||||
.cfg_gpio = exynos4_ac97_cfg_gpio,
|
||||
};
|
||||
|
||||
static u64 s5pv310_ac97_dmamask = DMA_BIT_MASK(32);
|
||||
static u64 exynos4_ac97_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device s5pv310_device_ac97 = {
|
||||
struct platform_device exynos4_device_ac97 = {
|
||||
.name = "samsung-ac97",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_ac97_resource),
|
||||
.resource = s5pv310_ac97_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_ac97_resource),
|
||||
.resource = exynos4_ac97_resource,
|
||||
.dev = {
|
||||
.platform_data = &s3c_ac97_pdata,
|
||||
.dma_mask = &s5pv310_ac97_dmamask,
|
||||
.dma_mask = &exynos4_ac97_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
||||
|
||||
/* S/PDIF Controller platform_device */
|
||||
|
||||
static int s5pv310_spdif_cfg_gpio(struct platform_device *pdev)
|
||||
static int exynos4_spdif_cfg_gpio(struct platform_device *pdev)
|
||||
{
|
||||
s3c_gpio_cfgpin_range(S5PV310_GPC1(0), 2, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_cfgpin_range(EXYNOS4_GPC1(0), 2, S3C_GPIO_SFN(3));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct resource s5pv310_spdif_resource[] = {
|
||||
static struct resource exynos4_spdif_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_SPDIF,
|
||||
.end = S5PV310_PA_SPDIF + 0x100 - 1,
|
||||
.start = EXYNOS4_PA_SPDIF,
|
||||
.end = EXYNOS4_PA_SPDIF + 0x100 - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -346,19 +349,19 @@ static struct resource s5pv310_spdif_resource[] = {
|
|||
};
|
||||
|
||||
static struct s3c_audio_pdata samsung_spdif_pdata = {
|
||||
.cfg_gpio = s5pv310_spdif_cfg_gpio,
|
||||
.cfg_gpio = exynos4_spdif_cfg_gpio,
|
||||
};
|
||||
|
||||
static u64 s5pv310_spdif_dmamask = DMA_BIT_MASK(32);
|
||||
static u64 exynos4_spdif_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
struct platform_device s5pv310_device_spdif = {
|
||||
struct platform_device exynos4_device_spdif = {
|
||||
.name = "samsung-spdif",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_spdif_resource),
|
||||
.resource = s5pv310_spdif_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_spdif_resource),
|
||||
.resource = exynos4_spdif_resource,
|
||||
.dev = {
|
||||
.platform_data = &samsung_spdif_pdata,
|
||||
.dma_mask = &s5pv310_spdif_dmamask,
|
||||
.dma_mask = &exynos4_spdif_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
};
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/dev-pd.c
|
||||
/* linux/arch/arm/mach-exynos4/dev-pd.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - Power Domain support
|
||||
* EXYNOS4 - Power Domain support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -19,7 +19,7 @@
|
|||
|
||||
#include <plat/pd.h>
|
||||
|
||||
static int s5pv310_pd_enable(struct device *dev)
|
||||
static int exynos4_pd_enable(struct device *dev)
|
||||
{
|
||||
struct samsung_pd_info *pdata = dev->platform_data;
|
||||
u32 timeout;
|
||||
|
@ -42,7 +42,7 @@ static int s5pv310_pd_enable(struct device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int s5pv310_pd_disable(struct device *dev)
|
||||
static int exynos4_pd_disable(struct device *dev)
|
||||
{
|
||||
struct samsung_pd_info *pdata = dev->platform_data;
|
||||
u32 timeout;
|
||||
|
@ -64,14 +64,14 @@ static int s5pv310_pd_disable(struct device *dev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
struct platform_device s5pv310_device_pd[] = {
|
||||
struct platform_device exynos4_device_pd[] = {
|
||||
{
|
||||
.name = "samsung-pd",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &(struct samsung_pd_info) {
|
||||
.enable = s5pv310_pd_enable,
|
||||
.disable = s5pv310_pd_disable,
|
||||
.enable = exynos4_pd_enable,
|
||||
.disable = exynos4_pd_disable,
|
||||
.base = S5P_PMU_MFC_CONF,
|
||||
},
|
||||
},
|
||||
|
@ -80,8 +80,8 @@ struct platform_device s5pv310_device_pd[] = {
|
|||
.id = 1,
|
||||
.dev = {
|
||||
.platform_data = &(struct samsung_pd_info) {
|
||||
.enable = s5pv310_pd_enable,
|
||||
.disable = s5pv310_pd_disable,
|
||||
.enable = exynos4_pd_enable,
|
||||
.disable = exynos4_pd_disable,
|
||||
.base = S5P_PMU_G3D_CONF,
|
||||
},
|
||||
},
|
||||
|
@ -90,8 +90,8 @@ struct platform_device s5pv310_device_pd[] = {
|
|||
.id = 2,
|
||||
.dev = {
|
||||
.platform_data = &(struct samsung_pd_info) {
|
||||
.enable = s5pv310_pd_enable,
|
||||
.disable = s5pv310_pd_disable,
|
||||
.enable = exynos4_pd_enable,
|
||||
.disable = exynos4_pd_disable,
|
||||
.base = S5P_PMU_LCD0_CONF,
|
||||
},
|
||||
},
|
||||
|
@ -100,8 +100,8 @@ struct platform_device s5pv310_device_pd[] = {
|
|||
.id = 3,
|
||||
.dev = {
|
||||
.platform_data = &(struct samsung_pd_info) {
|
||||
.enable = s5pv310_pd_enable,
|
||||
.disable = s5pv310_pd_disable,
|
||||
.enable = exynos4_pd_enable,
|
||||
.disable = exynos4_pd_disable,
|
||||
.base = S5P_PMU_LCD1_CONF,
|
||||
},
|
||||
},
|
||||
|
@ -110,8 +110,8 @@ struct platform_device s5pv310_device_pd[] = {
|
|||
.id = 4,
|
||||
.dev = {
|
||||
.platform_data = &(struct samsung_pd_info) {
|
||||
.enable = s5pv310_pd_enable,
|
||||
.disable = s5pv310_pd_disable,
|
||||
.enable = exynos4_pd_enable,
|
||||
.disable = exynos4_pd_disable,
|
||||
.base = S5P_PMU_TV_CONF,
|
||||
},
|
||||
},
|
||||
|
@ -120,8 +120,8 @@ struct platform_device s5pv310_device_pd[] = {
|
|||
.id = 5,
|
||||
.dev = {
|
||||
.platform_data = &(struct samsung_pd_info) {
|
||||
.enable = s5pv310_pd_enable,
|
||||
.disable = s5pv310_pd_disable,
|
||||
.enable = exynos4_pd_enable,
|
||||
.disable = exynos4_pd_disable,
|
||||
.base = S5P_PMU_CAM_CONF,
|
||||
},
|
||||
},
|
||||
|
@ -130,8 +130,8 @@ struct platform_device s5pv310_device_pd[] = {
|
|||
.id = 6,
|
||||
.dev = {
|
||||
.platform_data = &(struct samsung_pd_info) {
|
||||
.enable = s5pv310_pd_enable,
|
||||
.disable = s5pv310_pd_disable,
|
||||
.enable = exynos4_pd_enable,
|
||||
.disable = exynos4_pd_disable,
|
||||
.base = S5P_PMU_GPS_CONF,
|
||||
},
|
||||
},
|
|
@ -1,8 +1,10 @@
|
|||
/* linux/arch/arm/mach-s5pv310/dev-sysmmu.c
|
||||
/* linux/arch/arm/mach-exynos4/dev-sysmmu.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - System MMU support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
|
@ -13,11 +15,33 @@
|
|||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
#include <mach/sysmmu.h>
|
||||
#include <plat/s5p-clock.h>
|
||||
|
||||
static struct resource s5pv310_sysmmu_resource[] = {
|
||||
/* These names must be equal to the clock names in mach-exynos4/clock.c */
|
||||
const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM] = {
|
||||
"SYSMMU_MDMA" ,
|
||||
"SYSMMU_SSS" ,
|
||||
"SYSMMU_FIMC0" ,
|
||||
"SYSMMU_FIMC1" ,
|
||||
"SYSMMU_FIMC2" ,
|
||||
"SYSMMU_FIMC3" ,
|
||||
"SYSMMU_JPEG" ,
|
||||
"SYSMMU_FIMD0" ,
|
||||
"SYSMMU_FIMD1" ,
|
||||
"SYSMMU_PCIe" ,
|
||||
"SYSMMU_G2D" ,
|
||||
"SYSMMU_ROTATOR",
|
||||
"SYSMMU_MDMA2" ,
|
||||
"SYSMMU_TV" ,
|
||||
"SYSMMU_MFC_L" ,
|
||||
"SYSMMU_MFC_R" ,
|
||||
};
|
||||
|
||||
static struct resource exynos4_sysmmu_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_SYSMMU_MDMA,
|
||||
.end = S5PV310_PA_SYSMMU_MDMA + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_MDMA,
|
||||
.end = EXYNOS4_PA_SYSMMU_MDMA + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -26,8 +50,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[2] = {
|
||||
.start = S5PV310_PA_SYSMMU_SSS,
|
||||
.end = S5PV310_PA_SYSMMU_SSS + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_SSS,
|
||||
.end = EXYNOS4_PA_SYSMMU_SSS + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[3] = {
|
||||
|
@ -36,8 +60,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[4] = {
|
||||
.start = S5PV310_PA_SYSMMU_FIMC0,
|
||||
.end = S5PV310_PA_SYSMMU_FIMC0 + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_FIMC0,
|
||||
.end = EXYNOS4_PA_SYSMMU_FIMC0 + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[5] = {
|
||||
|
@ -46,8 +70,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[6] = {
|
||||
.start = S5PV310_PA_SYSMMU_FIMC1,
|
||||
.end = S5PV310_PA_SYSMMU_FIMC1 + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_FIMC1,
|
||||
.end = EXYNOS4_PA_SYSMMU_FIMC1 + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[7] = {
|
||||
|
@ -56,8 +80,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[8] = {
|
||||
.start = S5PV310_PA_SYSMMU_FIMC2,
|
||||
.end = S5PV310_PA_SYSMMU_FIMC2 + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_FIMC2,
|
||||
.end = EXYNOS4_PA_SYSMMU_FIMC2 + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[9] = {
|
||||
|
@ -66,8 +90,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[10] = {
|
||||
.start = S5PV310_PA_SYSMMU_FIMC3,
|
||||
.end = S5PV310_PA_SYSMMU_FIMC3 + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_FIMC3,
|
||||
.end = EXYNOS4_PA_SYSMMU_FIMC3 + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[11] = {
|
||||
|
@ -76,8 +100,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[12] = {
|
||||
.start = S5PV310_PA_SYSMMU_JPEG,
|
||||
.end = S5PV310_PA_SYSMMU_JPEG + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_JPEG,
|
||||
.end = EXYNOS4_PA_SYSMMU_JPEG + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[13] = {
|
||||
|
@ -86,8 +110,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[14] = {
|
||||
.start = S5PV310_PA_SYSMMU_FIMD0,
|
||||
.end = S5PV310_PA_SYSMMU_FIMD0 + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_FIMD0,
|
||||
.end = EXYNOS4_PA_SYSMMU_FIMD0 + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[15] = {
|
||||
|
@ -96,8 +120,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[16] = {
|
||||
.start = S5PV310_PA_SYSMMU_FIMD1,
|
||||
.end = S5PV310_PA_SYSMMU_FIMD1 + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_FIMD1,
|
||||
.end = EXYNOS4_PA_SYSMMU_FIMD1 + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[17] = {
|
||||
|
@ -106,8 +130,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[18] = {
|
||||
.start = S5PV310_PA_SYSMMU_PCIe,
|
||||
.end = S5PV310_PA_SYSMMU_PCIe + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_PCIe,
|
||||
.end = EXYNOS4_PA_SYSMMU_PCIe + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[19] = {
|
||||
|
@ -116,8 +140,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[20] = {
|
||||
.start = S5PV310_PA_SYSMMU_G2D,
|
||||
.end = S5PV310_PA_SYSMMU_G2D + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_G2D,
|
||||
.end = EXYNOS4_PA_SYSMMU_G2D + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[21] = {
|
||||
|
@ -126,8 +150,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[22] = {
|
||||
.start = S5PV310_PA_SYSMMU_ROTATOR,
|
||||
.end = S5PV310_PA_SYSMMU_ROTATOR + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_ROTATOR,
|
||||
.end = EXYNOS4_PA_SYSMMU_ROTATOR + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[23] = {
|
||||
|
@ -136,8 +160,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[24] = {
|
||||
.start = S5PV310_PA_SYSMMU_MDMA2,
|
||||
.end = S5PV310_PA_SYSMMU_MDMA2 + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_MDMA2,
|
||||
.end = EXYNOS4_PA_SYSMMU_MDMA2 + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[25] = {
|
||||
|
@ -146,8 +170,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[26] = {
|
||||
.start = S5PV310_PA_SYSMMU_TV,
|
||||
.end = S5PV310_PA_SYSMMU_TV + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_TV,
|
||||
.end = EXYNOS4_PA_SYSMMU_TV + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[27] = {
|
||||
|
@ -156,8 +180,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[28] = {
|
||||
.start = S5PV310_PA_SYSMMU_MFC_L,
|
||||
.end = S5PV310_PA_SYSMMU_MFC_L + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_MFC_L,
|
||||
.end = EXYNOS4_PA_SYSMMU_MFC_L + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[29] = {
|
||||
|
@ -166,8 +190,8 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
.flags = IORESOURCE_IRQ,
|
||||
},
|
||||
[30] = {
|
||||
.start = S5PV310_PA_SYSMMU_MFC_R,
|
||||
.end = S5PV310_PA_SYSMMU_MFC_R + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SYSMMU_MFC_R,
|
||||
.end = EXYNOS4_PA_SYSMMU_MFC_R + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[31] = {
|
||||
|
@ -177,11 +201,32 @@ static struct resource s5pv310_sysmmu_resource[] = {
|
|||
},
|
||||
};
|
||||
|
||||
struct platform_device s5pv310_device_sysmmu = {
|
||||
struct platform_device exynos4_device_sysmmu = {
|
||||
.name = "s5p-sysmmu",
|
||||
.id = 32,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_sysmmu_resource),
|
||||
.resource = s5pv310_sysmmu_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_sysmmu_resource),
|
||||
.resource = exynos4_sysmmu_resource,
|
||||
};
|
||||
EXPORT_SYMBOL(exynos4_device_sysmmu);
|
||||
|
||||
EXPORT_SYMBOL(s5pv310_device_sysmmu);
|
||||
static struct clk *sysmmu_clk[S5P_SYSMMU_TOTAL_IPNUM];
|
||||
void sysmmu_clk_init(struct device *dev, sysmmu_ips ips)
|
||||
{
|
||||
sysmmu_clk[ips] = clk_get(dev, sysmmu_ips_name[ips]);
|
||||
if (IS_ERR(sysmmu_clk[ips]))
|
||||
sysmmu_clk[ips] = NULL;
|
||||
else
|
||||
clk_put(sysmmu_clk[ips]);
|
||||
}
|
||||
|
||||
void sysmmu_clk_enable(sysmmu_ips ips)
|
||||
{
|
||||
if (sysmmu_clk[ips])
|
||||
clk_enable(sysmmu_clk[ips]);
|
||||
}
|
||||
|
||||
void sysmmu_clk_disable(sysmmu_ips ips)
|
||||
{
|
||||
if (sysmmu_clk[ips])
|
||||
clk_disable(sysmmu_clk[ips]);
|
||||
}
|
|
@ -1,4 +1,8 @@
|
|||
/*
|
||||
/* linux/arch/arm/mach-exynos4/dma.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
|
||||
* Jaswinder Singh <jassi.brar@samsung.com>
|
||||
*
|
||||
|
@ -30,10 +34,10 @@
|
|||
|
||||
static u64 dma_dmamask = DMA_BIT_MASK(32);
|
||||
|
||||
static struct resource s5pv310_pdma0_resource[] = {
|
||||
static struct resource exynos4_pdma0_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_PDMA0,
|
||||
.end = S5PV310_PA_PDMA0 + SZ_4K,
|
||||
.start = EXYNOS4_PA_PDMA0,
|
||||
.end = EXYNOS4_PA_PDMA0 + SZ_4K,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -43,7 +47,7 @@ static struct resource s5pv310_pdma0_resource[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
|
||||
static struct s3c_pl330_platdata exynos4_pdma0_pdata = {
|
||||
.peri = {
|
||||
[0] = DMACH_PCM0_RX,
|
||||
[1] = DMACH_PCM0_TX,
|
||||
|
@ -80,22 +84,22 @@ static struct s3c_pl330_platdata s5pv310_pdma0_pdata = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct platform_device s5pv310_device_pdma0 = {
|
||||
static struct platform_device exynos4_device_pdma0 = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 0,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_pdma0_resource),
|
||||
.resource = s5pv310_pdma0_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pdma0_resource),
|
||||
.resource = exynos4_pdma0_resource,
|
||||
.dev = {
|
||||
.dma_mask = &dma_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &s5pv310_pdma0_pdata,
|
||||
.platform_data = &exynos4_pdma0_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct resource s5pv310_pdma1_resource[] = {
|
||||
static struct resource exynos4_pdma1_resource[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_PDMA1,
|
||||
.end = S5PV310_PA_PDMA1 + SZ_4K,
|
||||
.start = EXYNOS4_PA_PDMA1,
|
||||
.end = EXYNOS4_PA_PDMA1 + SZ_4K,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -105,7 +109,7 @@ static struct resource s5pv310_pdma1_resource[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
|
||||
static struct s3c_pl330_platdata exynos4_pdma1_pdata = {
|
||||
.peri = {
|
||||
[0] = DMACH_PCM0_RX,
|
||||
[1] = DMACH_PCM0_TX,
|
||||
|
@ -142,27 +146,27 @@ static struct s3c_pl330_platdata s5pv310_pdma1_pdata = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct platform_device s5pv310_device_pdma1 = {
|
||||
static struct platform_device exynos4_device_pdma1 = {
|
||||
.name = "s3c-pl330",
|
||||
.id = 1,
|
||||
.num_resources = ARRAY_SIZE(s5pv310_pdma1_resource),
|
||||
.resource = s5pv310_pdma1_resource,
|
||||
.num_resources = ARRAY_SIZE(exynos4_pdma1_resource),
|
||||
.resource = exynos4_pdma1_resource,
|
||||
.dev = {
|
||||
.dma_mask = &dma_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
.platform_data = &s5pv310_pdma1_pdata,
|
||||
.platform_data = &exynos4_pdma1_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *s5pv310_dmacs[] __initdata = {
|
||||
&s5pv310_device_pdma0,
|
||||
&s5pv310_device_pdma1,
|
||||
static struct platform_device *exynos4_dmacs[] __initdata = {
|
||||
&exynos4_device_pdma0,
|
||||
&exynos4_device_pdma1,
|
||||
};
|
||||
|
||||
static int __init s5pv310_dma_init(void)
|
||||
static int __init exynos4_dma_init(void)
|
||||
{
|
||||
platform_add_devices(s5pv310_dmacs, ARRAY_SIZE(s5pv310_dmacs));
|
||||
platform_add_devices(exynos4_dmacs, ARRAY_SIZE(exynos4_dmacs));
|
||||
|
||||
return 0;
|
||||
}
|
||||
arch_initcall(s5pv310_dma_init);
|
||||
arch_initcall(exynos4_dma_init);
|
365
arch/arm/mach-exynos4/gpiolib.c
Normal file
365
arch/arm/mach-exynos4/gpiolib.c
Normal file
|
@ -0,0 +1,365 @@
|
|||
/* linux/arch/arm/mach-exynos4/gpiolib.c
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - GPIOlib support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/gpio-core.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/gpio-cfg-helpers.h>
|
||||
|
||||
static struct s3c_gpio_cfg gpio_cfg = {
|
||||
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
static struct s3c_gpio_cfg gpio_cfg_noint = {
|
||||
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
/*
|
||||
* Following are the gpio banks in v310.
|
||||
*
|
||||
* The 'config' member when left to NULL, is initialized to the default
|
||||
* structure gpio_cfg in the init function below.
|
||||
*
|
||||
* The 'base' member is also initialized in the init function below.
|
||||
* Note: The initialization of 'base' member of s3c_gpio_chip structure
|
||||
* uses the above macro and depends on the banks being listed in order here.
|
||||
*/
|
||||
static struct s3c_gpio_chip exynos4_gpio_part1_4bit[] = {
|
||||
{
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPA0(0),
|
||||
.ngpio = EXYNOS4_GPIO_A0_NR,
|
||||
.label = "GPA0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPA1(0),
|
||||
.ngpio = EXYNOS4_GPIO_A1_NR,
|
||||
.label = "GPA1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPB(0),
|
||||
.ngpio = EXYNOS4_GPIO_B_NR,
|
||||
.label = "GPB",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPC0(0),
|
||||
.ngpio = EXYNOS4_GPIO_C0_NR,
|
||||
.label = "GPC0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPC1(0),
|
||||
.ngpio = EXYNOS4_GPIO_C1_NR,
|
||||
.label = "GPC1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPD0(0),
|
||||
.ngpio = EXYNOS4_GPIO_D0_NR,
|
||||
.label = "GPD0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPD1(0),
|
||||
.ngpio = EXYNOS4_GPIO_D1_NR,
|
||||
.label = "GPD1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPE0(0),
|
||||
.ngpio = EXYNOS4_GPIO_E0_NR,
|
||||
.label = "GPE0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPE1(0),
|
||||
.ngpio = EXYNOS4_GPIO_E1_NR,
|
||||
.label = "GPE1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPE2(0),
|
||||
.ngpio = EXYNOS4_GPIO_E2_NR,
|
||||
.label = "GPE2",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPE3(0),
|
||||
.ngpio = EXYNOS4_GPIO_E3_NR,
|
||||
.label = "GPE3",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPE4(0),
|
||||
.ngpio = EXYNOS4_GPIO_E4_NR,
|
||||
.label = "GPE4",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPF0(0),
|
||||
.ngpio = EXYNOS4_GPIO_F0_NR,
|
||||
.label = "GPF0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPF1(0),
|
||||
.ngpio = EXYNOS4_GPIO_F1_NR,
|
||||
.label = "GPF1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPF2(0),
|
||||
.ngpio = EXYNOS4_GPIO_F2_NR,
|
||||
.label = "GPF2",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPF3(0),
|
||||
.ngpio = EXYNOS4_GPIO_F3_NR,
|
||||
.label = "GPF3",
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_gpio_chip exynos4_gpio_part2_4bit[] = {
|
||||
{
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPJ0(0),
|
||||
.ngpio = EXYNOS4_GPIO_J0_NR,
|
||||
.label = "GPJ0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPJ1(0),
|
||||
.ngpio = EXYNOS4_GPIO_J1_NR,
|
||||
.label = "GPJ1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPK0(0),
|
||||
.ngpio = EXYNOS4_GPIO_K0_NR,
|
||||
.label = "GPK0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPK1(0),
|
||||
.ngpio = EXYNOS4_GPIO_K1_NR,
|
||||
.label = "GPK1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPK2(0),
|
||||
.ngpio = EXYNOS4_GPIO_K2_NR,
|
||||
.label = "GPK2",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPK3(0),
|
||||
.ngpio = EXYNOS4_GPIO_K3_NR,
|
||||
.label = "GPK3",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPL0(0),
|
||||
.ngpio = EXYNOS4_GPIO_L0_NR,
|
||||
.label = "GPL0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPL1(0),
|
||||
.ngpio = EXYNOS4_GPIO_L1_NR,
|
||||
.label = "GPL1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPL2(0),
|
||||
.ngpio = EXYNOS4_GPIO_L2_NR,
|
||||
.label = "GPL2",
|
||||
},
|
||||
}, {
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY0(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y0_NR,
|
||||
.label = "GPY0",
|
||||
},
|
||||
}, {
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY1(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y1_NR,
|
||||
.label = "GPY1",
|
||||
},
|
||||
}, {
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY2(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y2_NR,
|
||||
.label = "GPY2",
|
||||
},
|
||||
}, {
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY3(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y3_NR,
|
||||
.label = "GPY3",
|
||||
},
|
||||
}, {
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY4(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y4_NR,
|
||||
.label = "GPY4",
|
||||
},
|
||||
}, {
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY5(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y5_NR,
|
||||
.label = "GPY5",
|
||||
},
|
||||
}, {
|
||||
.config = &gpio_cfg_noint,
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPY6(0),
|
||||
.ngpio = EXYNOS4_GPIO_Y6_NR,
|
||||
.label = "GPY6",
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC00),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(0),
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPX0(0),
|
||||
.ngpio = EXYNOS4_GPIO_X0_NR,
|
||||
.label = "GPX0",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC20),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(8),
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPX1(0),
|
||||
.ngpio = EXYNOS4_GPIO_X1_NR,
|
||||
.label = "GPX1",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC40),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(16),
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPX2(0),
|
||||
.ngpio = EXYNOS4_GPIO_X2_NR,
|
||||
.label = "GPX2",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC60),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(24),
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPX3(0),
|
||||
.ngpio = EXYNOS4_GPIO_X3_NR,
|
||||
.label = "GPX3",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_gpio_chip exynos4_gpio_part3_4bit[] = {
|
||||
{
|
||||
.chip = {
|
||||
.base = EXYNOS4_GPZ(0),
|
||||
.ngpio = EXYNOS4_GPIO_Z_NR,
|
||||
.label = "GPZ",
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static __init int exynos4_gpiolib_init(void)
|
||||
{
|
||||
struct s3c_gpio_chip *chip;
|
||||
int i;
|
||||
int group = 0;
|
||||
int nr_chips;
|
||||
|
||||
/* GPIO part 1 */
|
||||
|
||||
chip = exynos4_gpio_part1_4bit;
|
||||
nr_chips = ARRAY_SIZE(exynos4_gpio_part1_4bit);
|
||||
|
||||
for (i = 0; i < nr_chips; i++, chip++) {
|
||||
if (chip->config == NULL) {
|
||||
chip->config = &gpio_cfg;
|
||||
/* Assign the GPIO interrupt group */
|
||||
chip->group = group++;
|
||||
}
|
||||
if (chip->base == NULL)
|
||||
chip->base = S5P_VA_GPIO1 + (i) * 0x20;
|
||||
}
|
||||
|
||||
samsung_gpiolib_add_4bit_chips(exynos4_gpio_part1_4bit, nr_chips);
|
||||
|
||||
/* GPIO part 2 */
|
||||
|
||||
chip = exynos4_gpio_part2_4bit;
|
||||
nr_chips = ARRAY_SIZE(exynos4_gpio_part2_4bit);
|
||||
|
||||
for (i = 0; i < nr_chips; i++, chip++) {
|
||||
if (chip->config == NULL) {
|
||||
chip->config = &gpio_cfg;
|
||||
/* Assign the GPIO interrupt group */
|
||||
chip->group = group++;
|
||||
}
|
||||
if (chip->base == NULL)
|
||||
chip->base = S5P_VA_GPIO2 + (i) * 0x20;
|
||||
}
|
||||
|
||||
samsung_gpiolib_add_4bit_chips(exynos4_gpio_part2_4bit, nr_chips);
|
||||
|
||||
/* GPIO part 3 */
|
||||
|
||||
chip = exynos4_gpio_part3_4bit;
|
||||
nr_chips = ARRAY_SIZE(exynos4_gpio_part3_4bit);
|
||||
|
||||
for (i = 0; i < nr_chips; i++, chip++) {
|
||||
if (chip->config == NULL) {
|
||||
chip->config = &gpio_cfg;
|
||||
/* Assign the GPIO interrupt group */
|
||||
chip->group = group++;
|
||||
}
|
||||
if (chip->base == NULL)
|
||||
chip->base = S5P_VA_GPIO3 + (i) * 0x20;
|
||||
}
|
||||
|
||||
samsung_gpiolib_add_4bit_chips(exynos4_gpio_part3_4bit, nr_chips);
|
||||
s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
|
||||
s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
|
||||
|
||||
return 0;
|
||||
}
|
||||
core_initcall(exynos4_gpiolib_init);
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s5pv310/headsmp.S
|
||||
* linux/arch/arm/mach-exynos4/headsmp.S
|
||||
*
|
||||
* Cloned from linux/arch/arm/mach-realview/headsmp.S
|
||||
*
|
||||
|
@ -16,11 +16,11 @@
|
|||
__INIT
|
||||
|
||||
/*
|
||||
* s5pv310 specific entry point for secondary CPUs. This provides
|
||||
* exynos4 specific entry point for secondary CPUs. This provides
|
||||
* a "holding pen" into which all secondary cores are held until we're
|
||||
* ready for them to initialise.
|
||||
*/
|
||||
ENTRY(s5pv310_secondary_startup)
|
||||
ENTRY(exynos4_secondary_startup)
|
||||
mrc p15, 0, r0, c0, c0, 5
|
||||
and r0, r0, #15
|
||||
adr r4, 1f
|
|
@ -1,4 +1,4 @@
|
|||
/* linux arch/arm/mach-s5pv310/hotplug.c
|
||||
/* linux arch/arm/mach-exynos4/hotplug.c
|
||||
*
|
||||
* Cloned from linux/arch/arm/mach-realview/hotplug.c
|
||||
*
|
||||
|
@ -30,13 +30,13 @@ static inline void cpu_enter_lowpower(void)
|
|||
* Turn off coherency
|
||||
*/
|
||||
" mrc p15, 0, %0, c1, c0, 1\n"
|
||||
" bic %0, %0, #0x20\n"
|
||||
" bic %0, %0, %3\n"
|
||||
" mcr p15, 0, %0, c1, c0, 1\n"
|
||||
" mrc p15, 0, %0, c1, c0, 0\n"
|
||||
" bic %0, %0, %2\n"
|
||||
" mcr p15, 0, %0, c1, c0, 0\n"
|
||||
: "=&r" (v)
|
||||
: "r" (0), "Ir" (CR_C)
|
||||
: "r" (0), "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
}
|
||||
|
||||
|
@ -49,10 +49,10 @@ static inline void cpu_leave_lowpower(void)
|
|||
" orr %0, %0, %1\n"
|
||||
" mcr p15, 0, %0, c1, c0, 0\n"
|
||||
" mrc p15, 0, %0, c1, c0, 1\n"
|
||||
" orr %0, %0, #0x20\n"
|
||||
" orr %0, %0, %2\n"
|
||||
" mcr p15, 0, %0, c1, c0, 1\n"
|
||||
: "=&r" (v)
|
||||
: "Ir" (CR_C)
|
||||
: "Ir" (CR_C), "Ir" (0x40)
|
||||
: "cc");
|
||||
}
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/debug-macro.S
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/debug-macro.S
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Based on arch/arm/mach-s3c6400/include/mach/debug-macro.S
|
||||
*
|
|
@ -1,8 +1,8 @@
|
|||
/* arch/arm/mach-s5pv310/include/mach/entry-macro.S
|
||||
/* arch/arm/mach-exynos4/include/mach/entry-macro.S
|
||||
*
|
||||
* Cloned from arch/arm/mach-realview/include/mach/entry-macro.S
|
||||
*
|
||||
* Low-level IRQ helper macros for S5PV310 platforms
|
||||
* Low-level IRQ helper macros for EXYNOS4 platforms
|
||||
*
|
||||
* This file is licensed under the terms of the GNU General Public
|
||||
* License version 2. This program is licensed "as is" without any
|
156
arch/arm/mach-exynos4/include/mach/gpio.h
Normal file
156
arch/arm/mach-exynos4/include/mach/gpio.h
Normal file
|
@ -0,0 +1,156 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/gpio.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - GPIO lib support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_GPIO_H
|
||||
#define __ASM_ARCH_GPIO_H __FILE__
|
||||
|
||||
#define gpio_get_value __gpio_get_value
|
||||
#define gpio_set_value __gpio_set_value
|
||||
#define gpio_cansleep __gpio_cansleep
|
||||
#define gpio_to_irq __gpio_to_irq
|
||||
|
||||
/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
|
||||
|
||||
/* GPIO bank sizes */
|
||||
#define EXYNOS4_GPIO_A0_NR (8)
|
||||
#define EXYNOS4_GPIO_A1_NR (6)
|
||||
#define EXYNOS4_GPIO_B_NR (8)
|
||||
#define EXYNOS4_GPIO_C0_NR (5)
|
||||
#define EXYNOS4_GPIO_C1_NR (5)
|
||||
#define EXYNOS4_GPIO_D0_NR (4)
|
||||
#define EXYNOS4_GPIO_D1_NR (4)
|
||||
#define EXYNOS4_GPIO_E0_NR (5)
|
||||
#define EXYNOS4_GPIO_E1_NR (8)
|
||||
#define EXYNOS4_GPIO_E2_NR (6)
|
||||
#define EXYNOS4_GPIO_E3_NR (8)
|
||||
#define EXYNOS4_GPIO_E4_NR (8)
|
||||
#define EXYNOS4_GPIO_F0_NR (8)
|
||||
#define EXYNOS4_GPIO_F1_NR (8)
|
||||
#define EXYNOS4_GPIO_F2_NR (8)
|
||||
#define EXYNOS4_GPIO_F3_NR (6)
|
||||
#define EXYNOS4_GPIO_J0_NR (8)
|
||||
#define EXYNOS4_GPIO_J1_NR (5)
|
||||
#define EXYNOS4_GPIO_K0_NR (7)
|
||||
#define EXYNOS4_GPIO_K1_NR (7)
|
||||
#define EXYNOS4_GPIO_K2_NR (7)
|
||||
#define EXYNOS4_GPIO_K3_NR (7)
|
||||
#define EXYNOS4_GPIO_L0_NR (8)
|
||||
#define EXYNOS4_GPIO_L1_NR (3)
|
||||
#define EXYNOS4_GPIO_L2_NR (8)
|
||||
#define EXYNOS4_GPIO_X0_NR (8)
|
||||
#define EXYNOS4_GPIO_X1_NR (8)
|
||||
#define EXYNOS4_GPIO_X2_NR (8)
|
||||
#define EXYNOS4_GPIO_X3_NR (8)
|
||||
#define EXYNOS4_GPIO_Y0_NR (6)
|
||||
#define EXYNOS4_GPIO_Y1_NR (4)
|
||||
#define EXYNOS4_GPIO_Y2_NR (6)
|
||||
#define EXYNOS4_GPIO_Y3_NR (8)
|
||||
#define EXYNOS4_GPIO_Y4_NR (8)
|
||||
#define EXYNOS4_GPIO_Y5_NR (8)
|
||||
#define EXYNOS4_GPIO_Y6_NR (8)
|
||||
#define EXYNOS4_GPIO_Z_NR (7)
|
||||
|
||||
/* GPIO bank numbers */
|
||||
|
||||
#define EXYNOS4_GPIO_NEXT(__gpio) \
|
||||
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
|
||||
|
||||
enum s5p_gpio_number {
|
||||
EXYNOS4_GPIO_A0_START = 0,
|
||||
EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0),
|
||||
EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1),
|
||||
EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B),
|
||||
EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0),
|
||||
EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1),
|
||||
EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0),
|
||||
EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1),
|
||||
EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0),
|
||||
EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1),
|
||||
EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2),
|
||||
EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3),
|
||||
EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4),
|
||||
EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0),
|
||||
EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1),
|
||||
EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2),
|
||||
EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3),
|
||||
EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0),
|
||||
EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1),
|
||||
EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0),
|
||||
EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1),
|
||||
EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2),
|
||||
EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3),
|
||||
EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0),
|
||||
EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1),
|
||||
EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2),
|
||||
EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0),
|
||||
EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1),
|
||||
EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2),
|
||||
EXYNOS4_GPIO_Y0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3),
|
||||
EXYNOS4_GPIO_Y1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0),
|
||||
EXYNOS4_GPIO_Y2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1),
|
||||
EXYNOS4_GPIO_Y3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2),
|
||||
EXYNOS4_GPIO_Y4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3),
|
||||
EXYNOS4_GPIO_Y5_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4),
|
||||
EXYNOS4_GPIO_Y6_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5),
|
||||
EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6),
|
||||
};
|
||||
|
||||
/* EXYNOS4 GPIO number definitions */
|
||||
#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
|
||||
#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
|
||||
#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
|
||||
#define EXYNOS4_GPC0(_nr) (EXYNOS4_GPIO_C0_START + (_nr))
|
||||
#define EXYNOS4_GPC1(_nr) (EXYNOS4_GPIO_C1_START + (_nr))
|
||||
#define EXYNOS4_GPD0(_nr) (EXYNOS4_GPIO_D0_START + (_nr))
|
||||
#define EXYNOS4_GPD1(_nr) (EXYNOS4_GPIO_D1_START + (_nr))
|
||||
#define EXYNOS4_GPE0(_nr) (EXYNOS4_GPIO_E0_START + (_nr))
|
||||
#define EXYNOS4_GPE1(_nr) (EXYNOS4_GPIO_E1_START + (_nr))
|
||||
#define EXYNOS4_GPE2(_nr) (EXYNOS4_GPIO_E2_START + (_nr))
|
||||
#define EXYNOS4_GPE3(_nr) (EXYNOS4_GPIO_E3_START + (_nr))
|
||||
#define EXYNOS4_GPE4(_nr) (EXYNOS4_GPIO_E4_START + (_nr))
|
||||
#define EXYNOS4_GPF0(_nr) (EXYNOS4_GPIO_F0_START + (_nr))
|
||||
#define EXYNOS4_GPF1(_nr) (EXYNOS4_GPIO_F1_START + (_nr))
|
||||
#define EXYNOS4_GPF2(_nr) (EXYNOS4_GPIO_F2_START + (_nr))
|
||||
#define EXYNOS4_GPF3(_nr) (EXYNOS4_GPIO_F3_START + (_nr))
|
||||
#define EXYNOS4_GPJ0(_nr) (EXYNOS4_GPIO_J0_START + (_nr))
|
||||
#define EXYNOS4_GPJ1(_nr) (EXYNOS4_GPIO_J1_START + (_nr))
|
||||
#define EXYNOS4_GPK0(_nr) (EXYNOS4_GPIO_K0_START + (_nr))
|
||||
#define EXYNOS4_GPK1(_nr) (EXYNOS4_GPIO_K1_START + (_nr))
|
||||
#define EXYNOS4_GPK2(_nr) (EXYNOS4_GPIO_K2_START + (_nr))
|
||||
#define EXYNOS4_GPK3(_nr) (EXYNOS4_GPIO_K3_START + (_nr))
|
||||
#define EXYNOS4_GPL0(_nr) (EXYNOS4_GPIO_L0_START + (_nr))
|
||||
#define EXYNOS4_GPL1(_nr) (EXYNOS4_GPIO_L1_START + (_nr))
|
||||
#define EXYNOS4_GPL2(_nr) (EXYNOS4_GPIO_L2_START + (_nr))
|
||||
#define EXYNOS4_GPX0(_nr) (EXYNOS4_GPIO_X0_START + (_nr))
|
||||
#define EXYNOS4_GPX1(_nr) (EXYNOS4_GPIO_X1_START + (_nr))
|
||||
#define EXYNOS4_GPX2(_nr) (EXYNOS4_GPIO_X2_START + (_nr))
|
||||
#define EXYNOS4_GPX3(_nr) (EXYNOS4_GPIO_X3_START + (_nr))
|
||||
#define EXYNOS4_GPY0(_nr) (EXYNOS4_GPIO_Y0_START + (_nr))
|
||||
#define EXYNOS4_GPY1(_nr) (EXYNOS4_GPIO_Y1_START + (_nr))
|
||||
#define EXYNOS4_GPY2(_nr) (EXYNOS4_GPIO_Y2_START + (_nr))
|
||||
#define EXYNOS4_GPY3(_nr) (EXYNOS4_GPIO_Y3_START + (_nr))
|
||||
#define EXYNOS4_GPY4(_nr) (EXYNOS4_GPIO_Y4_START + (_nr))
|
||||
#define EXYNOS4_GPY5(_nr) (EXYNOS4_GPIO_Y5_START + (_nr))
|
||||
#define EXYNOS4_GPY6(_nr) (EXYNOS4_GPIO_Y6_START + (_nr))
|
||||
#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
|
||||
|
||||
/* the end of the EXYNOS4 specific gpios */
|
||||
#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
|
||||
#define S3C_GPIO_END EXYNOS4_GPIO_END
|
||||
|
||||
/* define the number of gpios we need to the one after the GPZ() range */
|
||||
#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \
|
||||
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* __ASM_ARCH_GPIO_H */
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/hardware.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/hardware.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - Hardware support
|
||||
* EXYNOS4 - Hardware support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
|
@ -1,13 +1,13 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/io.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/io.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright 2008-2010 Ben Dooks <ben-linux@fluff.org>
|
||||
*
|
||||
* Based on arch/arm/mach-s5p6442/include/mach/io.h
|
||||
*
|
||||
* Default IO routines for S5PV310
|
||||
* Default IO routines for EXYNOS4
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/irqs.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/irqs.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - IRQ definitions
|
||||
* EXYNOS4 - IRQ definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -85,6 +85,9 @@
|
|||
#define IRQ_RTC_ALARM COMBINER_IRQ(23, 0)
|
||||
#define IRQ_RTC_TIC COMBINER_IRQ(23, 1)
|
||||
|
||||
#define IRQ_GPIO_XB COMBINER_IRQ(24, 0)
|
||||
#define IRQ_GPIO_XA COMBINER_IRQ(24, 1)
|
||||
|
||||
#define IRQ_UART0 COMBINER_IRQ(26, 0)
|
||||
#define IRQ_UART1 COMBINER_IRQ(26, 1)
|
||||
#define IRQ_UART2 COMBINER_IRQ(26, 2)
|
||||
|
@ -108,6 +111,11 @@
|
|||
#define IRQ_MIPI_CSIS0 COMBINER_IRQ(30, 0)
|
||||
#define IRQ_MIPI_CSIS1 COMBINER_IRQ(30, 1)
|
||||
|
||||
#define IRQ_FIMC0 COMBINER_IRQ(32, 0)
|
||||
#define IRQ_FIMC1 COMBINER_IRQ(32, 1)
|
||||
#define IRQ_FIMC2 COMBINER_IRQ(33, 0)
|
||||
#define IRQ_FIMC3 COMBINER_IRQ(33, 1)
|
||||
|
||||
#define IRQ_ONENAND_AUDI COMBINER_IRQ(34, 0)
|
||||
|
||||
#define IRQ_MCT_L1 COMBINER_IRQ(35, 3)
|
||||
|
@ -131,6 +139,7 @@
|
|||
#define IRQ_MCT_L0 COMBINER_IRQ(51, 0)
|
||||
|
||||
#define IRQ_WDT COMBINER_IRQ(53, 0)
|
||||
#define IRQ_MCT_G0 COMBINER_IRQ(53, 4)
|
||||
|
||||
#define MAX_COMBINER_NR 54
|
||||
|
||||
|
@ -139,8 +148,13 @@
|
|||
#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE + 0)
|
||||
#define S5P_EINT_BASE2 (S5P_IRQ_EINT_BASE + 16)
|
||||
|
||||
/* Set the default NR_IRQS */
|
||||
/* optional GPIO interrupts */
|
||||
#define S5P_GPIOINT_BASE (S5P_IRQ_EINT_BASE + 32)
|
||||
#define IRQ_GPIO1_NR_GROUPS 16
|
||||
#define IRQ_GPIO2_NR_GROUPS 9
|
||||
#define IRQ_GPIO_END (S5P_GPIOINT_BASE + S5P_GPIOINT_COUNT)
|
||||
|
||||
#define NR_IRQS (S5P_IRQ_EINT_BASE + 32)
|
||||
/* Set the default NR_IRQS */
|
||||
#define NR_IRQS (IRQ_GPIO_END)
|
||||
|
||||
#endif /* __ASM_ARCH_IRQS_H */
|
162
arch/arm/mach-exynos4/include/mach/map.h
Normal file
162
arch/arm/mach-exynos4/include/mach/map.h
Normal file
|
@ -0,0 +1,162 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/map.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* EXYNOS4 - Memory map definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MAP_H
|
||||
#define __ASM_ARCH_MAP_H __FILE__
|
||||
|
||||
#include <plat/map-base.h>
|
||||
|
||||
/*
|
||||
* EXYNOS4 UART offset is 0x10000 but the older S5P SoCs are 0x400.
|
||||
* So need to define it, and here is to avoid redefinition warning.
|
||||
*/
|
||||
#define S3C_UART_OFFSET (0x10000)
|
||||
|
||||
#include <plat/map-s5p.h>
|
||||
|
||||
#define EXYNOS4_PA_SYSRAM 0x02020000
|
||||
|
||||
#define EXYNOS4_PA_FIMC0 0x11800000
|
||||
#define EXYNOS4_PA_FIMC1 0x11810000
|
||||
#define EXYNOS4_PA_FIMC2 0x11820000
|
||||
#define EXYNOS4_PA_FIMC3 0x11830000
|
||||
|
||||
#define EXYNOS4_PA_I2S0 0x03830000
|
||||
#define EXYNOS4_PA_I2S1 0xE3100000
|
||||
#define EXYNOS4_PA_I2S2 0xE2A00000
|
||||
|
||||
#define EXYNOS4_PA_PCM0 0x03840000
|
||||
#define EXYNOS4_PA_PCM1 0x13980000
|
||||
#define EXYNOS4_PA_PCM2 0x13990000
|
||||
|
||||
#define EXYNOS4_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
|
||||
|
||||
#define EXYNOS4_PA_ONENAND 0x0C000000
|
||||
#define EXYNOS4_PA_ONENAND_DMA 0x0C600000
|
||||
|
||||
#define EXYNOS4_PA_CHIPID 0x10000000
|
||||
|
||||
#define EXYNOS4_PA_SYSCON 0x10010000
|
||||
#define EXYNOS4_PA_PMU 0x10020000
|
||||
#define EXYNOS4_PA_CMU 0x10030000
|
||||
|
||||
#define EXYNOS4_PA_SYSTIMER 0x10050000
|
||||
#define EXYNOS4_PA_WATCHDOG 0x10060000
|
||||
#define EXYNOS4_PA_RTC 0x10070000
|
||||
|
||||
#define EXYNOS4_PA_KEYPAD 0x100A0000
|
||||
|
||||
#define EXYNOS4_PA_DMC0 0x10400000
|
||||
|
||||
#define EXYNOS4_PA_COMBINER 0x10448000
|
||||
|
||||
#define EXYNOS4_PA_COREPERI 0x10500000
|
||||
#define EXYNOS4_PA_GIC_CPU 0x10500100
|
||||
#define EXYNOS4_PA_TWD 0x10500600
|
||||
#define EXYNOS4_PA_GIC_DIST 0x10501000
|
||||
#define EXYNOS4_PA_L2CC 0x10502000
|
||||
|
||||
#define EXYNOS4_PA_MDMA 0x10810000
|
||||
#define EXYNOS4_PA_PDMA0 0x12680000
|
||||
#define EXYNOS4_PA_PDMA1 0x12690000
|
||||
|
||||
#define EXYNOS4_PA_SYSMMU_MDMA 0x10A40000
|
||||
#define EXYNOS4_PA_SYSMMU_SSS 0x10A50000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC0 0x11A20000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC1 0x11A30000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC2 0x11A40000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMC3 0x11A50000
|
||||
#define EXYNOS4_PA_SYSMMU_JPEG 0x11A60000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMD0 0x11E20000
|
||||
#define EXYNOS4_PA_SYSMMU_FIMD1 0x12220000
|
||||
#define EXYNOS4_PA_SYSMMU_PCIe 0x12620000
|
||||
#define EXYNOS4_PA_SYSMMU_G2D 0x12A20000
|
||||
#define EXYNOS4_PA_SYSMMU_ROTATOR 0x12A30000
|
||||
#define EXYNOS4_PA_SYSMMU_MDMA2 0x12A40000
|
||||
#define EXYNOS4_PA_SYSMMU_TV 0x12E20000
|
||||
#define EXYNOS4_PA_SYSMMU_MFC_L 0x13620000
|
||||
#define EXYNOS4_PA_SYSMMU_MFC_R 0x13630000
|
||||
|
||||
#define EXYNOS4_PA_GPIO1 0x11400000
|
||||
#define EXYNOS4_PA_GPIO2 0x11000000
|
||||
#define EXYNOS4_PA_GPIO3 0x03860000
|
||||
|
||||
#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
|
||||
#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
|
||||
|
||||
#define EXYNOS4_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
|
||||
|
||||
#define EXYNOS4_PA_SATA 0x12560000
|
||||
#define EXYNOS4_PA_SATAPHY 0x125D0000
|
||||
#define EXYNOS4_PA_SATAPHY_CTRL 0x126B0000
|
||||
|
||||
#define EXYNOS4_PA_SROMC 0x12570000
|
||||
|
||||
#define EXYNOS4_PA_UART 0x13800000
|
||||
|
||||
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
|
||||
|
||||
#define EXYNOS4_PA_AC97 0x139A0000
|
||||
|
||||
#define EXYNOS4_PA_SPDIF 0x139B0000
|
||||
|
||||
#define EXYNOS4_PA_TIMER 0x139D0000
|
||||
|
||||
#define EXYNOS4_PA_SDRAM 0x40000000
|
||||
|
||||
/* Compatibiltiy Defines */
|
||||
|
||||
#define S3C_PA_HSMMC0 EXYNOS4_PA_HSMMC(0)
|
||||
#define S3C_PA_HSMMC1 EXYNOS4_PA_HSMMC(1)
|
||||
#define S3C_PA_HSMMC2 EXYNOS4_PA_HSMMC(2)
|
||||
#define S3C_PA_HSMMC3 EXYNOS4_PA_HSMMC(3)
|
||||
#define S3C_PA_IIC EXYNOS4_PA_IIC(0)
|
||||
#define S3C_PA_IIC1 EXYNOS4_PA_IIC(1)
|
||||
#define S3C_PA_IIC2 EXYNOS4_PA_IIC(2)
|
||||
#define S3C_PA_IIC3 EXYNOS4_PA_IIC(3)
|
||||
#define S3C_PA_IIC4 EXYNOS4_PA_IIC(4)
|
||||
#define S3C_PA_IIC5 EXYNOS4_PA_IIC(5)
|
||||
#define S3C_PA_IIC6 EXYNOS4_PA_IIC(6)
|
||||
#define S3C_PA_IIC7 EXYNOS4_PA_IIC(7)
|
||||
#define S3C_PA_RTC EXYNOS4_PA_RTC
|
||||
#define S3C_PA_WDT EXYNOS4_PA_WATCHDOG
|
||||
|
||||
#define S5P_PA_CHIPID EXYNOS4_PA_CHIPID
|
||||
#define S5P_PA_FIMC0 EXYNOS4_PA_FIMC0
|
||||
#define S5P_PA_FIMC1 EXYNOS4_PA_FIMC1
|
||||
#define S5P_PA_FIMC2 EXYNOS4_PA_FIMC2
|
||||
#define S5P_PA_FIMC3 EXYNOS4_PA_FIMC3
|
||||
#define S5P_PA_MIPI_CSIS0 EXYNOS4_PA_MIPI_CSIS0
|
||||
#define S5P_PA_MIPI_CSIS1 EXYNOS4_PA_MIPI_CSIS1
|
||||
#define S5P_PA_ONENAND EXYNOS4_PA_ONENAND
|
||||
#define S5P_PA_ONENAND_DMA EXYNOS4_PA_ONENAND_DMA
|
||||
#define S5P_PA_SDRAM EXYNOS4_PA_SDRAM
|
||||
#define S5P_PA_SROMC EXYNOS4_PA_SROMC
|
||||
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
|
||||
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
|
||||
|
||||
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
|
||||
|
||||
/* UART */
|
||||
|
||||
#define S3C_PA_UART EXYNOS4_PA_UART
|
||||
|
||||
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
|
||||
#define S5P_PA_UART0 S5P_PA_UART(0)
|
||||
#define S5P_PA_UART1 S5P_PA_UART(1)
|
||||
#define S5P_PA_UART2 S5P_PA_UART(2)
|
||||
#define S5P_PA_UART3 S5P_PA_UART(3)
|
||||
#define S5P_PA_UART4 S5P_PA_UART(4)
|
||||
|
||||
#define S5P_SZ_UART SZ_256
|
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/memory.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/memory.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - Memory definitions
|
||||
* EXYNOS4 - Memory definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
49
arch/arm/mach-exynos4/include/mach/pm-core.h
Normal file
49
arch/arm/mach-exynos4/include/mach/pm-core.h
Normal file
|
@ -0,0 +1,49 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/pm-core.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Based on arch/arm/mach-s3c2410/include/mach/pm-core.h,
|
||||
* Copyright 2008 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
* http://armlinux.simtec.co.uk/
|
||||
*
|
||||
* EXYNOS4210 - PM core support for arch/arm/plat-s5p/pm.c
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
static inline void s3c_pm_debug_init_uart(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_prepare_irqs(void)
|
||||
{
|
||||
unsigned int tmp;
|
||||
tmp = __raw_readl(S5P_WAKEUP_MASK);
|
||||
tmp &= ~(1 << 31);
|
||||
__raw_writel(tmp, S5P_WAKEUP_MASK);
|
||||
|
||||
__raw_writel(s3c_irqwake_intmask, S5P_WAKEUP_MASK);
|
||||
__raw_writel(s3c_irqwake_eintmask, S5P_EINT_WAKEUP_MASK);
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_stop_clocks(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_show_resume_irqs(void)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
||||
|
||||
static inline void s3c_pm_arch_update_uart(void __iomem *regs,
|
||||
struct pm_uart_save *save)
|
||||
{
|
||||
/* nothing here yet */
|
||||
}
|
|
@ -1,7 +1,7 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/pwm-clock.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/pwm-clock.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright 2008 Openmoko, Inc.
|
||||
* Copyright 2008 Simtec Electronics
|
||||
|
@ -10,7 +10,7 @@
|
|||
*
|
||||
* Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
|
||||
*
|
||||
* S5PV310 - pwm clock and timer support
|
||||
* EXYNOS4 - pwm clock and timer support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/regs-clock.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/regs-clock.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - Clock register definitions
|
||||
* EXYNOS4 - Clock register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -17,13 +17,13 @@
|
|||
|
||||
#define S5P_CLKREG(x) (S5P_VA_CMU + (x))
|
||||
|
||||
#define S5P_INFORM0 S5P_CLKREG(0x800)
|
||||
|
||||
#define S5P_CLKDIV_LEFTBUS S5P_CLKREG(0x04500)
|
||||
#define S5P_CLKDIV_STAT_LEFTBUS S5P_CLKREG(0x04600)
|
||||
#define S5P_CLKGATE_IP_LEFTBUS S5P_CLKREG(0x04800)
|
||||
|
||||
#define S5P_CLKDIV_RIGHTBUS S5P_CLKREG(0x08500)
|
||||
#define S5P_CLKDIV_STAT_RIGHTBUS S5P_CLKREG(0x08600)
|
||||
#define S5P_CLKGATE_IP_RIGHTBUS S5P_CLKREG(0x08800)
|
||||
|
||||
#define S5P_EPLL_CON0 S5P_CLKREG(0x0C110)
|
||||
#define S5P_EPLL_CON1 S5P_CLKREG(0x0C114)
|
||||
|
@ -33,18 +33,24 @@
|
|||
#define S5P_CLKSRC_TOP0 S5P_CLKREG(0x0C210)
|
||||
#define S5P_CLKSRC_TOP1 S5P_CLKREG(0x0C214)
|
||||
#define S5P_CLKSRC_CAM S5P_CLKREG(0x0C220)
|
||||
#define S5P_CLKSRC_MFC S5P_CLKREG(0x0C228)
|
||||
#define S5P_CLKSRC_IMAGE S5P_CLKREG(0x0C230)
|
||||
#define S5P_CLKSRC_LCD0 S5P_CLKREG(0x0C234)
|
||||
#define S5P_CLKSRC_LCD1 S5P_CLKREG(0x0C238)
|
||||
#define S5P_CLKSRC_MAUDIO S5P_CLKREG(0x0C23C)
|
||||
#define S5P_CLKSRC_FSYS S5P_CLKREG(0x0C240)
|
||||
#define S5P_CLKSRC_PERIL0 S5P_CLKREG(0x0C250)
|
||||
#define S5P_CLKSRC_PERIL1 S5P_CLKREG(0x0C254)
|
||||
|
||||
#define S5P_CLKDIV_TOP S5P_CLKREG(0x0C510)
|
||||
#define S5P_CLKDIV_CAM S5P_CLKREG(0x0C520)
|
||||
#define S5P_CLKDIV_TV S5P_CLKREG(0x0C524)
|
||||
#define S5P_CLKDIV_MFC S5P_CLKREG(0x0C528)
|
||||
#define S5P_CLKDIV_G3D S5P_CLKREG(0x0C52C)
|
||||
#define S5P_CLKDIV_IMAGE S5P_CLKREG(0x0C530)
|
||||
#define S5P_CLKDIV_LCD0 S5P_CLKREG(0x0C534)
|
||||
#define S5P_CLKDIV_LCD1 S5P_CLKREG(0x0C538)
|
||||
#define S5P_CLKDIV_MAUDIO S5P_CLKREG(0x0C53C)
|
||||
#define S5P_CLKDIV_FSYS0 S5P_CLKREG(0x0C540)
|
||||
#define S5P_CLKDIV_FSYS1 S5P_CLKREG(0x0C544)
|
||||
#define S5P_CLKDIV_FSYS2 S5P_CLKREG(0x0C548)
|
||||
|
@ -58,25 +64,36 @@
|
|||
|
||||
#define S5P_CLKSRC_MASK_TOP S5P_CLKREG(0x0C310)
|
||||
#define S5P_CLKSRC_MASK_CAM S5P_CLKREG(0x0C320)
|
||||
#define S5P_CLKSRC_MASK_TV S5P_CLKREG(0x0C324)
|
||||
#define S5P_CLKSRC_MASK_LCD0 S5P_CLKREG(0x0C334)
|
||||
#define S5P_CLKSRC_MASK_LCD1 S5P_CLKREG(0x0C338)
|
||||
#define S5P_CLKSRC_MASK_MAUDIO S5P_CLKREG(0x0C33C)
|
||||
#define S5P_CLKSRC_MASK_FSYS S5P_CLKREG(0x0C340)
|
||||
#define S5P_CLKSRC_MASK_PERIL0 S5P_CLKREG(0x0C350)
|
||||
#define S5P_CLKSRC_MASK_PERIL1 S5P_CLKREG(0x0C354)
|
||||
|
||||
#define S5P_CLKDIV_STAT_TOP S5P_CLKREG(0x0C610)
|
||||
|
||||
#define S5P_CLKGATE_SCLKCAM S5P_CLKREG(0x0C820)
|
||||
#define S5P_CLKGATE_IP_CAM S5P_CLKREG(0x0C920)
|
||||
#define S5P_CLKGATE_IP_TV S5P_CLKREG(0x0C924)
|
||||
#define S5P_CLKGATE_IP_MFC S5P_CLKREG(0x0C928)
|
||||
#define S5P_CLKGATE_IP_G3D S5P_CLKREG(0x0C92C)
|
||||
#define S5P_CLKGATE_IP_IMAGE S5P_CLKREG(0x0C930)
|
||||
#define S5P_CLKGATE_IP_LCD0 S5P_CLKREG(0x0C934)
|
||||
#define S5P_CLKGATE_IP_LCD1 S5P_CLKREG(0x0C938)
|
||||
#define S5P_CLKGATE_IP_FSYS S5P_CLKREG(0x0C940)
|
||||
#define S5P_CLKGATE_IP_GPS S5P_CLKREG(0x0C94C)
|
||||
#define S5P_CLKGATE_IP_PERIL S5P_CLKREG(0x0C950)
|
||||
#define S5P_CLKGATE_IP_PERIR S5P_CLKREG(0x0C960)
|
||||
#define S5P_CLKGATE_BLOCK S5P_CLKREG(0x0C970)
|
||||
|
||||
#define S5P_CLKSRC_MASK_DMC S5P_CLKREG(0x10300)
|
||||
#define S5P_CLKSRC_DMC S5P_CLKREG(0x10200)
|
||||
#define S5P_CLKDIV_DMC0 S5P_CLKREG(0x10500)
|
||||
#define S5P_CLKDIV_DMC1 S5P_CLKREG(0x10504)
|
||||
#define S5P_CLKDIV_STAT_DMC0 S5P_CLKREG(0x10600)
|
||||
#define S5P_CLKGATE_IP_DMC S5P_CLKREG(0x10900)
|
||||
|
||||
#define S5P_APLL_LOCK S5P_CLKREG(0x14000)
|
||||
#define S5P_MPLL_LOCK S5P_CLKREG(0x14004)
|
||||
|
@ -94,21 +111,18 @@
|
|||
#define S5P_CLKDIV_STATCPU1 S5P_CLKREG(0x14604)
|
||||
|
||||
#define S5P_CLKGATE_SCLKCPU S5P_CLKREG(0x14800)
|
||||
#define S5P_CLKGATE_IP_CPU S5P_CLKREG(0x14900)
|
||||
|
||||
/* APLL_LOCK */
|
||||
#define S5P_APLL_LOCKTIME (0x1C20) /* 300us */
|
||||
|
||||
/* APLL_CON0 */
|
||||
#define S5P_APLLCON0_ENABLE_SHIFT (31)
|
||||
#define S5P_APLLCON0_LOCKED_SHIFT (29)
|
||||
#define S5P_APLL_VAL_1000 ((250 << 16) | (6 << 8) | 1)
|
||||
#define S5P_APLL_VAL_800 ((200 << 16) | (6 << 8) | 1)
|
||||
|
||||
/* CLK_SRC_CPU */
|
||||
#define S5P_CLKSRC_CPU_MUXCORE_SHIFT (16)
|
||||
#define S5P_CLKMUX_STATCPU_MUXCORE_MASK (0x7 << S5P_CLKSRC_CPU_MUXCORE_SHIFT)
|
||||
|
||||
/* CLKDIV_CPU0 */
|
||||
#define S5P_CLKDIV_CPU0_CORE_SHIFT (0)
|
||||
#define S5P_CLKDIV_CPU0_CORE_MASK (0x7 << S5P_CLKDIV_CPU0_CORE_SHIFT)
|
||||
#define S5P_CLKDIV_CPU0_COREM0_SHIFT (4)
|
||||
|
@ -124,7 +138,6 @@
|
|||
#define S5P_CLKDIV_CPU0_APLL_SHIFT (24)
|
||||
#define S5P_CLKDIV_CPU0_APLL_MASK (0x7 << S5P_CLKDIV_CPU0_APLL_SHIFT)
|
||||
|
||||
/* CLKDIV_DMC0 */
|
||||
#define S5P_CLKDIV_DMC0_ACP_SHIFT (0)
|
||||
#define S5P_CLKDIV_DMC0_ACP_MASK (0x7 << S5P_CLKDIV_DMC0_ACP_SHIFT)
|
||||
#define S5P_CLKDIV_DMC0_ACPPCLK_SHIFT (4)
|
||||
|
@ -142,7 +155,6 @@
|
|||
#define S5P_CLKDIV_DMC0_CORETI_SHIFT (28)
|
||||
#define S5P_CLKDIV_DMC0_CORETI_MASK (0x7 << S5P_CLKDIV_DMC0_CORETI_SHIFT)
|
||||
|
||||
/* CLKDIV_TOP */
|
||||
#define S5P_CLKDIV_TOP_ACLK200_SHIFT (0)
|
||||
#define S5P_CLKDIV_TOP_ACLK200_MASK (0x7 << S5P_CLKDIV_TOP_ACLK200_SHIFT)
|
||||
#define S5P_CLKDIV_TOP_ACLK100_SHIFT (4)
|
||||
|
@ -154,13 +166,14 @@
|
|||
#define S5P_CLKDIV_TOP_ONENAND_SHIFT (16)
|
||||
#define S5P_CLKDIV_TOP_ONENAND_MASK (0x7 << S5P_CLKDIV_TOP_ONENAND_SHIFT)
|
||||
|
||||
/* CLKDIV_LEFTBUS / CLKDIV_RIGHTBUS*/
|
||||
#define S5P_CLKDIV_BUS_GDLR_SHIFT (0)
|
||||
#define S5P_CLKDIV_BUS_GDLR_MASK (0x7 << S5P_CLKDIV_BUS_GDLR_SHIFT)
|
||||
#define S5P_CLKDIV_BUS_GPLR_SHIFT (4)
|
||||
#define S5P_CLKDIV_BUS_GPLR_MASK (0x7 << S5P_CLKDIV_BUS_GPLR_SHIFT)
|
||||
|
||||
/* Compatibility defines */
|
||||
/* Compatibility defines and inclusion */
|
||||
|
||||
#include <mach/regs-pmu.h>
|
||||
|
||||
#define S5P_EPLL_CON S5P_EPLL_CON0
|
||||
|
42
arch/arm/mach-exynos4/include/mach/regs-gpio.h
Normal file
42
arch/arm/mach-exynos4/include/mach/regs-gpio.h
Normal file
|
@ -0,0 +1,42 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/regs-gpio.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - GPIO (including EINT) register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_GPIO_H
|
||||
#define __ASM_ARCH_REGS_GPIO_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#define EXYNOS4_EINT40CON (S5P_VA_GPIO2 + 0xE00)
|
||||
#define S5P_EINT_CON(x) (EXYNOS4_EINT40CON + ((x) * 0x4))
|
||||
|
||||
#define EXYNOS4_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
|
||||
#define S5P_EINT_FLTCON(x) (EXYNOS4_EINT40FLTCON0 + ((x) * 0x4))
|
||||
|
||||
#define EXYNOS4_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
|
||||
#define S5P_EINT_MASK(x) (EXYNOS4_EINT40MASK + ((x) * 0x4))
|
||||
|
||||
#define EXYNOS4_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
|
||||
#define S5P_EINT_PEND(x) (EXYNOS4_EINT40PEND + ((x) * 0x4))
|
||||
|
||||
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
|
||||
|
||||
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
|
||||
|
||||
#define EINT_MODE S3C_GPIO_SFN(0xf)
|
||||
|
||||
#define EINT_GPIO_0(x) EXYNOS4_GPX0(x)
|
||||
#define EINT_GPIO_1(x) EXYNOS4_GPX1(x)
|
||||
#define EINT_GPIO_2(x) EXYNOS4_GPX2(x)
|
||||
#define EINT_GPIO_3(x) EXYNOS4_GPX3(x)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_GPIO_H */
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/regs-irq.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/regs-irq.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - IRQ register definitions
|
||||
* EXYNOS4 - IRQ register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
52
arch/arm/mach-exynos4/include/mach/regs-mct.h
Normal file
52
arch/arm/mach-exynos4/include/mach/regs-mct.h
Normal file
|
@ -0,0 +1,52 @@
|
|||
/* arch/arm/mach-exynos4/include/mach/regs-mct.h
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 MCT configutation
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_MCT_H
|
||||
#define __ASM_ARCH_REGS_MCT_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define EXYNOS4_MCTREG(x) (S5P_VA_SYSTIMER + (x))
|
||||
|
||||
#define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100)
|
||||
#define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104)
|
||||
#define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110)
|
||||
|
||||
#define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200)
|
||||
#define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204)
|
||||
#define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208)
|
||||
|
||||
#define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240)
|
||||
|
||||
#define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244)
|
||||
#define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248)
|
||||
#define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C)
|
||||
|
||||
#define EXYNOS4_MCT_L0_BASE EXYNOS4_MCTREG(0x300)
|
||||
#define EXYNOS4_MCT_L1_BASE EXYNOS4_MCTREG(0x400)
|
||||
|
||||
#define MCT_L_TCNTB_OFFSET (0x00)
|
||||
#define MCT_L_ICNTB_OFFSET (0x08)
|
||||
#define MCT_L_TCON_OFFSET (0x20)
|
||||
#define MCT_L_INT_CSTAT_OFFSET (0x30)
|
||||
#define MCT_L_INT_ENB_OFFSET (0x34)
|
||||
#define MCT_L_WSTAT_OFFSET (0x40)
|
||||
|
||||
#define MCT_G_TCON_START (1 << 8)
|
||||
#define MCT_G_TCON_COMP0_AUTO_INC (1 << 1)
|
||||
#define MCT_G_TCON_COMP0_ENABLE (1 << 0)
|
||||
|
||||
#define MCT_L_TCON_INTERVAL_MODE (1 << 2)
|
||||
#define MCT_L_TCON_INT_START (1 << 1)
|
||||
#define MCT_L_TCON_TIMER_START (1 << 0)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_MCT_H */
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/regs-mem.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/regs-mem.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - SROMC and DMC register definitions
|
||||
* EXYNOS4 - SROMC and DMC register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
162
arch/arm/mach-exynos4/include/mach/regs-pmu.h
Normal file
162
arch/arm/mach-exynos4/include/mach/regs-pmu.h
Normal file
|
@ -0,0 +1,162 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/regs-pmu.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 - Power management unit definition
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_PMU_H
|
||||
#define __ASM_ARCH_REGS_PMU_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
|
||||
|
||||
#define S5P_CENTRAL_SEQ_CONFIGURATION S5P_PMUREG(0x0200)
|
||||
|
||||
#define S5P_CENTRAL_LOWPWR_CFG (1 << 16)
|
||||
|
||||
#define S5P_CENTRAL_SEQ_OPTION S5P_PMUREG(0x0208)
|
||||
|
||||
#define S5P_USE_STANDBY_WFI0 (1 << 16)
|
||||
#define S5P_USE_STANDBY_WFI1 (1 << 17)
|
||||
#define S5P_USE_STANDBY_WFE0 (1 << 24)
|
||||
#define S5P_USE_STANDBY_WFE1 (1 << 25)
|
||||
#define S5P_USE_MASK ((0x3 << 16) | (0x3 << 24))
|
||||
|
||||
#define S5P_WAKEUP_STAT S5P_PMUREG(0x0600)
|
||||
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
|
||||
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
|
||||
|
||||
#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
|
||||
#define S5P_MIPI_DPHY_ENABLE (1 << 0)
|
||||
#define S5P_MIPI_DPHY_SRESETN (1 << 1)
|
||||
#define S5P_MIPI_DPHY_MRESETN (1 << 2)
|
||||
|
||||
#define S5P_PMU_SATA_PHY_CONTROL S5P_PMUREG(0x0720)
|
||||
#define S5P_INFORM0 S5P_PMUREG(0x0800)
|
||||
#define S5P_INFORM1 S5P_PMUREG(0x0804)
|
||||
#define S5P_INFORM2 S5P_PMUREG(0x0808)
|
||||
#define S5P_INFORM3 S5P_PMUREG(0x080C)
|
||||
#define S5P_INFORM4 S5P_PMUREG(0x0810)
|
||||
#define S5P_INFORM5 S5P_PMUREG(0x0814)
|
||||
#define S5P_INFORM6 S5P_PMUREG(0x0818)
|
||||
#define S5P_INFORM7 S5P_PMUREG(0x081C)
|
||||
|
||||
#define S5P_ARM_CORE0_LOWPWR S5P_PMUREG(0x1000)
|
||||
#define S5P_DIS_IRQ_CORE0 S5P_PMUREG(0x1004)
|
||||
#define S5P_DIS_IRQ_CENTRAL0 S5P_PMUREG(0x1008)
|
||||
#define S5P_ARM_CORE1_LOWPWR S5P_PMUREG(0x1010)
|
||||
#define S5P_DIS_IRQ_CORE1 S5P_PMUREG(0x1014)
|
||||
#define S5P_DIS_IRQ_CENTRAL1 S5P_PMUREG(0x1018)
|
||||
#define S5P_ARM_COMMON_LOWPWR S5P_PMUREG(0x1080)
|
||||
#define S5P_L2_0_LOWPWR S5P_PMUREG(0x10C0)
|
||||
#define S5P_L2_1_LOWPWR S5P_PMUREG(0x10C4)
|
||||
#define S5P_CMU_ACLKSTOP_LOWPWR S5P_PMUREG(0x1100)
|
||||
#define S5P_CMU_SCLKSTOP_LOWPWR S5P_PMUREG(0x1104)
|
||||
#define S5P_CMU_RESET_LOWPWR S5P_PMUREG(0x110C)
|
||||
#define S5P_APLL_SYSCLK_LOWPWR S5P_PMUREG(0x1120)
|
||||
#define S5P_MPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1124)
|
||||
#define S5P_VPLL_SYSCLK_LOWPWR S5P_PMUREG(0x1128)
|
||||
#define S5P_EPLL_SYSCLK_LOWPWR S5P_PMUREG(0x112C)
|
||||
#define S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR S5P_PMUREG(0x1138)
|
||||
#define S5P_CMU_RESET_GPSALIVE_LOWPWR S5P_PMUREG(0x113C)
|
||||
#define S5P_CMU_CLKSTOP_CAM_LOWPWR S5P_PMUREG(0x1140)
|
||||
#define S5P_CMU_CLKSTOP_TV_LOWPWR S5P_PMUREG(0x1144)
|
||||
#define S5P_CMU_CLKSTOP_MFC_LOWPWR S5P_PMUREG(0x1148)
|
||||
#define S5P_CMU_CLKSTOP_G3D_LOWPWR S5P_PMUREG(0x114C)
|
||||
#define S5P_CMU_CLKSTOP_LCD0_LOWPWR S5P_PMUREG(0x1150)
|
||||
#define S5P_CMU_CLKSTOP_LCD1_LOWPWR S5P_PMUREG(0x1154)
|
||||
#define S5P_CMU_CLKSTOP_MAUDIO_LOWPWR S5P_PMUREG(0x1158)
|
||||
#define S5P_CMU_CLKSTOP_GPS_LOWPWR S5P_PMUREG(0x115C)
|
||||
#define S5P_CMU_RESET_CAM_LOWPWR S5P_PMUREG(0x1160)
|
||||
#define S5P_CMU_RESET_TV_LOWPWR S5P_PMUREG(0x1164)
|
||||
#define S5P_CMU_RESET_MFC_LOWPWR S5P_PMUREG(0x1168)
|
||||
#define S5P_CMU_RESET_G3D_LOWPWR S5P_PMUREG(0x116C)
|
||||
#define S5P_CMU_RESET_LCD0_LOWPWR S5P_PMUREG(0x1170)
|
||||
#define S5P_CMU_RESET_LCD1_LOWPWR S5P_PMUREG(0x1174)
|
||||
#define S5P_CMU_RESET_MAUDIO_LOWPWR S5P_PMUREG(0x1178)
|
||||
#define S5P_CMU_RESET_GPS_LOWPWR S5P_PMUREG(0x117C)
|
||||
#define S5P_TOP_BUS_LOWPWR S5P_PMUREG(0x1180)
|
||||
#define S5P_TOP_RETENTION_LOWPWR S5P_PMUREG(0x1184)
|
||||
#define S5P_TOP_PWR_LOWPWR S5P_PMUREG(0x1188)
|
||||
#define S5P_LOGIC_RESET_LOWPWR S5P_PMUREG(0x11A0)
|
||||
#define S5P_ONENAND_MEM_LOWPWR S5P_PMUREG(0x11C0)
|
||||
#define S5P_MODIMIF_MEM_LOWPWR S5P_PMUREG(0x11C4)
|
||||
#define S5P_G2D_ACP_MEM_LOWPWR S5P_PMUREG(0x11C8)
|
||||
#define S5P_USBOTG_MEM_LOWPWR S5P_PMUREG(0x11CC)
|
||||
#define S5P_HSMMC_MEM_LOWPWR S5P_PMUREG(0x11D0)
|
||||
#define S5P_CSSYS_MEM_LOWPWR S5P_PMUREG(0x11D4)
|
||||
#define S5P_SECSS_MEM_LOWPWR S5P_PMUREG(0x11D8)
|
||||
#define S5P_PCIE_MEM_LOWPWR S5P_PMUREG(0x11E0)
|
||||
#define S5P_SATA_MEM_LOWPWR S5P_PMUREG(0x11E4)
|
||||
#define S5P_PAD_RETENTION_DRAM_LOWPWR S5P_PMUREG(0x1200)
|
||||
#define S5P_PAD_RETENTION_MAUDIO_LOWPWR S5P_PMUREG(0x1204)
|
||||
#define S5P_PAD_RETENTION_GPIO_LOWPWR S5P_PMUREG(0x1220)
|
||||
#define S5P_PAD_RETENTION_UART_LOWPWR S5P_PMUREG(0x1224)
|
||||
#define S5P_PAD_RETENTION_MMCA_LOWPWR S5P_PMUREG(0x1228)
|
||||
#define S5P_PAD_RETENTION_MMCB_LOWPWR S5P_PMUREG(0x122C)
|
||||
#define S5P_PAD_RETENTION_EBIA_LOWPWR S5P_PMUREG(0x1230)
|
||||
#define S5P_PAD_RETENTION_EBIB_LOWPWR S5P_PMUREG(0x1234)
|
||||
#define S5P_PAD_RETENTION_ISOLATION_LOWPWR S5P_PMUREG(0x1240)
|
||||
#define S5P_PAD_RETENTION_ALV_SEL_LOWPWR S5P_PMUREG(0x1260)
|
||||
#define S5P_XUSBXTI_LOWPWR S5P_PMUREG(0x1280)
|
||||
#define S5P_XXTI_LOWPWR S5P_PMUREG(0x1284)
|
||||
#define S5P_EXT_REGULATOR_LOWPWR S5P_PMUREG(0x12C0)
|
||||
#define S5P_GPIO_MODE_LOWPWR S5P_PMUREG(0x1300)
|
||||
#define S5P_GPIO_MODE_MAUDIO_LOWPWR S5P_PMUREG(0x1340)
|
||||
#define S5P_CAM_LOWPWR S5P_PMUREG(0x1380)
|
||||
#define S5P_TV_LOWPWR S5P_PMUREG(0x1384)
|
||||
#define S5P_MFC_LOWPWR S5P_PMUREG(0x1388)
|
||||
#define S5P_G3D_LOWPWR S5P_PMUREG(0x138C)
|
||||
#define S5P_LCD0_LOWPWR S5P_PMUREG(0x1390)
|
||||
#define S5P_LCD1_LOWPWR S5P_PMUREG(0x1394)
|
||||
#define S5P_MAUDIO_LOWPWR S5P_PMUREG(0x1398)
|
||||
#define S5P_GPS_LOWPWR S5P_PMUREG(0x139C)
|
||||
#define S5P_GPS_ALIVE_LOWPWR S5P_PMUREG(0x13A0)
|
||||
|
||||
#define S5P_ARM_CORE0_CONFIGURATION S5P_PMUREG(0x2000)
|
||||
#define S5P_ARM_CORE0_OPTION S5P_PMUREG(0x2008)
|
||||
#define S5P_ARM_CORE1_CONFIGURATION S5P_PMUREG(0x2080)
|
||||
#define S5P_ARM_CORE1_STATUS S5P_PMUREG(0x2084)
|
||||
#define S5P_ARM_CORE1_OPTION S5P_PMUREG(0x2088)
|
||||
|
||||
#define S5P_ARM_COMMON_OPTION S5P_PMUREG(0x2408)
|
||||
#define S5P_TOP_PWR_OPTION S5P_PMUREG(0x2C48)
|
||||
#define S5P_CAM_OPTION S5P_PMUREG(0x3C08)
|
||||
#define S5P_TV_OPTION S5P_PMUREG(0x3C28)
|
||||
#define S5P_MFC_OPTION S5P_PMUREG(0x3C48)
|
||||
#define S5P_G3D_OPTION S5P_PMUREG(0x3C68)
|
||||
#define S5P_LCD0_OPTION S5P_PMUREG(0x3C88)
|
||||
#define S5P_LCD1_OPTION S5P_PMUREG(0x3CA8)
|
||||
#define S5P_MAUDIO_OPTION S5P_PMUREG(0x3CC8)
|
||||
#define S5P_GPS_OPTION S5P_PMUREG(0x3CE8)
|
||||
#define S5P_GPS_ALIVE_OPTION S5P_PMUREG(0x3D08)
|
||||
|
||||
#define S5P_PAD_RET_MAUDIO_OPTION S5P_PMUREG(0x3028)
|
||||
#define S5P_PAD_RET_GPIO_OPTION S5P_PMUREG(0x3108)
|
||||
#define S5P_PAD_RET_UART_OPTION S5P_PMUREG(0x3128)
|
||||
#define S5P_PAD_RET_MMCA_OPTION S5P_PMUREG(0x3148)
|
||||
#define S5P_PAD_RET_MMCB_OPTION S5P_PMUREG(0x3168)
|
||||
#define S5P_PAD_RET_EBIA_OPTION S5P_PMUREG(0x3188)
|
||||
#define S5P_PAD_RET_EBIB_OPTION S5P_PMUREG(0x31A8)
|
||||
|
||||
#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
|
||||
#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
|
||||
#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
|
||||
#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
|
||||
#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
|
||||
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
|
||||
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
|
||||
|
||||
#define S5P_PMU_SATA_PHY_CONTROL_EN 0x1
|
||||
#define S5P_INT_LOCAL_PWR_EN 0x7
|
||||
|
||||
#define S5P_CHECK_SLEEP 0x00000BAD
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_PMU_H */
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/regs-sysmmu.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/regs-sysmmu.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - System MMU register
|
||||
* EXYNOS4 - System MMU register
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -19,6 +19,10 @@
|
|||
#define S5P_MMU_FLUSH 0x00C
|
||||
#define S5P_PT_BASE_ADDR 0x014
|
||||
#define S5P_INT_STATUS 0x018
|
||||
#define S5P_INT_CLEAR 0x01C
|
||||
#define S5P_PAGE_FAULT_ADDR 0x024
|
||||
#define S5P_AW_FAULT_ADDR 0x028
|
||||
#define S5P_AR_FAULT_ADDR 0x02C
|
||||
#define S5P_DEFAULT_SLAVE_ADDR 0x030
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_SYSMMU_H */
|
|
@ -1,4 +1,4 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/smp.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/smp.h
|
||||
*
|
||||
* Cloned from arch/arm/mach-realview/include/mach/smp.h
|
||||
*/
|
46
arch/arm/mach-exynos4/include/mach/sysmmu.h
Normal file
46
arch/arm/mach-exynos4/include/mach/sysmmu.h
Normal file
|
@ -0,0 +1,46 @@
|
|||
/* linux/arch/arm/mach-exynos4/include/mach/sysmmu.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Samsung sysmmu driver for EXYNOS4
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_SYSMMU_H
|
||||
#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
|
||||
|
||||
enum exynos4_sysmmu_ips {
|
||||
SYSMMU_MDMA,
|
||||
SYSMMU_SSS,
|
||||
SYSMMU_FIMC0,
|
||||
SYSMMU_FIMC1,
|
||||
SYSMMU_FIMC2,
|
||||
SYSMMU_FIMC3,
|
||||
SYSMMU_JPEG,
|
||||
SYSMMU_FIMD0,
|
||||
SYSMMU_FIMD1,
|
||||
SYSMMU_PCIe,
|
||||
SYSMMU_G2D,
|
||||
SYSMMU_ROTATOR,
|
||||
SYSMMU_MDMA2,
|
||||
SYSMMU_TV,
|
||||
SYSMMU_MFC_L,
|
||||
SYSMMU_MFC_R,
|
||||
EXYNOS4_SYSMMU_TOTAL_IPNUM,
|
||||
};
|
||||
|
||||
#define S5P_SYSMMU_TOTAL_IPNUM EXYNOS4_SYSMMU_TOTAL_IPNUM
|
||||
|
||||
extern const char *sysmmu_ips_name[EXYNOS4_SYSMMU_TOTAL_IPNUM];
|
||||
|
||||
typedef enum exynos4_sysmmu_ips sysmmu_ips;
|
||||
|
||||
void sysmmu_clk_init(struct device *dev, sysmmu_ips ips);
|
||||
void sysmmu_clk_enable(sysmmu_ips ips);
|
||||
void sysmmu_clk_disable(sysmmu_ips ips);
|
||||
|
||||
#endif /* __ASM_ARM_ARCH_SYSMMU_H */
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/system.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/system.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - system support header
|
||||
* EXYNOS4 - system support header
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
|
@ -1,14 +1,14 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/timex.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/timex.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright (c) 2003-2010 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* Based on arch/arm/mach-s5p6442/include/mach/timex.h
|
||||
*
|
||||
* S5PV310 - time parameters
|
||||
* EXYNOS4 - time parameters
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/uncompress.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/uncompress.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - uncompress code
|
||||
* EXYNOS4 - uncompress code
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
|
@ -1,7 +1,7 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/vmalloc.h
|
||||
/* linux/arch/arm/mach-exynos4/include/mach/vmalloc.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Copyright 2010 Ben Dooks <ben-linux@fluff.org>
|
||||
*
|
||||
|
@ -11,7 +11,7 @@
|
|||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* S5PV310 vmalloc definition
|
||||
* EXYNOS4 vmalloc definition
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_VMALLOC_H
|
|
@ -1,4 +1,4 @@
|
|||
/* linux/arch/arm/mach-s5pv310/init.c
|
||||
/* linux/arch/arm/mach-exynos4/init.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
|
@ -14,7 +14,7 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/regs-serial.h>
|
||||
|
||||
static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
|
||||
static struct s3c24xx_uart_clksrc exynos4_serial_clocks[] = {
|
||||
[0] = {
|
||||
.name = "uclk1",
|
||||
.divisor = 1,
|
||||
|
@ -24,7 +24,7 @@ static struct s3c24xx_uart_clksrc s5pv310_serial_clocks[] = {
|
|||
};
|
||||
|
||||
/* uart registration process */
|
||||
void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
void __init exynos4_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
||||
{
|
||||
struct s3c2410_uartcfg *tcfg = cfg;
|
||||
u32 ucnt;
|
||||
|
@ -32,8 +32,8 @@ void __init s5pv310_common_init_uarts(struct s3c2410_uartcfg *cfg, int no)
|
|||
for (ucnt = 0; ucnt < no; ucnt++, tcfg++) {
|
||||
if (!tcfg->clocks) {
|
||||
tcfg->has_fracval = 1;
|
||||
tcfg->clocks = s5pv310_serial_clocks;
|
||||
tcfg->clocks_size = ARRAY_SIZE(s5pv310_serial_clocks);
|
||||
tcfg->clocks = exynos4_serial_clocks;
|
||||
tcfg->clocks_size = ARRAY_SIZE(exynos4_serial_clocks);
|
||||
}
|
||||
}
|
||||
|
|
@ -1,6 +1,6 @@
|
|||
/* linux/arch/arm/mach-s5pv310/irq-combiner.c
|
||||
/* linux/arch/arm/mach-exynos4/irq-combiner.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Based on arch/arm/common/gic.c
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/irq-eint.c
|
||||
/* linux/arch/arm/mach-exynos4/irq-eint.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - IRQ EINT support
|
||||
* EXYNOS4 - IRQ EINT support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -27,7 +27,7 @@ static DEFINE_SPINLOCK(eint_lock);
|
|||
|
||||
static unsigned int eint0_15_data[16];
|
||||
|
||||
static unsigned int s5pv310_get_irq_nr(unsigned int number)
|
||||
static unsigned int exynos4_get_irq_nr(unsigned int number)
|
||||
{
|
||||
u32 ret = 0;
|
||||
|
||||
|
@ -48,7 +48,7 @@ static unsigned int s5pv310_get_irq_nr(unsigned int number)
|
|||
return ret;
|
||||
}
|
||||
|
||||
static inline void s5pv310_irq_eint_mask(struct irq_data *data)
|
||||
static inline void exynos4_irq_eint_mask(struct irq_data *data)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
|
@ -59,7 +59,7 @@ static inline void s5pv310_irq_eint_mask(struct irq_data *data)
|
|||
spin_unlock(&eint_lock);
|
||||
}
|
||||
|
||||
static void s5pv310_irq_eint_unmask(struct irq_data *data)
|
||||
static void exynos4_irq_eint_unmask(struct irq_data *data)
|
||||
{
|
||||
u32 mask;
|
||||
|
||||
|
@ -70,19 +70,19 @@ static void s5pv310_irq_eint_unmask(struct irq_data *data)
|
|||
spin_unlock(&eint_lock);
|
||||
}
|
||||
|
||||
static inline void s5pv310_irq_eint_ack(struct irq_data *data)
|
||||
static inline void exynos4_irq_eint_ack(struct irq_data *data)
|
||||
{
|
||||
__raw_writel(eint_irq_to_bit(data->irq),
|
||||
S5P_EINT_PEND(EINT_REG_NR(data->irq)));
|
||||
}
|
||||
|
||||
static void s5pv310_irq_eint_maskack(struct irq_data *data)
|
||||
static void exynos4_irq_eint_maskack(struct irq_data *data)
|
||||
{
|
||||
s5pv310_irq_eint_mask(data);
|
||||
s5pv310_irq_eint_ack(data);
|
||||
exynos4_irq_eint_mask(data);
|
||||
exynos4_irq_eint_ack(data);
|
||||
}
|
||||
|
||||
static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
|
||||
static int exynos4_irq_eint_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
int offs = EINT_OFFSET(data->irq);
|
||||
int shift;
|
||||
|
@ -145,19 +145,19 @@ static int s5pv310_irq_eint_set_type(struct irq_data *data, unsigned int type)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static struct irq_chip s5pv310_irq_eint = {
|
||||
.name = "s5pv310-eint",
|
||||
.irq_mask = s5pv310_irq_eint_mask,
|
||||
.irq_unmask = s5pv310_irq_eint_unmask,
|
||||
.irq_mask_ack = s5pv310_irq_eint_maskack,
|
||||
.irq_ack = s5pv310_irq_eint_ack,
|
||||
.irq_set_type = s5pv310_irq_eint_set_type,
|
||||
static struct irq_chip exynos4_irq_eint = {
|
||||
.name = "exynos4-eint",
|
||||
.irq_mask = exynos4_irq_eint_mask,
|
||||
.irq_unmask = exynos4_irq_eint_unmask,
|
||||
.irq_mask_ack = exynos4_irq_eint_maskack,
|
||||
.irq_ack = exynos4_irq_eint_ack,
|
||||
.irq_set_type = exynos4_irq_eint_set_type,
|
||||
#ifdef CONFIG_PM
|
||||
.irq_set_wake = s3c_irqext_wake,
|
||||
#endif
|
||||
};
|
||||
|
||||
/* s5pv310_irq_demux_eint
|
||||
/* exynos4_irq_demux_eint
|
||||
*
|
||||
* This function demuxes the IRQ from from EINTs 16 to 31.
|
||||
* It is designed to be inlined into the specific handler
|
||||
|
@ -165,7 +165,7 @@ static struct irq_chip s5pv310_irq_eint = {
|
|||
*
|
||||
* Each EINT pend/mask registers handle eight of them.
|
||||
*/
|
||||
static inline void s5pv310_irq_demux_eint(unsigned int start)
|
||||
static inline void exynos4_irq_demux_eint(unsigned int start)
|
||||
{
|
||||
unsigned int irq;
|
||||
|
||||
|
@ -182,13 +182,13 @@ static inline void s5pv310_irq_demux_eint(unsigned int start)
|
|||
}
|
||||
}
|
||||
|
||||
static void s5pv310_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
|
||||
static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
s5pv310_irq_demux_eint(IRQ_EINT(16));
|
||||
s5pv310_irq_demux_eint(IRQ_EINT(24));
|
||||
exynos4_irq_demux_eint(IRQ_EINT(16));
|
||||
exynos4_irq_demux_eint(IRQ_EINT(24));
|
||||
}
|
||||
|
||||
static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
||||
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
||||
{
|
||||
u32 *irq_data = get_irq_data(irq);
|
||||
struct irq_chip *chip = get_irq_chip(irq);
|
||||
|
@ -203,27 +203,27 @@ static void s5pv310_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
|
|||
chip->irq_unmask(&desc->irq_data);
|
||||
}
|
||||
|
||||
int __init s5pv310_init_irq_eint(void)
|
||||
int __init exynos4_init_irq_eint(void)
|
||||
{
|
||||
int irq;
|
||||
|
||||
for (irq = 0 ; irq <= 31 ; irq++) {
|
||||
set_irq_chip(IRQ_EINT(irq), &s5pv310_irq_eint);
|
||||
set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint);
|
||||
set_irq_handler(IRQ_EINT(irq), handle_level_irq);
|
||||
set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
|
||||
}
|
||||
|
||||
set_irq_chained_handler(IRQ_EINT16_31, s5pv310_irq_demux_eint16_31);
|
||||
set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
|
||||
|
||||
for (irq = 0 ; irq <= 15 ; irq++) {
|
||||
eint0_15_data[irq] = IRQ_EINT(irq);
|
||||
|
||||
set_irq_data(s5pv310_get_irq_nr(irq), &eint0_15_data[irq]);
|
||||
set_irq_chained_handler(s5pv310_get_irq_nr(irq),
|
||||
s5pv310_irq_eint0_15);
|
||||
set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
|
||||
set_irq_chained_handler(exynos4_get_irq_nr(irq),
|
||||
exynos4_irq_eint0_15);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
arch_initcall(s5pv310_init_irq_eint);
|
||||
arch_initcall(exynos4_init_irq_eint);
|
|
@ -1,4 +1,4 @@
|
|||
/* linux/arch/arm/mach-s5pv310/localtimer.c
|
||||
/* linux/arch/arm/mach-exynos4/localtimer.c
|
||||
*
|
||||
* Cloned from linux/arch/arm/mach-realview/localtimer.c
|
||||
*
|
215
arch/arm/mach-exynos4/mach-armlex4210.c
Normal file
215
arch/arm/mach-exynos4/mach-armlex4210.c
Normal file
|
@ -0,0 +1,215 @@
|
|||
/* linux/arch/arm/mach-exynos4/mach-armlex4210.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/smsc911x.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-srom.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define ARMLEX4210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
S3C2410_UCON_TXIRQMODE | \
|
||||
S3C2410_UCON_RXIRQMODE | \
|
||||
S3C2410_UCON_RXFIFO_TOI | \
|
||||
S3C2443_UCON_RXERR_IRQEN)
|
||||
|
||||
#define ARMLEX4210_ULCON_DEFAULT S3C2410_LCON_CS8
|
||||
|
||||
#define ARMLEX4210_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
|
||||
S5PV210_UFCON_TXTRIG4 | \
|
||||
S5PV210_UFCON_RXTRIG4)
|
||||
|
||||
static struct s3c2410_uartcfg armlex4210_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.flags = 0,
|
||||
.ucon = ARMLEX4210_UCON_DEFAULT,
|
||||
.ulcon = ARMLEX4210_ULCON_DEFAULT,
|
||||
.ufcon = ARMLEX4210_UFCON_DEFAULT,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.flags = 0,
|
||||
.ucon = ARMLEX4210_UCON_DEFAULT,
|
||||
.ulcon = ARMLEX4210_ULCON_DEFAULT,
|
||||
.ufcon = ARMLEX4210_UFCON_DEFAULT,
|
||||
},
|
||||
[2] = {
|
||||
.hwport = 2,
|
||||
.flags = 0,
|
||||
.ucon = ARMLEX4210_UCON_DEFAULT,
|
||||
.ulcon = ARMLEX4210_ULCON_DEFAULT,
|
||||
.ufcon = ARMLEX4210_UFCON_DEFAULT,
|
||||
},
|
||||
[3] = {
|
||||
.hwport = 3,
|
||||
.flags = 0,
|
||||
.ucon = ARMLEX4210_UCON_DEFAULT,
|
||||
.ulcon = ARMLEX4210_ULCON_DEFAULT,
|
||||
.ufcon = ARMLEX4210_UFCON_DEFAULT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata armlex4210_hsmmc0_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata armlex4210_hsmmc2_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = EXYNOS4_GPX2(5),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
.max_width = 4,
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata armlex4210_hsmmc3_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
.max_width = 4,
|
||||
};
|
||||
|
||||
static void __init armlex4210_sdhci_init(void)
|
||||
{
|
||||
s3c_sdhci0_set_platdata(&armlex4210_hsmmc0_pdata);
|
||||
s3c_sdhci2_set_platdata(&armlex4210_hsmmc2_pdata);
|
||||
s3c_sdhci3_set_platdata(&armlex4210_hsmmc3_pdata);
|
||||
}
|
||||
|
||||
static void __init armlex4210_wlan_init(void)
|
||||
{
|
||||
/* enable */
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX2(0), S3C_GPIO_SFN(0xf));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX2(0), S3C_GPIO_PULL_UP);
|
||||
|
||||
/* reset */
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX1(6), S3C_GPIO_SFN(0xf));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX1(6), S3C_GPIO_PULL_UP);
|
||||
|
||||
/* wakeup */
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPX1(5), S3C_GPIO_SFN(0xf));
|
||||
s3c_gpio_setpull(EXYNOS4_GPX1(5), S3C_GPIO_PULL_UP);
|
||||
}
|
||||
|
||||
static struct resource armlex4210_smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_SROM_BANK(3),
|
||||
.end = EXYNOS4_PA_SROM_BANK(3) + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_EINT(27),
|
||||
.end = IRQ_EINT(27),
|
||||
.flags = IORESOURCE_IRQ | IRQF_TRIGGER_HIGH,
|
||||
},
|
||||
};
|
||||
|
||||
static struct smsc911x_platform_config smsc9215_config = {
|
||||
.irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
|
||||
.irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
|
||||
.flags = SMSC911X_USE_16BIT | SMSC911X_FORCE_INTERNAL_PHY,
|
||||
.phy_interface = PHY_INTERFACE_MODE_MII,
|
||||
.mac = {0x00, 0x80, 0x00, 0x23, 0x45, 0x67},
|
||||
};
|
||||
|
||||
static struct platform_device armlex4210_smsc911x = {
|
||||
.name = "smsc911x",
|
||||
.id = -1,
|
||||
.num_resources = ARRAY_SIZE(armlex4210_smsc911x_resources),
|
||||
.resource = armlex4210_smsc911x_resources,
|
||||
.dev = {
|
||||
.platform_data = &smsc9215_config,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *armlex4210_devices[] __initdata = {
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_wdt,
|
||||
&exynos4_device_sysmmu,
|
||||
&samsung_asoc_dma,
|
||||
&armlex4210_smsc911x,
|
||||
&exynos4_device_ahci,
|
||||
};
|
||||
|
||||
static void __init armlex4210_smsc911x_init(void)
|
||||
{
|
||||
u32 cs1;
|
||||
|
||||
/* configure nCS1 width to 16 bits */
|
||||
cs1 = __raw_readl(S5P_SROM_BW) &
|
||||
~(S5P_SROM_BW__CS_MASK << S5P_SROM_BW__NCS1__SHIFT);
|
||||
cs1 |= ((1 << S5P_SROM_BW__DATAWIDTH__SHIFT) |
|
||||
(0 << S5P_SROM_BW__WAITENABLE__SHIFT) |
|
||||
(1 << S5P_SROM_BW__ADDRMODE__SHIFT) |
|
||||
(1 << S5P_SROM_BW__BYTEENABLE__SHIFT)) <<
|
||||
S5P_SROM_BW__NCS1__SHIFT;
|
||||
__raw_writel(cs1, S5P_SROM_BW);
|
||||
|
||||
/* set timing for nCS1 suitable for ethernet chip */
|
||||
__raw_writel((0x1 << S5P_SROM_BCX__PMC__SHIFT) |
|
||||
(0x9 << S5P_SROM_BCX__TACP__SHIFT) |
|
||||
(0xc << S5P_SROM_BCX__TCAH__SHIFT) |
|
||||
(0x1 << S5P_SROM_BCX__TCOH__SHIFT) |
|
||||
(0x6 << S5P_SROM_BCX__TACC__SHIFT) |
|
||||
(0x1 << S5P_SROM_BCX__TCOS__SHIFT) |
|
||||
(0x1 << S5P_SROM_BCX__TACS__SHIFT), S5P_SROM_BC1);
|
||||
}
|
||||
|
||||
static void __init armlex4210_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(armlex4210_uartcfgs,
|
||||
ARRAY_SIZE(armlex4210_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init armlex4210_machine_init(void)
|
||||
{
|
||||
armlex4210_smsc911x_init();
|
||||
|
||||
armlex4210_sdhci_init();
|
||||
|
||||
armlex4210_wlan_init();
|
||||
|
||||
platform_add_devices(armlex4210_devices,
|
||||
ARRAY_SIZE(armlex4210_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(ARMLEX4210, "ARMLEX4210")
|
||||
/* Maintainer: Alim Akhtar <alim.akhtar@samsung.com> */
|
||||
.boot_params = S5P_PA_SDRAM + 0x100,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = armlex4210_map_io,
|
||||
.init_machine = armlex4210_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
MACHINE_END
|
305
arch/arm/mach-exynos4/mach-nuri.c
Normal file
305
arch/arm/mach-exynos4/mach-nuri.c
Normal file
|
@ -0,0 +1,305 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-exynos4/mach-nuri.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/fb.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define NURI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
S3C2410_UCON_TXIRQMODE | \
|
||||
S3C2410_UCON_RXIRQMODE | \
|
||||
S3C2410_UCON_RXFIFO_TOI | \
|
||||
S3C2443_UCON_RXERR_IRQEN)
|
||||
|
||||
#define NURI_ULCON_DEFAULT S3C2410_LCON_CS8
|
||||
|
||||
#define NURI_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
|
||||
S5PV210_UFCON_TXTRIG256 | \
|
||||
S5PV210_UFCON_RXTRIG256)
|
||||
|
||||
enum fixed_regulator_id {
|
||||
FIXED_REG_ID_MMC = 0,
|
||||
};
|
||||
|
||||
static struct s3c2410_uartcfg nuri_uartcfgs[] __initdata = {
|
||||
{
|
||||
.hwport = 0,
|
||||
.ucon = NURI_UCON_DEFAULT,
|
||||
.ulcon = NURI_ULCON_DEFAULT,
|
||||
.ufcon = NURI_UFCON_DEFAULT,
|
||||
},
|
||||
{
|
||||
.hwport = 1,
|
||||
.ucon = NURI_UCON_DEFAULT,
|
||||
.ulcon = NURI_ULCON_DEFAULT,
|
||||
.ufcon = NURI_UFCON_DEFAULT,
|
||||
},
|
||||
{
|
||||
.hwport = 2,
|
||||
.ucon = NURI_UCON_DEFAULT,
|
||||
.ulcon = NURI_ULCON_DEFAULT,
|
||||
.ufcon = NURI_UFCON_DEFAULT,
|
||||
},
|
||||
{
|
||||
.hwport = 3,
|
||||
.ucon = NURI_UCON_DEFAULT,
|
||||
.ulcon = NURI_ULCON_DEFAULT,
|
||||
.ufcon = NURI_UFCON_DEFAULT,
|
||||
},
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
|
||||
.max_width = 8,
|
||||
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_DISABLE | MMC_CAP_ERASE),
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply emmc_supplies[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
|
||||
REGULATOR_SUPPLY("vmmc", "dw_mmc"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data emmc_fixed_voltage_init_data = {
|
||||
.constraints = {
|
||||
.name = "VMEM_VDD_2.8V",
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(emmc_supplies),
|
||||
.consumer_supplies = emmc_supplies,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config emmc_fixed_voltage_config = {
|
||||
.supply_name = "MASSMEMORY_EN (inverted)",
|
||||
.microvolts = 2800000,
|
||||
.gpio = EXYNOS4_GPL1(1),
|
||||
.enable_high = false,
|
||||
.init_data = &emmc_fixed_voltage_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device emmc_fixed_voltage = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = FIXED_REG_ID_MMC,
|
||||
.dev = {
|
||||
.platform_data = &emmc_fixed_voltage_config,
|
||||
},
|
||||
};
|
||||
|
||||
/* SD */
|
||||
static struct s3c_sdhci_platdata nuri_hsmmc2_data __initdata = {
|
||||
.max_width = 4,
|
||||
.host_caps = MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_DISABLE,
|
||||
.ext_cd_gpio = EXYNOS4_GPX3(3), /* XEINT_27 */
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
/* WLAN */
|
||||
static struct s3c_sdhci_platdata nuri_hsmmc3_data __initdata = {
|
||||
.max_width = 4,
|
||||
.host_caps = MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED,
|
||||
.cd_type = S3C_SDHCI_CD_EXTERNAL,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static void __init nuri_sdhci_init(void)
|
||||
{
|
||||
s3c_sdhci0_set_platdata(&nuri_hsmmc0_data);
|
||||
s3c_sdhci2_set_platdata(&nuri_hsmmc2_data);
|
||||
s3c_sdhci3_set_platdata(&nuri_hsmmc3_data);
|
||||
}
|
||||
|
||||
/* GPIO KEYS */
|
||||
static struct gpio_keys_button nuri_gpio_keys_tables[] = {
|
||||
{
|
||||
.code = KEY_VOLUMEUP,
|
||||
.gpio = EXYNOS4_GPX2(0), /* XEINT16 */
|
||||
.desc = "gpio-keys: KEY_VOLUMEUP",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_VOLUMEDOWN,
|
||||
.gpio = EXYNOS4_GPX2(1), /* XEINT17 */
|
||||
.desc = "gpio-keys: KEY_VOLUMEDOWN",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_POWER,
|
||||
.gpio = EXYNOS4_GPX2(7), /* XEINT23 */
|
||||
.desc = "gpio-keys: KEY_POWER",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.wakeup = 1,
|
||||
.debounce_interval = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data nuri_gpio_keys_data = {
|
||||
.buttons = nuri_gpio_keys_tables,
|
||||
.nbuttons = ARRAY_SIZE(nuri_gpio_keys_tables),
|
||||
};
|
||||
|
||||
static struct platform_device nuri_gpio_keys = {
|
||||
.name = "gpio-keys",
|
||||
.dev = {
|
||||
.platform_data = &nuri_gpio_keys_data,
|
||||
},
|
||||
};
|
||||
|
||||
static void nuri_lcd_power_on(struct plat_lcd_data *pd, unsigned int power)
|
||||
{
|
||||
int gpio = EXYNOS4_GPE1(5);
|
||||
|
||||
gpio_request(gpio, "LVDS_nSHDN");
|
||||
gpio_direction_output(gpio, power);
|
||||
gpio_free(gpio);
|
||||
}
|
||||
|
||||
static int nuri_bl_init(struct device *dev)
|
||||
{
|
||||
int ret, gpio = EXYNOS4_GPE2(3);
|
||||
|
||||
ret = gpio_request(gpio, "LCD_LDO_EN");
|
||||
if (!ret)
|
||||
gpio_direction_output(gpio, 0);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int nuri_bl_notify(struct device *dev, int brightness)
|
||||
{
|
||||
if (brightness < 1)
|
||||
brightness = 0;
|
||||
|
||||
gpio_set_value(EXYNOS4_GPE2(3), 1);
|
||||
|
||||
return brightness;
|
||||
}
|
||||
|
||||
static void nuri_bl_exit(struct device *dev)
|
||||
{
|
||||
gpio_free(EXYNOS4_GPE2(3));
|
||||
}
|
||||
|
||||
/* nuri pwm backlight */
|
||||
static struct platform_pwm_backlight_data nuri_backlight_data = {
|
||||
.pwm_id = 0,
|
||||
.pwm_period_ns = 30000,
|
||||
.max_brightness = 100,
|
||||
.dft_brightness = 50,
|
||||
.init = nuri_bl_init,
|
||||
.notify = nuri_bl_notify,
|
||||
.exit = nuri_bl_exit,
|
||||
};
|
||||
|
||||
static struct platform_device nuri_backlight_device = {
|
||||
.name = "pwm-backlight",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.parent = &s3c_device_timer[0].dev,
|
||||
.platform_data = &nuri_backlight_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct plat_lcd_data nuri_lcd_platform_data = {
|
||||
.set_power = nuri_lcd_power_on,
|
||||
};
|
||||
|
||||
static struct platform_device nuri_lcd_device = {
|
||||
.name = "platform-lcd",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = &nuri_lcd_platform_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* I2C1 */
|
||||
static struct i2c_board_info i2c1_devs[] __initdata = {
|
||||
/* Gyro, To be updated */
|
||||
};
|
||||
|
||||
/* GPIO I2C 5 (PMIC) */
|
||||
static struct i2c_board_info i2c5_devs[] __initdata = {
|
||||
/* max8997, To be updated */
|
||||
};
|
||||
|
||||
static struct platform_device *nuri_devices[] __initdata = {
|
||||
/* Samsung Platform Devices */
|
||||
&emmc_fixed_voltage,
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
&s3c_device_wdt,
|
||||
&s3c_device_timer[0],
|
||||
|
||||
/* NURI Devices */
|
||||
&nuri_gpio_keys,
|
||||
&nuri_lcd_device,
|
||||
&nuri_backlight_device,
|
||||
};
|
||||
|
||||
static void __init nuri_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(nuri_uartcfgs, ARRAY_SIZE(nuri_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init nuri_machine_init(void)
|
||||
{
|
||||
nuri_sdhci_init();
|
||||
|
||||
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
|
||||
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
|
||||
|
||||
/* Last */
|
||||
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(NURI, "NURI")
|
||||
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
|
||||
.boot_params = S5P_PA_SDRAM + 0x100,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = nuri_map_io,
|
||||
.init_machine = nuri_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
MACHINE_END
|
|
@ -1,7 +1,7 @@
|
|||
/* linux/arch/arm/mach-s5pv310/mach-smdkc210.c
|
||||
/* linux/arch/arm/mach-exynos4/mach-smdkc210.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -21,7 +21,7 @@
|
|||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-srom.h>
|
||||
#include <plat/s5pv310.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
@ -77,10 +77,10 @@ static struct s3c2410_uartcfg smdkc210_uartcfgs[] __initdata = {
|
|||
|
||||
static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = S5PV310_GPK0(2),
|
||||
.ext_cd_gpio = EXYNOS4_GPK0(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
#endif
|
||||
|
@ -88,17 +88,17 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc0_pdata __initdata = {
|
|||
|
||||
static struct s3c_sdhci_platdata smdkc210_hsmmc1_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = S5PV310_GPK0(2),
|
||||
.ext_cd_gpio = EXYNOS4_GPK0(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = S5PV310_GPK2(2),
|
||||
.ext_cd_gpio = EXYNOS4_GPK2(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
#endif
|
||||
|
@ -106,15 +106,15 @@ static struct s3c_sdhci_platdata smdkc210_hsmmc2_pdata __initdata = {
|
|||
|
||||
static struct s3c_sdhci_platdata smdkc210_hsmmc3_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = S5PV310_GPK2(2),
|
||||
.ext_cd_gpio = EXYNOS4_GPK2(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct resource smdkc210_smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_SROM_BANK(1),
|
||||
.end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SROM_BANK(1),
|
||||
.end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -154,16 +154,16 @@ static struct platform_device *smdkc210_devices[] __initdata = {
|
|||
&s3c_device_i2c1,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_wdt,
|
||||
&s5pv310_device_ac97,
|
||||
&s5pv310_device_i2s0,
|
||||
&s5pv310_device_pd[PD_MFC],
|
||||
&s5pv310_device_pd[PD_G3D],
|
||||
&s5pv310_device_pd[PD_LCD0],
|
||||
&s5pv310_device_pd[PD_LCD1],
|
||||
&s5pv310_device_pd[PD_CAM],
|
||||
&s5pv310_device_pd[PD_TV],
|
||||
&s5pv310_device_pd[PD_GPS],
|
||||
&s5pv310_device_sysmmu,
|
||||
&exynos4_device_ac97,
|
||||
&exynos4_device_i2s0,
|
||||
&exynos4_device_pd[PD_MFC],
|
||||
&exynos4_device_pd[PD_G3D],
|
||||
&exynos4_device_pd[PD_LCD0],
|
||||
&exynos4_device_pd[PD_LCD1],
|
||||
&exynos4_device_pd[PD_CAM],
|
||||
&exynos4_device_pd[PD_TV],
|
||||
&exynos4_device_pd[PD_GPS],
|
||||
&exynos4_device_sysmmu,
|
||||
&samsung_asoc_dma,
|
||||
&smdkc210_smsc911x,
|
||||
};
|
||||
|
@ -216,8 +216,8 @@ static void __init smdkc210_machine_init(void)
|
|||
MACHINE_START(SMDKC210, "SMDKC210")
|
||||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
.boot_params = S5P_PA_SDRAM + 0x100,
|
||||
.init_irq = s5pv310_init_irq,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkc210_map_io,
|
||||
.init_machine = smdkc210_machine_init,
|
||||
.timer = &s5pv310_timer,
|
||||
.timer = &exynos4_timer,
|
||||
MACHINE_END
|
|
@ -1,7 +1,7 @@
|
|||
/* linux/arch/arm/mach-s5pv310/mach-smdkv310.c
|
||||
/* linux/arch/arm/mach-exynos4/mach-smdkv310.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -15,15 +15,17 @@
|
|||
#include <linux/smsc911x.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/input.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/regs-srom.h>
|
||||
#include <plat/s5pv310.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/keypad.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/pd.h>
|
||||
|
@ -77,10 +79,10 @@ static struct s3c2410_uartcfg smdkv310_uartcfgs[] __initdata = {
|
|||
|
||||
static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = S5PV310_GPK0(2),
|
||||
.ext_cd_gpio = EXYNOS4_GPK0(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_S5PV310_SDHCI_CH0_8BIT
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH0_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
#endif
|
||||
|
@ -88,17 +90,17 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc0_pdata __initdata = {
|
|||
|
||||
static struct s3c_sdhci_platdata smdkv310_hsmmc1_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = S5PV310_GPK0(2),
|
||||
.ext_cd_gpio = EXYNOS4_GPK0(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = S5PV310_GPK2(2),
|
||||
.ext_cd_gpio = EXYNOS4_GPK2(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
#ifdef CONFIG_S5PV310_SDHCI_CH2_8BIT
|
||||
#ifdef CONFIG_EXYNOS4_SDHCI_CH2_8BIT
|
||||
.max_width = 8,
|
||||
.host_caps = MMC_CAP_8_BIT_DATA,
|
||||
#endif
|
||||
|
@ -106,15 +108,15 @@ static struct s3c_sdhci_platdata smdkv310_hsmmc2_pdata __initdata = {
|
|||
|
||||
static struct s3c_sdhci_platdata smdkv310_hsmmc3_pdata __initdata = {
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.ext_cd_gpio = S5PV310_GPK2(2),
|
||||
.ext_cd_gpio = EXYNOS4_GPK2(2),
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct resource smdkv310_smsc911x_resources[] = {
|
||||
[0] = {
|
||||
.start = S5PV310_PA_SROM_BANK(1),
|
||||
.end = S5PV310_PA_SROM_BANK(1) + SZ_64K - 1,
|
||||
.start = EXYNOS4_PA_SROM_BANK(1),
|
||||
.end = EXYNOS4_PA_SROM_BANK(1) + SZ_64K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
|
@ -142,6 +144,25 @@ static struct platform_device smdkv310_smsc911x = {
|
|||
},
|
||||
};
|
||||
|
||||
static uint32_t smdkv310_keymap[] __initdata = {
|
||||
/* KEY(row, col, keycode) */
|
||||
KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
|
||||
KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
|
||||
KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
|
||||
KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
|
||||
};
|
||||
|
||||
static struct matrix_keymap_data smdkv310_keymap_data __initdata = {
|
||||
.keymap = smdkv310_keymap,
|
||||
.keymap_size = ARRAY_SIZE(smdkv310_keymap),
|
||||
};
|
||||
|
||||
static struct samsung_keypad_platdata smdkv310_keypad_data __initdata = {
|
||||
.keymap_data = &smdkv310_keymap_data,
|
||||
.rows = 2,
|
||||
.cols = 8,
|
||||
};
|
||||
|
||||
static struct i2c_board_info i2c_devs1[] __initdata = {
|
||||
{I2C_BOARD_INFO("wm8994", 0x1a),},
|
||||
};
|
||||
|
@ -154,16 +175,17 @@ static struct platform_device *smdkv310_devices[] __initdata = {
|
|||
&s3c_device_i2c1,
|
||||
&s3c_device_rtc,
|
||||
&s3c_device_wdt,
|
||||
&s5pv310_device_ac97,
|
||||
&s5pv310_device_i2s0,
|
||||
&s5pv310_device_pd[PD_MFC],
|
||||
&s5pv310_device_pd[PD_G3D],
|
||||
&s5pv310_device_pd[PD_LCD0],
|
||||
&s5pv310_device_pd[PD_LCD1],
|
||||
&s5pv310_device_pd[PD_CAM],
|
||||
&s5pv310_device_pd[PD_TV],
|
||||
&s5pv310_device_pd[PD_GPS],
|
||||
&s5pv310_device_sysmmu,
|
||||
&exynos4_device_ac97,
|
||||
&exynos4_device_i2s0,
|
||||
&samsung_device_keypad,
|
||||
&exynos4_device_pd[PD_MFC],
|
||||
&exynos4_device_pd[PD_G3D],
|
||||
&exynos4_device_pd[PD_LCD0],
|
||||
&exynos4_device_pd[PD_LCD1],
|
||||
&exynos4_device_pd[PD_CAM],
|
||||
&exynos4_device_pd[PD_TV],
|
||||
&exynos4_device_pd[PD_GPS],
|
||||
&exynos4_device_sysmmu,
|
||||
&samsung_asoc_dma,
|
||||
&smdkv310_smsc911x,
|
||||
};
|
||||
|
@ -210,6 +232,8 @@ static void __init smdkv310_machine_init(void)
|
|||
s3c_sdhci2_set_platdata(&smdkv310_hsmmc2_pdata);
|
||||
s3c_sdhci3_set_platdata(&smdkv310_hsmmc3_pdata);
|
||||
|
||||
samsung_keypad_set_platdata(&smdkv310_keypad_data);
|
||||
|
||||
platform_add_devices(smdkv310_devices, ARRAY_SIZE(smdkv310_devices));
|
||||
}
|
||||
|
||||
|
@ -217,8 +241,8 @@ MACHINE_START(SMDKV310, "SMDKV310")
|
|||
/* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
|
||||
/* Maintainer: Changhwan Youn <chaos.youn@samsung.com> */
|
||||
.boot_params = S5P_PA_SDRAM + 0x100,
|
||||
.init_irq = s5pv310_init_irq,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = smdkv310_map_io,
|
||||
.init_machine = smdkv310_machine_init,
|
||||
.timer = &s5pv310_timer,
|
||||
.timer = &exynos4_timer,
|
||||
MACHINE_END
|
650
arch/arm/mach-exynos4/mach-universal_c210.c
Normal file
650
arch/arm/mach-exynos4/mach-universal_c210.c
Normal file
|
@ -0,0 +1,650 @@
|
|||
/* linux/arch/arm/mach-exynos4/mach-universal_c210.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/mfd/max8998.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/max8952.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/exynos4.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
S3C2410_UCON_TXIRQMODE | \
|
||||
S3C2410_UCON_RXIRQMODE | \
|
||||
S3C2410_UCON_RXFIFO_TOI | \
|
||||
S3C2443_UCON_RXERR_IRQEN)
|
||||
|
||||
#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
|
||||
|
||||
#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
|
||||
S5PV210_UFCON_TXTRIG256 | \
|
||||
S5PV210_UFCON_RXTRIG256)
|
||||
|
||||
static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.ucon = UNIVERSAL_UCON_DEFAULT,
|
||||
.ulcon = UNIVERSAL_ULCON_DEFAULT,
|
||||
.ufcon = UNIVERSAL_UFCON_DEFAULT,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.ucon = UNIVERSAL_UCON_DEFAULT,
|
||||
.ulcon = UNIVERSAL_ULCON_DEFAULT,
|
||||
.ufcon = UNIVERSAL_UFCON_DEFAULT,
|
||||
},
|
||||
[2] = {
|
||||
.hwport = 2,
|
||||
.ucon = UNIVERSAL_UCON_DEFAULT,
|
||||
.ulcon = UNIVERSAL_ULCON_DEFAULT,
|
||||
.ufcon = UNIVERSAL_UFCON_DEFAULT,
|
||||
},
|
||||
[3] = {
|
||||
.hwport = 3,
|
||||
.ucon = UNIVERSAL_UCON_DEFAULT,
|
||||
.ulcon = UNIVERSAL_ULCON_DEFAULT,
|
||||
.ufcon = UNIVERSAL_UFCON_DEFAULT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply max8952_consumer =
|
||||
REGULATOR_SUPPLY("vddarm", NULL);
|
||||
|
||||
static struct max8952_platform_data universal_max8952_pdata __initdata = {
|
||||
.gpio_vid0 = EXYNOS4_GPX0(3),
|
||||
.gpio_vid1 = EXYNOS4_GPX0(4),
|
||||
.gpio_en = -1, /* Not controllable, set "Always High" */
|
||||
.default_mode = 0, /* vid0 = 0, vid1 = 0 */
|
||||
.dvs_mode = { 48, 32, 28, 18 }, /* 1.25, 1.20, 1.05, 0.95V */
|
||||
.sync_freq = 0, /* default: fastest */
|
||||
.ramp_speed = 0, /* default: fastest */
|
||||
|
||||
.reg_data = {
|
||||
.constraints = {
|
||||
.name = "VARM_1.2V",
|
||||
.min_uV = 770000,
|
||||
.max_uV = 1400000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &max8952_consumer,
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply lp3974_buck1_consumer =
|
||||
REGULATOR_SUPPLY("vddint", NULL);
|
||||
|
||||
static struct regulator_consumer_supply lp3974_buck2_consumer =
|
||||
REGULATOR_SUPPLY("vddg3d", NULL);
|
||||
|
||||
static struct regulator_init_data lp3974_buck1_data = {
|
||||
.constraints = {
|
||||
.name = "VINT_1.1V",
|
||||
.min_uV = 750000,
|
||||
.max_uV = 1500000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.boot_on = 1,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &lp3974_buck1_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_buck2_data = {
|
||||
.constraints = {
|
||||
.name = "VG3D_1.1V",
|
||||
.min_uV = 750000,
|
||||
.max_uV = 1500000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.boot_on = 1,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &lp3974_buck2_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_buck3_data = {
|
||||
.constraints = {
|
||||
.name = "VCC_1.8V",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_buck4_data = {
|
||||
.constraints = {
|
||||
.name = "VMEM_1.2V",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.apply_uV = 1,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo2_data = {
|
||||
.constraints = {
|
||||
.name = "VALIVE_1.2V",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo3_data = {
|
||||
.constraints = {
|
||||
.name = "VUSB+MIPI_1.1V",
|
||||
.min_uV = 1100000,
|
||||
.max_uV = 1100000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo4_data = {
|
||||
.constraints = {
|
||||
.name = "VADC_3.3V",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo5_data = {
|
||||
.constraints = {
|
||||
.name = "VTF_2.8V",
|
||||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo6_data = {
|
||||
.constraints = {
|
||||
.name = "LDO6",
|
||||
.min_uV = 2000000,
|
||||
.max_uV = 2000000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo7_data = {
|
||||
.constraints = {
|
||||
.name = "VLCD+VMIPI_1.8V",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo8_data = {
|
||||
.constraints = {
|
||||
.name = "VUSB+VDAC_3.3V",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo9_data = {
|
||||
.constraints = {
|
||||
.name = "VCC_2.8V",
|
||||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo10_data = {
|
||||
.constraints = {
|
||||
.name = "VPLL_1.1V",
|
||||
.min_uV = 1100000,
|
||||
.max_uV = 1100000,
|
||||
.boot_on = 1,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo11_data = {
|
||||
.constraints = {
|
||||
.name = "CAM_AF_3.3V",
|
||||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo12_data = {
|
||||
.constraints = {
|
||||
.name = "PS_2.8V",
|
||||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo13_data = {
|
||||
.constraints = {
|
||||
.name = "VHIC_1.2V",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo14_data = {
|
||||
.constraints = {
|
||||
.name = "CAM_I_HOST_1.8V",
|
||||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo15_data = {
|
||||
.constraints = {
|
||||
.name = "CAM_S_DIG+FM33_CORE_1.2V",
|
||||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo16_data = {
|
||||
.constraints = {
|
||||
.name = "CAM_S_ANA_2.8V",
|
||||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_ldo17_data = {
|
||||
.constraints = {
|
||||
.name = "VCC_3.0V_LCD",
|
||||
.min_uV = 3000000,
|
||||
.max_uV = 3000000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.boot_on = 1,
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_32khz_ap_data = {
|
||||
.constraints = {
|
||||
.name = "32KHz AP",
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_32khz_cp_data = {
|
||||
.constraints = {
|
||||
.name = "32KHz CP",
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_vichg_data = {
|
||||
.constraints = {
|
||||
.name = "VICHG",
|
||||
.state_mem = {
|
||||
.disabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_esafeout1_data = {
|
||||
.constraints = {
|
||||
.name = "SAFEOUT1",
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct regulator_init_data lp3974_esafeout2_data = {
|
||||
.constraints = {
|
||||
.name = "SAFEOUT2",
|
||||
.boot_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct max8998_regulator_data lp3974_regulators[] = {
|
||||
{ MAX8998_LDO2, &lp3974_ldo2_data },
|
||||
{ MAX8998_LDO3, &lp3974_ldo3_data },
|
||||
{ MAX8998_LDO4, &lp3974_ldo4_data },
|
||||
{ MAX8998_LDO5, &lp3974_ldo5_data },
|
||||
{ MAX8998_LDO6, &lp3974_ldo6_data },
|
||||
{ MAX8998_LDO7, &lp3974_ldo7_data },
|
||||
{ MAX8998_LDO8, &lp3974_ldo8_data },
|
||||
{ MAX8998_LDO9, &lp3974_ldo9_data },
|
||||
{ MAX8998_LDO10, &lp3974_ldo10_data },
|
||||
{ MAX8998_LDO11, &lp3974_ldo11_data },
|
||||
{ MAX8998_LDO12, &lp3974_ldo12_data },
|
||||
{ MAX8998_LDO13, &lp3974_ldo13_data },
|
||||
{ MAX8998_LDO14, &lp3974_ldo14_data },
|
||||
{ MAX8998_LDO15, &lp3974_ldo15_data },
|
||||
{ MAX8998_LDO16, &lp3974_ldo16_data },
|
||||
{ MAX8998_LDO17, &lp3974_ldo17_data },
|
||||
{ MAX8998_BUCK1, &lp3974_buck1_data },
|
||||
{ MAX8998_BUCK2, &lp3974_buck2_data },
|
||||
{ MAX8998_BUCK3, &lp3974_buck3_data },
|
||||
{ MAX8998_BUCK4, &lp3974_buck4_data },
|
||||
{ MAX8998_EN32KHZ_AP, &lp3974_32khz_ap_data },
|
||||
{ MAX8998_EN32KHZ_CP, &lp3974_32khz_cp_data },
|
||||
{ MAX8998_ENVICHG, &lp3974_vichg_data },
|
||||
{ MAX8998_ESAFEOUT1, &lp3974_esafeout1_data },
|
||||
{ MAX8998_ESAFEOUT2, &lp3974_esafeout2_data },
|
||||
};
|
||||
|
||||
static struct max8998_platform_data universal_lp3974_pdata = {
|
||||
.num_regulators = ARRAY_SIZE(lp3974_regulators),
|
||||
.regulators = lp3974_regulators,
|
||||
.buck1_voltage1 = 1100000, /* INT */
|
||||
.buck1_voltage2 = 1000000,
|
||||
.buck1_voltage3 = 1100000,
|
||||
.buck1_voltage4 = 1000000,
|
||||
.buck1_set1 = EXYNOS4_GPX0(5),
|
||||
.buck1_set2 = EXYNOS4_GPX0(6),
|
||||
.buck2_voltage1 = 1200000, /* G3D */
|
||||
.buck2_voltage2 = 1100000,
|
||||
.buck1_default_idx = 0,
|
||||
.buck2_set3 = EXYNOS4_GPE2(0),
|
||||
.buck2_default_idx = 0,
|
||||
.wakeup = true,
|
||||
};
|
||||
|
||||
/* GPIO I2C 5 (PMIC) */
|
||||
static struct i2c_board_info i2c5_devs[] __initdata = {
|
||||
{
|
||||
I2C_BOARD_INFO("max8952", 0xC0 >> 1),
|
||||
.platform_data = &universal_max8952_pdata,
|
||||
}, {
|
||||
I2C_BOARD_INFO("lp3974", 0xCC >> 1),
|
||||
.platform_data = &universal_lp3974_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
/* GPIO KEYS */
|
||||
static struct gpio_keys_button universal_gpio_keys_tables[] = {
|
||||
{
|
||||
.code = KEY_VOLUMEUP,
|
||||
.gpio = EXYNOS4_GPX2(0), /* XEINT16 */
|
||||
.desc = "gpio-keys: KEY_VOLUMEUP",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_VOLUMEDOWN,
|
||||
.gpio = EXYNOS4_GPX2(1), /* XEINT17 */
|
||||
.desc = "gpio-keys: KEY_VOLUMEDOWN",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_CONFIG,
|
||||
.gpio = EXYNOS4_GPX2(2), /* XEINT18 */
|
||||
.desc = "gpio-keys: KEY_CONFIG",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_CAMERA,
|
||||
.gpio = EXYNOS4_GPX2(3), /* XEINT19 */
|
||||
.desc = "gpio-keys: KEY_CAMERA",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_OK,
|
||||
.gpio = EXYNOS4_GPX3(5), /* XEINT29 */
|
||||
.desc = "gpio-keys: KEY_OK",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data universal_gpio_keys_data = {
|
||||
.buttons = universal_gpio_keys_tables,
|
||||
.nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
|
||||
};
|
||||
|
||||
static struct platform_device universal_gpio_keys = {
|
||||
.name = "gpio-keys",
|
||||
.dev = {
|
||||
.platform_data = &universal_gpio_keys_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
|
||||
.max_width = 8,
|
||||
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_DISABLE),
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply mmc0_supplies[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data mmc0_fixed_voltage_init_data = {
|
||||
.constraints = {
|
||||
.name = "VMEM_VDD_2.8V",
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
|
||||
.consumer_supplies = mmc0_supplies,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config mmc0_fixed_voltage_config = {
|
||||
.supply_name = "MASSMEMORY_EN",
|
||||
.microvolts = 2800000,
|
||||
.gpio = EXYNOS4_GPE1(3),
|
||||
.enable_high = true,
|
||||
.init_data = &mmc0_fixed_voltage_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device mmc0_fixed_voltage = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &mmc0_fixed_voltage_config,
|
||||
},
|
||||
};
|
||||
|
||||
/* SD */
|
||||
static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
|
||||
.max_width = 4,
|
||||
.host_caps = MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_DISABLE,
|
||||
.ext_cd_gpio = EXYNOS4_GPX3(4), /* XEINT_28 */
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
/* WiFi */
|
||||
static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
|
||||
.max_width = 4,
|
||||
.host_caps = MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_DISABLE,
|
||||
.cd_type = S3C_SDHCI_CD_EXTERNAL,
|
||||
};
|
||||
|
||||
static void __init universal_sdhci_init(void)
|
||||
{
|
||||
s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
|
||||
s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
|
||||
s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
|
||||
}
|
||||
|
||||
/* I2C0 */
|
||||
static struct i2c_board_info i2c0_devs[] __initdata = {
|
||||
/* Camera, To be updated */
|
||||
};
|
||||
|
||||
/* I2C1 */
|
||||
static struct i2c_board_info i2c1_devs[] __initdata = {
|
||||
/* Gyro, To be updated */
|
||||
};
|
||||
|
||||
static struct platform_device *universal_devices[] __initdata = {
|
||||
/* Samsung Platform Devices */
|
||||
&mmc0_fixed_voltage,
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
&s3c_device_i2c5,
|
||||
|
||||
/* Universal Devices */
|
||||
&universal_gpio_keys,
|
||||
&s5p_device_onenand,
|
||||
};
|
||||
|
||||
static void __init universal_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init universal_machine_init(void)
|
||||
{
|
||||
universal_sdhci_init();
|
||||
|
||||
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
|
||||
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
|
||||
|
||||
s3c_i2c5_set_platdata(NULL);
|
||||
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
|
||||
|
||||
/* Last */
|
||||
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
|
||||
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
|
||||
.boot_params = S5P_PA_SDRAM + 0x100,
|
||||
.init_irq = exynos4_init_irq,
|
||||
.map_io = universal_map_io,
|
||||
.init_machine = universal_machine_init,
|
||||
.timer = &exynos4_timer,
|
||||
MACHINE_END
|
421
arch/arm/mach-exynos4/mct.c
Normal file
421
arch/arm/mach-exynos4/mct.c
Normal file
|
@ -0,0 +1,421 @@
|
|||
/* linux/arch/arm/mach-exynos4/mct.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4 MCT(Multi-Core Timer) support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/sched.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clockchips.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/percpu.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-mct.h>
|
||||
#include <asm/mach/time.h>
|
||||
|
||||
static unsigned long clk_cnt_per_tick;
|
||||
static unsigned long clk_rate;
|
||||
|
||||
struct mct_clock_event_device {
|
||||
struct clock_event_device *evt;
|
||||
void __iomem *base;
|
||||
};
|
||||
|
||||
struct mct_clock_event_device mct_tick[2];
|
||||
|
||||
static void exynos4_mct_write(unsigned int value, void *addr)
|
||||
{
|
||||
void __iomem *stat_addr;
|
||||
u32 mask;
|
||||
u32 i;
|
||||
|
||||
__raw_writel(value, addr);
|
||||
|
||||
switch ((u32) addr) {
|
||||
case (u32) EXYNOS4_MCT_G_TCON:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 16; /* G_TCON write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_COMP0_L:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 0; /* G_COMP0_L write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_COMP0_U:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 1; /* G_COMP0_U write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_COMP0_ADD_INCR:
|
||||
stat_addr = EXYNOS4_MCT_G_WSTAT;
|
||||
mask = 1 << 2; /* G_COMP0_ADD_INCR write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_CNT_L:
|
||||
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
|
||||
mask = 1 << 0; /* G_CNT_L write status */
|
||||
break;
|
||||
case (u32) EXYNOS4_MCT_G_CNT_U:
|
||||
stat_addr = EXYNOS4_MCT_G_CNT_WSTAT;
|
||||
mask = 1 << 1; /* G_CNT_U write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCON_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 3; /* L0_TCON write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCON_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 3; /* L1_TCON write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_TCNTB_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 0; /* L0_TCNTB write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_TCNTB_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 0; /* L1_TCNTB write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L0_BASE + MCT_L_ICNTB_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L0_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 1; /* L0_ICNTB write status */
|
||||
break;
|
||||
case (u32)(EXYNOS4_MCT_L1_BASE + MCT_L_ICNTB_OFFSET):
|
||||
stat_addr = EXYNOS4_MCT_L1_BASE + MCT_L_WSTAT_OFFSET;
|
||||
mask = 1 << 1; /* L1_ICNTB write status */
|
||||
break;
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
/* Wait maximum 1 ms until written values are applied */
|
||||
for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++)
|
||||
if (__raw_readl(stat_addr) & mask) {
|
||||
__raw_writel(mask, stat_addr);
|
||||
return;
|
||||
}
|
||||
|
||||
panic("MCT hangs after writing %d (addr:0x%08x)\n", value, (u32)addr);
|
||||
}
|
||||
|
||||
/* Clocksource handling */
|
||||
static void exynos4_mct_frc_start(u32 hi, u32 lo)
|
||||
{
|
||||
u32 reg;
|
||||
|
||||
exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L);
|
||||
exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U);
|
||||
|
||||
reg = __raw_readl(EXYNOS4_MCT_G_TCON);
|
||||
reg |= MCT_G_TCON_START;
|
||||
exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON);
|
||||
}
|
||||
|
||||
static cycle_t exynos4_frc_read(struct clocksource *cs)
|
||||
{
|
||||
unsigned int lo, hi;
|
||||
u32 hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
|
||||
|
||||
do {
|
||||
hi = hi2;
|
||||
lo = __raw_readl(EXYNOS4_MCT_G_CNT_L);
|
||||
hi2 = __raw_readl(EXYNOS4_MCT_G_CNT_U);
|
||||
} while (hi != hi2);
|
||||
|
||||
return ((cycle_t)hi << 32) | lo;
|
||||
}
|
||||
|
||||
struct clocksource mct_frc = {
|
||||
.name = "mct-frc",
|
||||
.rating = 400,
|
||||
.read = exynos4_frc_read,
|
||||
.mask = CLOCKSOURCE_MASK(64),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static void __init exynos4_clocksource_init(void)
|
||||
{
|
||||
exynos4_mct_frc_start(0, 0);
|
||||
|
||||
if (clocksource_register_hz(&mct_frc, clk_rate))
|
||||
panic("%s: can't register clocksource\n", mct_frc.name);
|
||||
}
|
||||
|
||||
static void exynos4_mct_comp0_stop(void)
|
||||
{
|
||||
unsigned int tcon;
|
||||
|
||||
tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
|
||||
tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC);
|
||||
|
||||
exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON);
|
||||
exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB);
|
||||
}
|
||||
|
||||
static void exynos4_mct_comp0_start(enum clock_event_mode mode,
|
||||
unsigned long cycles)
|
||||
{
|
||||
unsigned int tcon;
|
||||
cycle_t comp_cycle;
|
||||
|
||||
tcon = __raw_readl(EXYNOS4_MCT_G_TCON);
|
||||
|
||||
if (mode == CLOCK_EVT_MODE_PERIODIC) {
|
||||
tcon |= MCT_G_TCON_COMP0_AUTO_INC;
|
||||
exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR);
|
||||
}
|
||||
|
||||
comp_cycle = exynos4_frc_read(&mct_frc) + cycles;
|
||||
exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L);
|
||||
exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U);
|
||||
|
||||
exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB);
|
||||
|
||||
tcon |= MCT_G_TCON_COMP0_ENABLE;
|
||||
exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON);
|
||||
}
|
||||
|
||||
static int exynos4_comp_set_next_event(unsigned long cycles,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
exynos4_mct_comp0_start(evt->mode, cycles);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void exynos4_comp_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
exynos4_mct_comp0_stop();
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
exynos4_mct_comp0_start(mode, clk_cnt_per_tick);
|
||||
break;
|
||||
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
case CLOCK_EVT_MODE_RESUME:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static struct clock_event_device mct_comp_device = {
|
||||
.name = "mct-comp",
|
||||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.rating = 250,
|
||||
.set_next_event = exynos4_comp_set_next_event,
|
||||
.set_mode = exynos4_comp_set_mode,
|
||||
};
|
||||
|
||||
static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = dev_id;
|
||||
|
||||
exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT);
|
||||
|
||||
evt->event_handler(evt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction mct_comp_event_irq = {
|
||||
.name = "mct_comp_irq",
|
||||
.flags = IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = exynos4_mct_comp_isr,
|
||||
.dev_id = &mct_comp_device,
|
||||
};
|
||||
|
||||
static void exynos4_clockevent_init(void)
|
||||
{
|
||||
clk_cnt_per_tick = clk_rate / 2 / HZ;
|
||||
|
||||
clockevents_calc_mult_shift(&mct_comp_device, clk_rate / 2, 5);
|
||||
mct_comp_device.max_delta_ns =
|
||||
clockevent_delta2ns(0xffffffff, &mct_comp_device);
|
||||
mct_comp_device.min_delta_ns =
|
||||
clockevent_delta2ns(0xf, &mct_comp_device);
|
||||
mct_comp_device.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&mct_comp_device);
|
||||
|
||||
setup_irq(IRQ_MCT_G0, &mct_comp_event_irq);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
/* Clock event handling */
|
||||
static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt)
|
||||
{
|
||||
unsigned long tmp;
|
||||
unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START;
|
||||
void __iomem *addr = mevt->base + MCT_L_TCON_OFFSET;
|
||||
|
||||
tmp = __raw_readl(addr);
|
||||
if (tmp & mask) {
|
||||
tmp &= ~mask;
|
||||
exynos4_mct_write(tmp, addr);
|
||||
}
|
||||
}
|
||||
|
||||
static void exynos4_mct_tick_start(unsigned long cycles,
|
||||
struct mct_clock_event_device *mevt)
|
||||
{
|
||||
unsigned long tmp;
|
||||
|
||||
exynos4_mct_tick_stop(mevt);
|
||||
|
||||
tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */
|
||||
|
||||
/* update interrupt count buffer */
|
||||
exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET);
|
||||
|
||||
/* enable MCT tick interupt */
|
||||
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET);
|
||||
|
||||
tmp = __raw_readl(mevt->base + MCT_L_TCON_OFFSET);
|
||||
tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START |
|
||||
MCT_L_TCON_INTERVAL_MODE;
|
||||
exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET);
|
||||
}
|
||||
|
||||
static int exynos4_tick_set_next_event(unsigned long cycles,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
|
||||
|
||||
exynos4_mct_tick_start(cycles, mevt);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static inline void exynos4_tick_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
struct mct_clock_event_device *mevt = &mct_tick[smp_processor_id()];
|
||||
|
||||
exynos4_mct_tick_stop(mevt);
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
exynos4_mct_tick_start(clk_cnt_per_tick, mevt);
|
||||
break;
|
||||
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
case CLOCK_EVT_MODE_UNUSED:
|
||||
case CLOCK_EVT_MODE_SHUTDOWN:
|
||||
case CLOCK_EVT_MODE_RESUME:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct mct_clock_event_device *mevt = dev_id;
|
||||
struct clock_event_device *evt = mevt->evt;
|
||||
|
||||
/*
|
||||
* This is for supporting oneshot mode.
|
||||
* Mct would generate interrupt periodically
|
||||
* without explicit stopping.
|
||||
*/
|
||||
if (evt->mode != CLOCK_EVT_MODE_PERIODIC)
|
||||
exynos4_mct_tick_stop(mevt);
|
||||
|
||||
/* Clear the MCT tick interrupt */
|
||||
exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET);
|
||||
|
||||
evt->event_handler(evt);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction mct_tick0_event_irq = {
|
||||
.name = "mct_tick0_irq",
|
||||
.flags = IRQF_TIMER | IRQF_NOBALANCING,
|
||||
.handler = exynos4_mct_tick_isr,
|
||||
};
|
||||
|
||||
static struct irqaction mct_tick1_event_irq = {
|
||||
.name = "mct_tick1_irq",
|
||||
.flags = IRQF_TIMER | IRQF_NOBALANCING,
|
||||
.handler = exynos4_mct_tick_isr,
|
||||
};
|
||||
|
||||
static void exynos4_mct_tick_init(struct clock_event_device *evt)
|
||||
{
|
||||
unsigned int cpu = smp_processor_id();
|
||||
|
||||
mct_tick[cpu].evt = evt;
|
||||
|
||||
if (cpu == 0) {
|
||||
mct_tick[cpu].base = EXYNOS4_MCT_L0_BASE;
|
||||
evt->name = "mct_tick0";
|
||||
} else {
|
||||
mct_tick[cpu].base = EXYNOS4_MCT_L1_BASE;
|
||||
evt->name = "mct_tick1";
|
||||
}
|
||||
|
||||
evt->cpumask = cpumask_of(cpu);
|
||||
evt->set_next_event = exynos4_tick_set_next_event;
|
||||
evt->set_mode = exynos4_tick_set_mode;
|
||||
evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
|
||||
evt->rating = 450;
|
||||
|
||||
clockevents_calc_mult_shift(evt, clk_rate / 2, 5);
|
||||
evt->max_delta_ns =
|
||||
clockevent_delta2ns(0x7fffffff, evt);
|
||||
evt->min_delta_ns =
|
||||
clockevent_delta2ns(0xf, evt);
|
||||
|
||||
clockevents_register_device(evt);
|
||||
|
||||
exynos4_mct_write(0x1, mct_tick[cpu].base + MCT_L_TCNTB_OFFSET);
|
||||
|
||||
if (cpu == 0) {
|
||||
mct_tick0_event_irq.dev_id = &mct_tick[cpu];
|
||||
setup_irq(IRQ_MCT_L0, &mct_tick0_event_irq);
|
||||
} else {
|
||||
mct_tick1_event_irq.dev_id = &mct_tick[cpu];
|
||||
irq_set_affinity(IRQ_MCT1, cpumask_of(1));
|
||||
setup_irq(IRQ_MCT_L1, &mct_tick1_event_irq);
|
||||
}
|
||||
}
|
||||
|
||||
/* Setup the local clock events for a CPU */
|
||||
void __cpuinit local_timer_setup(struct clock_event_device *evt)
|
||||
{
|
||||
exynos4_mct_tick_init(evt);
|
||||
}
|
||||
|
||||
int local_timer_ack(void)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_LOCAL_TIMERS */
|
||||
|
||||
static void __init exynos4_timer_resources(void)
|
||||
{
|
||||
struct clk *mct_clk;
|
||||
mct_clk = clk_get(NULL, "xtal");
|
||||
|
||||
clk_rate = clk_get_rate(mct_clk);
|
||||
}
|
||||
|
||||
static void __init exynos4_timer_init(void)
|
||||
{
|
||||
exynos4_timer_resources();
|
||||
exynos4_clocksource_init();
|
||||
exynos4_clockevent_init();
|
||||
}
|
||||
|
||||
struct sys_timer exynos4_timer = {
|
||||
.init = exynos4_timer_init,
|
||||
};
|
|
@ -1,7 +1,7 @@
|
|||
/* linux/arch/arm/mach-s5pv310/platsmp.c
|
||||
/* linux/arch/arm/mach-exynos4/platsmp.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* Cloned from linux/arch/arm/mach-vexpress/platsmp.c
|
||||
*
|
||||
|
@ -28,7 +28,7 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/regs-clock.h>
|
||||
|
||||
extern void s5pv310_secondary_startup(void);
|
||||
extern void exynos4_secondary_startup(void);
|
||||
|
||||
/*
|
||||
* control for which core is the next to come out of the secondary
|
||||
|
@ -139,7 +139,7 @@ void __init smp_init_cpus(void)
|
|||
/* sanity check */
|
||||
if (ncores > NR_CPUS) {
|
||||
printk(KERN_WARNING
|
||||
"S5PV310: no. of cores (%d) greater than configured "
|
||||
"EXYNOS4: no. of cores (%d) greater than configured "
|
||||
"maximum of %d - clipping\n",
|
||||
ncores, NR_CPUS);
|
||||
ncores = NR_CPUS;
|
||||
|
@ -168,5 +168,5 @@ void __init platform_smp_prepare_cpus(unsigned int max_cpus)
|
|||
* until it receives a soft interrupt, and then the
|
||||
* secondary CPU branches to this address.
|
||||
*/
|
||||
__raw_writel(BSYM(virt_to_phys(s5pv310_secondary_startup)), S5P_VA_SYSRAM);
|
||||
__raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)), S5P_VA_SYSRAM);
|
||||
}
|
420
arch/arm/mach-exynos4/pm.c
Normal file
420
arch/arm/mach-exynos4/pm.c
Normal file
|
@ -0,0 +1,420 @@
|
|||
/* linux/arch/arm/mach-exynos4/pm.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 - Power Management support
|
||||
*
|
||||
* Based on arch/arm/mach-s3c2410/pm.c
|
||||
* Copyright (c) 2006 Simtec Electronics
|
||||
* Ben Dooks <ben@simtec.co.uk>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/init.h>
|
||||
#include <linux/suspend.h>
|
||||
#include <linux/io.h>
|
||||
|
||||
#include <asm/cacheflush.h>
|
||||
#include <asm/hardware/cache-l2x0.h>
|
||||
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/pm.h>
|
||||
|
||||
#include <mach/regs-irq.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/regs-pmu.h>
|
||||
#include <mach/pm-core.h>
|
||||
|
||||
static struct sleep_save exynos4_sleep[] = {
|
||||
{ .reg = S5P_ARM_CORE0_LOWPWR , .val = 0x2, },
|
||||
{ .reg = S5P_DIS_IRQ_CORE0 , .val = 0x0, },
|
||||
{ .reg = S5P_DIS_IRQ_CENTRAL0 , .val = 0x0, },
|
||||
{ .reg = S5P_ARM_CORE1_LOWPWR , .val = 0x2, },
|
||||
{ .reg = S5P_DIS_IRQ_CORE1 , .val = 0x0, },
|
||||
{ .reg = S5P_DIS_IRQ_CENTRAL1 , .val = 0x0, },
|
||||
{ .reg = S5P_ARM_COMMON_LOWPWR , .val = 0x2, },
|
||||
{ .reg = S5P_L2_0_LOWPWR , .val = 0x3, },
|
||||
{ .reg = S5P_L2_1_LOWPWR , .val = 0x3, },
|
||||
{ .reg = S5P_CMU_ACLKSTOP_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_SCLKSTOP_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_APLL_SYSCLK_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_MPLL_SYSCLK_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_VPLL_SYSCLK_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_EPLL_SYSCLK_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_CLKSTOP_GPS_ALIVE_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_GPSALIVE_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_CLKSTOP_CAM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_CLKSTOP_TV_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_CLKSTOP_MFC_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_CLKSTOP_G3D_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_CLKSTOP_LCD0_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_CLKSTOP_LCD1_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_CLKSTOP_MAUDIO_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_CLKSTOP_GPS_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_CAM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_TV_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_MFC_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_G3D_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_LCD0_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_LCD1_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_MAUDIO_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CMU_RESET_GPS_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_TOP_BUS_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_TOP_RETENTION_LOWPWR , .val = 0x1, },
|
||||
{ .reg = S5P_TOP_PWR_LOWPWR , .val = 0x3, },
|
||||
{ .reg = S5P_LOGIC_RESET_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_ONENAND_MEM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_MODIMIF_MEM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_G2D_ACP_MEM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_USBOTG_MEM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_HSMMC_MEM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CSSYS_MEM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_SECSS_MEM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PCIE_MEM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_SATA_MEM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_DRAM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_MAUDIO_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_GPIO_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_UART_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_MMCA_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_MMCB_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_EBIA_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_EBIB_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_ISOLATION_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_PAD_RETENTION_ALV_SEL_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_XUSBXTI_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_XXTI_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_EXT_REGULATOR_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_GPIO_MODE_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_GPIO_MODE_MAUDIO_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_CAM_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_TV_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_MFC_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_G3D_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_LCD0_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_LCD1_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_MAUDIO_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_GPS_LOWPWR , .val = 0x0, },
|
||||
{ .reg = S5P_GPS_ALIVE_LOWPWR , .val = 0x0, },
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4_set_clksrc[] = {
|
||||
{ .reg = S5P_CLKSRC_MASK_TOP , .val = 0x00000001, },
|
||||
{ .reg = S5P_CLKSRC_MASK_CAM , .val = 0x11111111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_TV , .val = 0x00000111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_LCD0 , .val = 0x00001111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_LCD1 , .val = 0x00001111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_MAUDIO , .val = 0x00000001, },
|
||||
{ .reg = S5P_CLKSRC_MASK_FSYS , .val = 0x01011111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_PERIL0 , .val = 0x01111111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_PERIL1 , .val = 0x01110111, },
|
||||
{ .reg = S5P_CLKSRC_MASK_DMC , .val = 0x00010000, },
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4_core_save[] = {
|
||||
/* CMU side */
|
||||
SAVE_ITEM(S5P_CLKDIV_LEFTBUS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LEFTBUS),
|
||||
SAVE_ITEM(S5P_CLKDIV_RIGHTBUS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_RIGHTBUS),
|
||||
SAVE_ITEM(S5P_EPLL_CON0),
|
||||
SAVE_ITEM(S5P_EPLL_CON1),
|
||||
SAVE_ITEM(S5P_VPLL_CON0),
|
||||
SAVE_ITEM(S5P_VPLL_CON1),
|
||||
SAVE_ITEM(S5P_CLKSRC_TOP0),
|
||||
SAVE_ITEM(S5P_CLKSRC_TOP1),
|
||||
SAVE_ITEM(S5P_CLKSRC_CAM),
|
||||
SAVE_ITEM(S5P_CLKSRC_MFC),
|
||||
SAVE_ITEM(S5P_CLKSRC_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKSRC_LCD0),
|
||||
SAVE_ITEM(S5P_CLKSRC_LCD1),
|
||||
SAVE_ITEM(S5P_CLKSRC_MAUDIO),
|
||||
SAVE_ITEM(S5P_CLKSRC_FSYS),
|
||||
SAVE_ITEM(S5P_CLKSRC_PERIL0),
|
||||
SAVE_ITEM(S5P_CLKSRC_PERIL1),
|
||||
SAVE_ITEM(S5P_CLKDIV_CAM),
|
||||
SAVE_ITEM(S5P_CLKDIV_TV),
|
||||
SAVE_ITEM(S5P_CLKDIV_MFC),
|
||||
SAVE_ITEM(S5P_CLKDIV_G3D),
|
||||
SAVE_ITEM(S5P_CLKDIV_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKDIV_LCD0),
|
||||
SAVE_ITEM(S5P_CLKDIV_LCD1),
|
||||
SAVE_ITEM(S5P_CLKDIV_MAUDIO),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS0),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS1),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS2),
|
||||
SAVE_ITEM(S5P_CLKDIV_FSYS3),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL0),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL1),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL2),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL3),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL4),
|
||||
SAVE_ITEM(S5P_CLKDIV_PERIL5),
|
||||
SAVE_ITEM(S5P_CLKDIV_TOP),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_CAM),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_TV),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_LCD0),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_LCD1),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_MAUDIO),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_FSYS),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL0),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_PERIL1),
|
||||
SAVE_ITEM(S5P_CLKGATE_SCLKCAM),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_CAM),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_TV),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_MFC),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_G3D),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_IMAGE),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LCD0),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_LCD1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_FSYS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_GPS),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIL),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_PERIR),
|
||||
SAVE_ITEM(S5P_CLKGATE_BLOCK),
|
||||
SAVE_ITEM(S5P_CLKSRC_MASK_DMC),
|
||||
SAVE_ITEM(S5P_CLKSRC_DMC),
|
||||
SAVE_ITEM(S5P_CLKDIV_DMC0),
|
||||
SAVE_ITEM(S5P_CLKDIV_DMC1),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_DMC),
|
||||
SAVE_ITEM(S5P_CLKSRC_CPU),
|
||||
SAVE_ITEM(S5P_CLKDIV_CPU),
|
||||
SAVE_ITEM(S5P_CLKGATE_SCLKCPU),
|
||||
SAVE_ITEM(S5P_CLKGATE_IP_CPU),
|
||||
/* GIC side */
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x000),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x004),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x008),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x00C),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x014),
|
||||
SAVE_ITEM(S5P_VA_GIC_CPU + 0x018),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x000),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x004),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x100),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x104),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x108),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x300),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x304),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x308),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x400),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x404),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x408),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x40C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x410),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x414),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x418),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x41C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x420),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x424),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x428),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x42C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x430),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x434),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x438),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x43C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x440),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x444),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x448),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x44C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x450),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x454),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x458),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x45C),
|
||||
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x800),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x804),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x808),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x80C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x810),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x814),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x818),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x81C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x820),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x824),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x828),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x82C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x830),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x834),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x838),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x83C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x840),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x844),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x848),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x84C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x850),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x854),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x858),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0x85C),
|
||||
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC00),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC04),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC08),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC0C),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC10),
|
||||
SAVE_ITEM(S5P_VA_GIC_DIST + 0xC14),
|
||||
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x000),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x010),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x020),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x030),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x040),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x050),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x060),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x070),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x080),
|
||||
SAVE_ITEM(S5P_VA_COMBINER_BASE + 0x090),
|
||||
};
|
||||
|
||||
static struct sleep_save exynos4_l2cc_save[] = {
|
||||
SAVE_ITEM(S5P_VA_L2CC + L2X0_TAG_LATENCY_CTRL),
|
||||
SAVE_ITEM(S5P_VA_L2CC + L2X0_DATA_LATENCY_CTRL),
|
||||
SAVE_ITEM(S5P_VA_L2CC + L2X0_PREFETCH_CTRL),
|
||||
SAVE_ITEM(S5P_VA_L2CC + L2X0_POWER_CTRL),
|
||||
SAVE_ITEM(S5P_VA_L2CC + L2X0_AUX_CTRL),
|
||||
};
|
||||
|
||||
void exynos4_cpu_suspend(void)
|
||||
{
|
||||
unsigned long tmp;
|
||||
unsigned long mask = 0xFFFFFFFF;
|
||||
|
||||
/* Setting Central Sequence Register for power down mode */
|
||||
|
||||
tmp = __raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
|
||||
tmp &= ~(S5P_CENTRAL_LOWPWR_CFG);
|
||||
__raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
|
||||
|
||||
/* Setting Central Sequence option Register */
|
||||
|
||||
tmp = __raw_readl(S5P_CENTRAL_SEQ_OPTION);
|
||||
tmp &= ~(S5P_USE_MASK);
|
||||
tmp |= S5P_USE_STANDBY_WFI0;
|
||||
__raw_writel(tmp, S5P_CENTRAL_SEQ_OPTION);
|
||||
|
||||
/* Clear all interrupt pending to avoid early wakeup */
|
||||
|
||||
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x280));
|
||||
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x284));
|
||||
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x288));
|
||||
|
||||
/* Disable all interrupt */
|
||||
|
||||
__raw_writel(0x0, (S5P_VA_GIC_CPU + 0x000));
|
||||
__raw_writel(0x0, (S5P_VA_GIC_DIST + 0x000));
|
||||
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x184));
|
||||
__raw_writel(mask, (S5P_VA_GIC_DIST + 0x188));
|
||||
|
||||
outer_flush_all();
|
||||
|
||||
/* issue the standby signal into the pm unit. */
|
||||
cpu_do_idle();
|
||||
|
||||
/* we should never get past here */
|
||||
panic("sleep resumed to originator?");
|
||||
}
|
||||
|
||||
static void exynos4_pm_prepare(void)
|
||||
{
|
||||
u32 tmp;
|
||||
|
||||
s3c_pm_do_save(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
|
||||
s3c_pm_do_save(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
|
||||
|
||||
tmp = __raw_readl(S5P_INFORM1);
|
||||
|
||||
/* Set value of power down register for sleep mode */
|
||||
|
||||
s3c_pm_do_restore_core(exynos4_sleep, ARRAY_SIZE(exynos4_sleep));
|
||||
__raw_writel(S5P_CHECK_SLEEP, S5P_INFORM1);
|
||||
|
||||
/* ensure at least INFORM0 has the resume address */
|
||||
|
||||
__raw_writel(virt_to_phys(s3c_cpu_resume), S5P_INFORM0);
|
||||
|
||||
/* Before enter central sequence mode, clock src register have to set */
|
||||
|
||||
s3c_pm_do_restore_core(exynos4_set_clksrc, ARRAY_SIZE(exynos4_set_clksrc));
|
||||
|
||||
}
|
||||
|
||||
static int exynos4_pm_add(struct sys_device *sysdev)
|
||||
{
|
||||
pm_cpu_prep = exynos4_pm_prepare;
|
||||
pm_cpu_sleep = exynos4_cpu_suspend;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This function copy from linux/arch/arm/kernel/smp_scu.c */
|
||||
|
||||
void exynos4_scu_enable(void __iomem *scu_base)
|
||||
{
|
||||
u32 scu_ctrl;
|
||||
|
||||
scu_ctrl = __raw_readl(scu_base);
|
||||
/* already enabled? */
|
||||
if (scu_ctrl & 1)
|
||||
return;
|
||||
|
||||
scu_ctrl |= 1;
|
||||
__raw_writel(scu_ctrl, scu_base);
|
||||
|
||||
/*
|
||||
* Ensure that the data accessed by CPU0 before the SCU was
|
||||
* initialised is visible to the other CPUs.
|
||||
*/
|
||||
flush_cache_all();
|
||||
}
|
||||
|
||||
static int exynos4_pm_resume(struct sys_device *dev)
|
||||
{
|
||||
/* For release retention */
|
||||
|
||||
__raw_writel((1 << 28), S5P_PAD_RET_MAUDIO_OPTION);
|
||||
__raw_writel((1 << 28), S5P_PAD_RET_GPIO_OPTION);
|
||||
__raw_writel((1 << 28), S5P_PAD_RET_UART_OPTION);
|
||||
__raw_writel((1 << 28), S5P_PAD_RET_MMCA_OPTION);
|
||||
__raw_writel((1 << 28), S5P_PAD_RET_MMCB_OPTION);
|
||||
__raw_writel((1 << 28), S5P_PAD_RET_EBIA_OPTION);
|
||||
__raw_writel((1 << 28), S5P_PAD_RET_EBIB_OPTION);
|
||||
|
||||
s3c_pm_do_restore_core(exynos4_core_save, ARRAY_SIZE(exynos4_core_save));
|
||||
|
||||
exynos4_scu_enable(S5P_VA_SCU);
|
||||
|
||||
#ifdef CONFIG_CACHE_L2X0
|
||||
s3c_pm_do_restore_core(exynos4_l2cc_save, ARRAY_SIZE(exynos4_l2cc_save));
|
||||
outer_inv_all();
|
||||
/* enable L2X0*/
|
||||
writel_relaxed(1, S5P_VA_L2CC + L2X0_CTRL);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct sysdev_driver exynos4_pm_driver = {
|
||||
.add = exynos4_pm_add,
|
||||
.resume = exynos4_pm_resume,
|
||||
};
|
||||
|
||||
static __init int exynos4_pm_drvinit(void)
|
||||
{
|
||||
unsigned int tmp;
|
||||
|
||||
s3c_pm_init();
|
||||
|
||||
/* All wakeup disable */
|
||||
|
||||
tmp = __raw_readl(S5P_WAKEUP_MASK);
|
||||
tmp |= ((0xFF << 8) | (0x1F << 1));
|
||||
__raw_writel(tmp, S5P_WAKEUP_MASK);
|
||||
|
||||
return sysdev_driver_register(&exynos4_sysclass, &exynos4_pm_driver);
|
||||
}
|
||||
arch_initcall(exynos4_pm_drvinit);
|
44
arch/arm/mach-exynos4/setup-fimc.c
Normal file
44
arch/arm/mach-exynos4/setup-fimc.c
Normal file
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* Exynos4 camera interface GPIO configuration.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/camport.h>
|
||||
|
||||
int exynos4_fimc_setup_gpio(enum s5p_camport_id id)
|
||||
{
|
||||
u32 gpio8, gpio5;
|
||||
u32 sfn;
|
||||
int ret;
|
||||
|
||||
switch (id) {
|
||||
case S5P_CAMPORT_A:
|
||||
gpio8 = EXYNOS4_GPJ0(0); /* PCLK, VSYNC, HREF, DATA[0:4] */
|
||||
gpio5 = EXYNOS4_GPJ1(0); /* DATA[5:7], CLKOUT, FIELD */
|
||||
sfn = S3C_GPIO_SFN(2);
|
||||
break;
|
||||
|
||||
case S5P_CAMPORT_B:
|
||||
gpio8 = EXYNOS4_GPE0(0); /* DATA[0:7] */
|
||||
gpio5 = EXYNOS4_GPE1(0); /* PCLK, VSYNC, HREF, CLKOUT, FIELD */
|
||||
sfn = S3C_GPIO_SFN(3);
|
||||
break;
|
||||
|
||||
default:
|
||||
WARN(1, "Wrong camport id: %d\n", id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = s3c_gpio_cfgall_range(gpio8, 8, sfn, S3C_GPIO_PULL_UP);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return s3c_gpio_cfgall_range(gpio5, 5, sfn, S3C_GPIO_PULL_UP);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s5pv310/setup-i2c0.c
|
||||
* linux/arch/arm/mach-exynos4/setup-i2c0.c
|
||||
*
|
||||
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
|
@ -21,6 +21,6 @@ struct platform_device; /* don't need the contents */
|
|||
|
||||
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgall_range(S5PV310_GPD1(0), 2,
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPD1(0), 2,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s5pv310/setup-i2c1.c
|
||||
* linux/arch/arm/mach-exynos4/setup-i2c1.c
|
||||
*
|
||||
* Copyright (C) 2010 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
|
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
|
|||
|
||||
void s3c_i2c1_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgall_range(S5PV310_GPD1(2), 2,
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPD1(2), 2,
|
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s5pv310/setup-i2c2.c
|
||||
* linux/arch/arm/mach-exynos4/setup-i2c2.c
|
||||
*
|
||||
* Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
|
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
|
|||
|
||||
void s3c_i2c2_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgall_range(S5PV310_GPA0(6), 2,
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPA0(6), 2,
|
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s5pv310/setup-i2c3.c
|
||||
* linux/arch/arm/mach-exynos4/setup-i2c3.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
|
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
|
|||
|
||||
void s3c_i2c3_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgall_range(S5PV310_GPA1(2), 2,
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPA1(2), 2,
|
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s5pv310/setup-i2c4.c
|
||||
* linux/arch/arm/mach-exynos4/setup-i2c4.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
|
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
|
|||
|
||||
void s3c_i2c4_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgall_range(S5PV310_GPB(2), 2,
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPB(2), 2,
|
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s5pv310/setup-i2c5.c
|
||||
* linux/arch/arm/mach-exynos4/setup-i2c5.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
|
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
|
|||
|
||||
void s3c_i2c5_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgall_range(S5PV310_GPB(6), 2,
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPB(6), 2,
|
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s5pv310/setup-i2c6.c
|
||||
* linux/arch/arm/mach-exynos4/setup-i2c6.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
|
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
|
|||
|
||||
void s3c_i2c6_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgall_range(S5PV310_GPC1(3), 2,
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPC1(3), 2,
|
||||
S3C_GPIO_SFN(4), S3C_GPIO_PULL_UP);
|
||||
}
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* linux/arch/arm/mach-s5pv310/setup-i2c7.c
|
||||
* linux/arch/arm/mach-exynos4/setup-i2c7.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
|
@ -18,6 +18,6 @@ struct platform_device; /* don't need the contents */
|
|||
|
||||
void s3c_i2c7_cfg_gpio(struct platform_device *dev)
|
||||
{
|
||||
s3c_gpio_cfgall_range(S5PV310_GPD0(2), 2,
|
||||
s3c_gpio_cfgall_range(EXYNOS4_GPD0(2), 2,
|
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
|
||||
}
|
35
arch/arm/mach-exynos4/setup-keypad.c
Normal file
35
arch/arm/mach-exynos4/setup-keypad.c
Normal file
|
@ -0,0 +1,35 @@
|
|||
/* linux/arch/arm/mach-exynos4/setup-keypad.c
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* GPIO configuration for Exynos4 KeyPad device
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
||||
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
|
||||
{
|
||||
/* Keypads can be of various combinations, Just making sure */
|
||||
|
||||
if (rows > 8) {
|
||||
/* Set all the necessary GPX2 pins: KP_ROW[0~7] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), 8, S3C_GPIO_SFN(3));
|
||||
|
||||
/* Set all the necessary GPX3 pins: KP_ROW[8~] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX3(0), (rows - 8),
|
||||
S3C_GPIO_SFN(3));
|
||||
} else {
|
||||
/* Set all the necessary GPX2 pins: KP_ROW[x] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX2(0), rows,
|
||||
S3C_GPIO_SFN(3));
|
||||
}
|
||||
|
||||
/* Set all the necessary GPX1 pins to special-function 3: KP_COL[x] */
|
||||
s3c_gpio_cfgrange_nopull(EXYNOS4_GPX1(0), cols, S3C_GPIO_SFN(3));
|
||||
}
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/setup-sdhci-gpio.c
|
||||
/* linux/arch/arm/mach-exynos4/setup-sdhci-gpio.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
|
||||
* EXYNOS4 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -23,13 +23,13 @@
|
|||
#include <plat/regs-sdhci.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
||||
void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
|
||||
unsigned int gpio;
|
||||
|
||||
/* Set all the necessary GPK0[0:1] pins to special-function 2 */
|
||||
for (gpio = S5PV310_GPK0(0); gpio < S5PV310_GPK0(2); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK0(0); gpio < EXYNOS4_GPK0(2); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
|
@ -37,14 +37,14 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
|||
|
||||
switch (width) {
|
||||
case 8:
|
||||
for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
|
||||
/* Data pin GPK1[3:6] to special-funtion 3 */
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
case 4:
|
||||
for (gpio = S5PV310_GPK0(3); gpio <= S5PV310_GPK0(6); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK0(3); gpio <= EXYNOS4_GPK0(6); gpio++) {
|
||||
/* Data pin GPK0[3:6] to special-funtion 2 */
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
|
||||
|
@ -55,25 +55,25 @@ void s5pv310_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
|
|||
}
|
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
|
||||
s3c_gpio_cfgpin(S5PV310_GPK0(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PV310_GPK0(2), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPK0(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(EXYNOS4_GPK0(2), S3C_GPIO_PULL_UP);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
}
|
||||
|
||||
void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
|
||||
void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
|
||||
unsigned int gpio;
|
||||
|
||||
/* Set all the necessary GPK1[0:1] pins to special-function 2 */
|
||||
for (gpio = S5PV310_GPK1(0); gpio < S5PV310_GPK1(2); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK1(0); gpio < EXYNOS4_GPK1(2); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
|
||||
for (gpio = S5PV310_GPK1(3); gpio <= S5PV310_GPK1(6); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK1(3); gpio <= EXYNOS4_GPK1(6); gpio++) {
|
||||
/* Data pin GPK1[3:6] to special-function 2 */
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
|
||||
|
@ -81,19 +81,19 @@ void s5pv310_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
|
|||
}
|
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
|
||||
s3c_gpio_cfgpin(S5PV310_GPK1(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PV310_GPK1(2), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPK1(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(EXYNOS4_GPK1(2), S3C_GPIO_PULL_UP);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
}
|
||||
|
||||
void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
|
||||
void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
|
||||
unsigned int gpio;
|
||||
|
||||
/* Set all the necessary GPK2[0:1] pins to special-function 2 */
|
||||
for (gpio = S5PV310_GPK2(0); gpio < S5PV310_GPK2(2); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK2(0); gpio < EXYNOS4_GPK2(2); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
|
@ -101,14 +101,14 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
|
|||
|
||||
switch (width) {
|
||||
case 8:
|
||||
for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
|
||||
/* Data pin GPK3[3:6] to special-function 3 */
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
case 4:
|
||||
for (gpio = S5PV310_GPK2(3); gpio <= S5PV310_GPK2(6); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK2(3); gpio <= EXYNOS4_GPK2(6); gpio++) {
|
||||
/* Data pin GPK2[3:6] to special-function 2 */
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
|
||||
|
@ -119,25 +119,25 @@ void s5pv310_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
|
|||
}
|
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
|
||||
s3c_gpio_cfgpin(S5PV310_GPK2(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PV310_GPK2(2), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPK2(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(EXYNOS4_GPK2(2), S3C_GPIO_PULL_UP);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
}
|
||||
|
||||
void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
|
||||
void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
|
||||
{
|
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
|
||||
unsigned int gpio;
|
||||
|
||||
/* Set all the necessary GPK3[0:1] pins to special-function 2 */
|
||||
for (gpio = S5PV310_GPK3(0); gpio < S5PV310_GPK3(2); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK3(0); gpio < EXYNOS4_GPK3(2); gpio++) {
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
|
||||
for (gpio = S5PV310_GPK3(3); gpio <= S5PV310_GPK3(6); gpio++) {
|
||||
for (gpio = EXYNOS4_GPK3(3); gpio <= EXYNOS4_GPK3(6); gpio++) {
|
||||
/* Data pin GPK3[3:6] to special-function 2 */
|
||||
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_UP);
|
||||
|
@ -145,8 +145,8 @@ void s5pv310_setup_sdhci3_cfg_gpio(struct platform_device *dev, int width)
|
|||
}
|
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
|
||||
s3c_gpio_cfgpin(S5PV310_GPK3(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(S5PV310_GPK3(2), S3C_GPIO_PULL_UP);
|
||||
s3c_gpio_cfgpin(EXYNOS4_GPK3(2), S3C_GPIO_SFN(2));
|
||||
s3c_gpio_setpull(EXYNOS4_GPK3(2), S3C_GPIO_PULL_UP);
|
||||
s5p_gpio_set_drvstr(gpio, S5P_GPIO_DRVSTR_LV4);
|
||||
}
|
||||
}
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/setup-sdhci.c
|
||||
/* linux/arch/arm/mach-exynos4/setup-sdhci.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - Helper functions for settign up SDHCI device(s) (HSMMC)
|
||||
* EXYNOS4 - Helper functions for settign up SDHCI device(s) (HSMMC)
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
@ -23,14 +23,14 @@
|
|||
|
||||
/* clock sources for the mmc bus clock, order as for the ctrl2[5..4] */
|
||||
|
||||
char *s5pv310_hsmmc_clksrcs[4] = {
|
||||
char *exynos4_hsmmc_clksrcs[4] = {
|
||||
[0] = NULL,
|
||||
[1] = NULL,
|
||||
[2] = "sclk_mmc", /* mmc_bus */
|
||||
[3] = NULL,
|
||||
};
|
||||
|
||||
void s5pv310_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
|
||||
void exynos4_setup_sdhci_cfg_card(struct platform_device *dev, void __iomem *r,
|
||||
struct mmc_ios *ios, struct mmc_card *card)
|
||||
{
|
||||
u32 ctrl2, ctrl3;
|
76
arch/arm/mach-exynos4/sleep.S
Normal file
76
arch/arm/mach-exynos4/sleep.S
Normal file
|
@ -0,0 +1,76 @@
|
|||
/* linux/arch/arm/mach-exynos4/sleep.S
|
||||
*
|
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* EXYNOS4210 power Manager (Suspend-To-RAM) support
|
||||
* Based on S3C2410 sleep code by:
|
||||
* Ben Dooks, (c) 2004 Simtec Electronics
|
||||
*
|
||||
* Based on PXA/SA1100 sleep code by:
|
||||
* Nicolas Pitre, (c) 2002 Monta Vista Software Inc
|
||||
* Cliff Brake, (c) 2001
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#include <linux/linkage.h>
|
||||
#include <asm/assembler.h>
|
||||
#include <asm/memory.h>
|
||||
|
||||
.text
|
||||
|
||||
/*
|
||||
* s3c_cpu_save
|
||||
*
|
||||
* entry:
|
||||
* r1 = v:p offset
|
||||
*/
|
||||
|
||||
ENTRY(s3c_cpu_save)
|
||||
|
||||
stmfd sp!, { r3 - r12, lr }
|
||||
ldr r3, =resume_with_mmu
|
||||
bl cpu_suspend
|
||||
|
||||
ldr r0, =pm_cpu_sleep
|
||||
ldr r0, [ r0 ]
|
||||
mov pc, r0
|
||||
|
||||
resume_with_mmu:
|
||||
ldmfd sp!, { r3 - r12, pc }
|
||||
|
||||
.ltorg
|
||||
|
||||
/*
|
||||
* sleep magic, to allow the bootloader to check for an valid
|
||||
* image to resume to. Must be the first word before the
|
||||
* s3c_cpu_resume entry.
|
||||
*/
|
||||
|
||||
.word 0x2bedf00d
|
||||
|
||||
/*
|
||||
* s3c_cpu_resume
|
||||
*
|
||||
* resume code entry for bootloader to call
|
||||
*
|
||||
* we must put this code here in the data segment as we have no
|
||||
* other way of restoring the stack pointer after sleep, and we
|
||||
* must not write to the code segment (code is read-only)
|
||||
*/
|
||||
|
||||
ENTRY(s3c_cpu_resume)
|
||||
b cpu_resume
|
|
@ -1,9 +1,9 @@
|
|||
/* linux/arch/arm/mach-s5pv310/time.c
|
||||
/* linux/arch/arm/mach-exynos4/time.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 (and compatible) HRT support
|
||||
* EXYNOS4 (and compatible) HRT support
|
||||
* PWM 2/4 is used for this feature
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
|
@ -33,7 +33,7 @@ static struct clk *tdiv2;
|
|||
static struct clk *tdiv4;
|
||||
static struct clk *timerclk;
|
||||
|
||||
static void s5pv310_pwm_stop(unsigned int pwm_id)
|
||||
static void exynos4_pwm_stop(unsigned int pwm_id)
|
||||
{
|
||||
unsigned long tcon;
|
||||
|
||||
|
@ -52,7 +52,7 @@ static void s5pv310_pwm_stop(unsigned int pwm_id)
|
|||
__raw_writel(tcon, S3C2410_TCON);
|
||||
}
|
||||
|
||||
static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
|
||||
static void exynos4_pwm_init(unsigned int pwm_id, unsigned long tcnt)
|
||||
{
|
||||
unsigned long tcon;
|
||||
|
||||
|
@ -86,7 +86,7 @@ static void s5pv310_pwm_init(unsigned int pwm_id, unsigned long tcnt)
|
|||
}
|
||||
}
|
||||
|
||||
static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
|
||||
static inline void exynos4_pwm_start(unsigned int pwm_id, bool periodic)
|
||||
{
|
||||
unsigned long tcon;
|
||||
|
||||
|
@ -117,23 +117,23 @@ static inline void s5pv310_pwm_start(unsigned int pwm_id, bool periodic)
|
|||
__raw_writel(tcon, S3C2410_TCON);
|
||||
}
|
||||
|
||||
static int s5pv310_pwm_set_next_event(unsigned long cycles,
|
||||
static int exynos4_pwm_set_next_event(unsigned long cycles,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
s5pv310_pwm_init(2, cycles);
|
||||
s5pv310_pwm_start(2, 0);
|
||||
exynos4_pwm_init(2, cycles);
|
||||
exynos4_pwm_start(2, 0);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void s5pv310_pwm_set_mode(enum clock_event_mode mode,
|
||||
static void exynos4_pwm_set_mode(enum clock_event_mode mode,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
s5pv310_pwm_stop(2);
|
||||
exynos4_pwm_stop(2);
|
||||
|
||||
switch (mode) {
|
||||
case CLOCK_EVT_MODE_PERIODIC:
|
||||
s5pv310_pwm_init(2, clock_count_per_tick);
|
||||
s5pv310_pwm_start(2, 1);
|
||||
exynos4_pwm_init(2, clock_count_per_tick);
|
||||
exynos4_pwm_start(2, 1);
|
||||
break;
|
||||
case CLOCK_EVT_MODE_ONESHOT:
|
||||
break;
|
||||
|
@ -149,11 +149,11 @@ static struct clock_event_device pwm_event_device = {
|
|||
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
|
||||
.rating = 200,
|
||||
.shift = 32,
|
||||
.set_next_event = s5pv310_pwm_set_next_event,
|
||||
.set_mode = s5pv310_pwm_set_mode,
|
||||
.set_next_event = exynos4_pwm_set_next_event,
|
||||
.set_mode = exynos4_pwm_set_mode,
|
||||
};
|
||||
|
||||
irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
|
||||
irqreturn_t exynos4_clock_event_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct clock_event_device *evt = &pwm_event_device;
|
||||
|
||||
|
@ -162,13 +162,13 @@ irqreturn_t s5pv310_clock_event_isr(int irq, void *dev_id)
|
|||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction s5pv310_clock_event_irq = {
|
||||
static struct irqaction exynos4_clock_event_irq = {
|
||||
.name = "pwm_timer2_irq",
|
||||
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
|
||||
.handler = s5pv310_clock_event_isr,
|
||||
.handler = exynos4_clock_event_isr,
|
||||
};
|
||||
|
||||
static void __init s5pv310_clockevent_init(void)
|
||||
static void __init exynos4_clockevent_init(void)
|
||||
{
|
||||
unsigned long pclk;
|
||||
unsigned long clock_rate;
|
||||
|
@ -198,23 +198,39 @@ static void __init s5pv310_clockevent_init(void)
|
|||
pwm_event_device.cpumask = cpumask_of(0);
|
||||
clockevents_register_device(&pwm_event_device);
|
||||
|
||||
setup_irq(IRQ_TIMER2, &s5pv310_clock_event_irq);
|
||||
setup_irq(IRQ_TIMER2, &exynos4_clock_event_irq);
|
||||
}
|
||||
|
||||
static cycle_t s5pv310_pwm4_read(struct clocksource *cs)
|
||||
static cycle_t exynos4_pwm4_read(struct clocksource *cs)
|
||||
{
|
||||
return (cycle_t) ~__raw_readl(S3C_TIMERREG(0x40));
|
||||
}
|
||||
|
||||
static void exynos4_pwm4_resume(struct clocksource *cs)
|
||||
{
|
||||
unsigned long pclk;
|
||||
|
||||
pclk = clk_get_rate(timerclk);
|
||||
|
||||
clk_set_rate(tdiv4, pclk / 2);
|
||||
clk_set_parent(tin4, tdiv4);
|
||||
|
||||
exynos4_pwm_init(4, ~0);
|
||||
exynos4_pwm_start(4, 1);
|
||||
}
|
||||
|
||||
struct clocksource pwm_clocksource = {
|
||||
.name = "pwm_timer4",
|
||||
.rating = 250,
|
||||
.read = s5pv310_pwm4_read,
|
||||
.read = exynos4_pwm4_read,
|
||||
.mask = CLOCKSOURCE_MASK(32),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS ,
|
||||
#ifdef CONFIG_PM
|
||||
.resume = exynos4_pwm4_resume,
|
||||
#endif
|
||||
};
|
||||
|
||||
static void __init s5pv310_clocksource_init(void)
|
||||
static void __init exynos4_clocksource_init(void)
|
||||
{
|
||||
unsigned long pclk;
|
||||
unsigned long clock_rate;
|
||||
|
@ -226,14 +242,14 @@ static void __init s5pv310_clocksource_init(void)
|
|||
|
||||
clock_rate = clk_get_rate(tin4);
|
||||
|
||||
s5pv310_pwm_init(4, ~0);
|
||||
s5pv310_pwm_start(4, 1);
|
||||
exynos4_pwm_init(4, ~0);
|
||||
exynos4_pwm_start(4, 1);
|
||||
|
||||
if (clocksource_register_hz(&pwm_clocksource, clock_rate))
|
||||
panic("%s: can't register clocksource\n", pwm_clocksource.name);
|
||||
}
|
||||
|
||||
static void __init s5pv310_timer_resources(void)
|
||||
static void __init exynos4_timer_resources(void)
|
||||
{
|
||||
struct platform_device tmpdev;
|
||||
|
||||
|
@ -267,17 +283,17 @@ static void __init s5pv310_timer_resources(void)
|
|||
clk_enable(tin4);
|
||||
}
|
||||
|
||||
static void __init s5pv310_timer_init(void)
|
||||
static void __init exynos4_timer_init(void)
|
||||
{
|
||||
#ifdef CONFIG_LOCAL_TIMERS
|
||||
twd_base = S5P_VA_TWD;
|
||||
#endif
|
||||
|
||||
s5pv310_timer_resources();
|
||||
s5pv310_clockevent_init();
|
||||
s5pv310_clocksource_init();
|
||||
exynos4_timer_resources();
|
||||
exynos4_clockevent_init();
|
||||
exynos4_clocksource_init();
|
||||
}
|
||||
|
||||
struct sys_timer s5pv310_timer = {
|
||||
.init = s5pv310_timer_init,
|
||||
struct sys_timer exynos4_timer = {
|
||||
.init = exynos4_timer_init,
|
||||
};
|
|
@ -58,6 +58,9 @@
|
|||
#include <linux/mfd/pcf50633/pmic.h>
|
||||
#include <linux/mfd/pcf50633/backlight.h>
|
||||
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
@ -86,6 +89,8 @@
|
|||
#include <plat/udc.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/ts.h>
|
||||
|
||||
|
||||
static struct pcf50633 *gta02_pcf;
|
||||
|
||||
|
@ -280,9 +285,6 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
|
|||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.always_on = 1,
|
||||
.apply_uV = 1,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
},
|
||||
[PCF50633_REGULATOR_DOWN1] = {
|
||||
|
@ -301,9 +303,6 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
|
|||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
},
|
||||
[PCF50633_REGULATOR_HCLDO] = {
|
||||
|
@ -311,8 +310,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
|
|||
.min_uV = 2000000,
|
||||
.max_uV = 3300000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
|
||||
.always_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
},
|
||||
[PCF50633_REGULATOR_LDO1] = {
|
||||
|
@ -320,10 +319,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
|
|||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.apply_uV = 1,
|
||||
.state_mem = {
|
||||
.enabled = 0,
|
||||
},
|
||||
},
|
||||
},
|
||||
[PCF50633_REGULATOR_LDO2] = {
|
||||
|
@ -347,6 +344,7 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
|
|||
.min_uV = 3200000,
|
||||
.max_uV = 3200000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.apply_uV = 1,
|
||||
},
|
||||
},
|
||||
|
@ -355,10 +353,8 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
|
|||
.min_uV = 3000000,
|
||||
.max_uV = 3000000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
.apply_uV = 1,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
},
|
||||
[PCF50633_REGULATOR_LDO6] = {
|
||||
|
@ -373,9 +369,6 @@ struct pcf50633_platform_data gta02_pcf_pdata = {
|
|||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.state_mem = {
|
||||
.enabled = 1,
|
||||
},
|
||||
},
|
||||
},
|
||||
|
||||
|
@ -489,6 +482,43 @@ static struct s3c2410_hcd_info gta02_usb_info __initdata = {
|
|||
},
|
||||
};
|
||||
|
||||
/* Touchscreen */
|
||||
static struct s3c2410_ts_mach_info gta02_ts_info = {
|
||||
.delay = 10000,
|
||||
.presc = 0xff, /* slow as we can go */
|
||||
.oversampling_shift = 2,
|
||||
};
|
||||
|
||||
/* Buttons */
|
||||
static struct gpio_keys_button gta02_buttons[] = {
|
||||
{
|
||||
.gpio = GTA02_GPIO_AUX_KEY,
|
||||
.code = KEY_PHONE,
|
||||
.desc = "Aux",
|
||||
.type = EV_KEY,
|
||||
.debounce_interval = 100,
|
||||
},
|
||||
{
|
||||
.gpio = GTA02_GPIO_HOLD_KEY,
|
||||
.code = KEY_PAUSE,
|
||||
.desc = "Hold",
|
||||
.type = EV_KEY,
|
||||
.debounce_interval = 100,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data gta02_buttons_pdata = {
|
||||
.buttons = gta02_buttons,
|
||||
.nbuttons = ARRAY_SIZE(gta02_buttons),
|
||||
};
|
||||
|
||||
static struct platform_device gta02_buttons_device = {
|
||||
.name = "gpio-keys",
|
||||
.id = -1,
|
||||
.dev = {
|
||||
.platform_data = >a02_buttons_pdata,
|
||||
},
|
||||
};
|
||||
|
||||
static void __init gta02_map_io(void)
|
||||
{
|
||||
|
@ -509,7 +539,11 @@ static struct platform_device *gta02_devices[] __initdata = {
|
|||
>a02_nor_flash,
|
||||
&s3c24xx_pwm_device,
|
||||
&s3c_device_iis,
|
||||
&samsung_asoc_dma,
|
||||
&s3c_device_i2c0,
|
||||
>a02_buttons_device,
|
||||
&s3c_device_adc,
|
||||
&s3c_device_ts,
|
||||
};
|
||||
|
||||
/* These guys DO need to be children of PMU. */
|
||||
|
@ -559,6 +593,7 @@ static void __init gta02_machine_init(void)
|
|||
#endif
|
||||
|
||||
s3c24xx_udc_set_platdata(>a02_udc_cfg);
|
||||
s3c24xx_ts_set_platdata(>a02_ts_info);
|
||||
s3c_ohci_set_platdata(>a02_usb_info);
|
||||
s3c_nand_set_platdata(>a02_nand_info);
|
||||
s3c_i2c0_set_platdata(NULL);
|
||||
|
@ -567,6 +602,8 @@ static void __init gta02_machine_init(void)
|
|||
|
||||
platform_add_devices(gta02_devices, ARRAY_SIZE(gta02_devices));
|
||||
pm_power_off = gta02_poweroff;
|
||||
|
||||
regulator_has_full_constraints();
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -143,6 +143,7 @@ config MACH_SMDK6410
|
|||
select S3C_DEV_USB_HSOTG
|
||||
select S3C_DEV_WDT
|
||||
select SAMSUNG_DEV_KEYPAD
|
||||
select SAMSUNG_DEV_PWM
|
||||
select HAVE_S3C2410_WATCHDOG if WATCHDOG
|
||||
select S3C64XX_SETUP_SDHCI
|
||||
select S3C64XX_SETUP_I2C1
|
||||
|
@ -231,7 +232,7 @@ config MACH_HMT
|
|||
select S3C_DEV_NAND
|
||||
select S3C_DEV_USB_HOST
|
||||
select S3C64XX_SETUP_FB_24BPP
|
||||
select HAVE_PWM
|
||||
select SAMSUNG_DEV_PWM
|
||||
help
|
||||
Machine support for the Airgoo HMT
|
||||
|
||||
|
@ -249,8 +250,8 @@ config MACH_SMARTQ
|
|||
select S3C64XX_SETUP_SDHCI
|
||||
select S3C64XX_SETUP_FB_24BPP
|
||||
select SAMSUNG_DEV_ADC
|
||||
select SAMSUNG_DEV_PWM
|
||||
select SAMSUNG_DEV_TS
|
||||
select HAVE_PWM
|
||||
help
|
||||
Shared machine support for SmartQ 5/7
|
||||
|
||||
|
|
|
@ -181,7 +181,7 @@ static void __init s3c64xx_cpufreq_config_regulator(void)
|
|||
}
|
||||
#endif
|
||||
|
||||
static int __init s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
|
||||
static int s3c64xx_cpufreq_driver_init(struct cpufreq_policy *policy)
|
||||
{
|
||||
int ret;
|
||||
struct cpufreq_frequency_table *freq;
|
||||
|
|
|
@ -29,6 +29,7 @@
|
|||
#include <linux/smsc911x.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
|
||||
#ifdef CONFIG_SMDK6410_WM1190_EV1
|
||||
#include <linux/mfd/wm8350/core.h>
|
||||
|
@ -49,6 +50,7 @@
|
|||
#include <mach/hardware.h>
|
||||
#include <mach/regs-fb.h>
|
||||
#include <mach/map.h>
|
||||
#include <mach/gpio-bank-f.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
@ -119,7 +121,6 @@ static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
|
|||
{
|
||||
if (power) {
|
||||
gpio_direction_output(S3C64XX_GPF(13), 1);
|
||||
gpio_direction_output(S3C64XX_GPF(15), 1);
|
||||
|
||||
/* fire nRESET on power up */
|
||||
gpio_direction_output(S3C64XX_GPN(5), 0);
|
||||
|
@ -127,7 +128,6 @@ static void smdk6410_lcd_power_set(struct plat_lcd_data *pd,
|
|||
gpio_direction_output(S3C64XX_GPN(5), 1);
|
||||
msleep(1);
|
||||
} else {
|
||||
gpio_direction_output(S3C64XX_GPF(15), 0);
|
||||
gpio_direction_output(S3C64XX_GPF(13), 0);
|
||||
}
|
||||
}
|
||||
|
@ -270,6 +270,45 @@ static struct samsung_keypad_platdata smdk6410_keypad_data __initdata = {
|
|||
.cols = 8,
|
||||
};
|
||||
|
||||
static int smdk6410_backlight_init(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(S3C64XX_GPF(15), "Backlight");
|
||||
if (ret) {
|
||||
printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Configure GPIO pin with S3C64XX_GPF15_PWM_TOUT1 */
|
||||
s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_SFN(2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void smdk6410_backlight_exit(struct device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S3C64XX_GPF(15), S3C_GPIO_OUTPUT);
|
||||
gpio_free(S3C64XX_GPF(15));
|
||||
}
|
||||
|
||||
static struct platform_pwm_backlight_data smdk6410_backlight_data = {
|
||||
.pwm_id = 1,
|
||||
.max_brightness = 255,
|
||||
.dft_brightness = 255,
|
||||
.pwm_period_ns = 78770,
|
||||
.init = smdk6410_backlight_init,
|
||||
.exit = smdk6410_backlight_exit,
|
||||
};
|
||||
|
||||
static struct platform_device smdk6410_backlight_device = {
|
||||
.name = "pwm-backlight",
|
||||
.dev = {
|
||||
.parent = &s3c_device_timer[1].dev,
|
||||
.platform_data = &smdk6410_backlight_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct map_desc smdk6410_iodesc[] = {};
|
||||
|
||||
static struct platform_device *smdk6410_devices[] __initdata = {
|
||||
|
@ -299,6 +338,8 @@ static struct platform_device *smdk6410_devices[] __initdata = {
|
|||
&s3c_device_rtc,
|
||||
&s3c_device_ts,
|
||||
&s3c_device_wdt,
|
||||
&s3c_device_timer[1],
|
||||
&smdk6410_backlight_device,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_REGULATOR
|
||||
|
@ -694,7 +735,6 @@ static void __init smdk6410_machine_init(void)
|
|||
|
||||
gpio_request(S3C64XX_GPN(5), "LCD power");
|
||||
gpio_request(S3C64XX_GPF(13), "LCD power");
|
||||
gpio_request(S3C64XX_GPF(15), "LCD power");
|
||||
|
||||
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
|
||||
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
|
||||
|
|
|
@ -10,12 +10,14 @@ if ARCH_S5P64X0
|
|||
config CPU_S5P6440
|
||||
bool
|
||||
select S3C_PL330_DMA
|
||||
select S5P_HRT
|
||||
help
|
||||
Enable S5P6440 CPU support
|
||||
|
||||
config CPU_S5P6450
|
||||
bool
|
||||
select S3C_PL330_DMA
|
||||
select S5P_HRT
|
||||
help
|
||||
Enable S5P6450 CPU support
|
||||
|
||||
|
@ -34,6 +36,7 @@ config MACH_SMDK6440
|
|||
select S3C_DEV_WDT
|
||||
select S3C64XX_DEV_SPI
|
||||
select SAMSUNG_DEV_ADC
|
||||
select SAMSUNG_DEV_PWM
|
||||
select SAMSUNG_DEV_TS
|
||||
select S5P64X0_SETUP_I2C1
|
||||
help
|
||||
|
@ -47,6 +50,7 @@ config MACH_SMDK6450
|
|||
select S3C_DEV_WDT
|
||||
select S3C64XX_DEV_SPI
|
||||
select SAMSUNG_DEV_ADC
|
||||
select SAMSUNG_DEV_PWM
|
||||
select SAMSUNG_DEV_TS
|
||||
select S5P64X0_SETUP_I2C1
|
||||
help
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -32,6 +33,7 @@
|
|||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/i2c.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
@ -43,6 +45,7 @@
|
|||
#include <plat/pll.h>
|
||||
#include <plat/adc.h>
|
||||
#include <plat/ts.h>
|
||||
#include <plat/s5p-time.h>
|
||||
|
||||
#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
|
@ -88,6 +91,45 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
|
|||
},
|
||||
};
|
||||
|
||||
static int smdk6440_backlight_init(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(S5P6440_GPF(15), "Backlight");
|
||||
if (ret) {
|
||||
printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Configure GPIO pin with S5P6440_GPF15_PWM_TOUT1 */
|
||||
s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_SFN(2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void smdk6440_backlight_exit(struct device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5P6440_GPF(15), S3C_GPIO_OUTPUT);
|
||||
gpio_free(S5P6440_GPF(15));
|
||||
}
|
||||
|
||||
static struct platform_pwm_backlight_data smdk6440_backlight_data = {
|
||||
.pwm_id = 1,
|
||||
.max_brightness = 255,
|
||||
.dft_brightness = 255,
|
||||
.pwm_period_ns = 78770,
|
||||
.init = smdk6440_backlight_init,
|
||||
.exit = smdk6440_backlight_exit,
|
||||
};
|
||||
|
||||
static struct platform_device smdk6440_backlight_device = {
|
||||
.name = "pwm-backlight",
|
||||
.dev = {
|
||||
.parent = &s3c_device_timer[1].dev,
|
||||
.platform_data = &smdk6440_backlight_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *smdk6440_devices[] __initdata = {
|
||||
&s3c_device_adc,
|
||||
&s3c_device_rtc,
|
||||
|
@ -97,6 +139,8 @@ static struct platform_device *smdk6440_devices[] __initdata = {
|
|||
&s3c_device_wdt,
|
||||
&samsung_asoc_dma,
|
||||
&s5p6440_device_iis,
|
||||
&s3c_device_timer[1],
|
||||
&smdk6440_backlight_device,
|
||||
};
|
||||
|
||||
static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
|
||||
|
@ -136,6 +180,7 @@ static void __init smdk6440_map_io(void)
|
|||
s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
|
||||
s3c24xx_init_clocks(12000000);
|
||||
s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdk6440_machine_init(void)
|
||||
|
@ -159,5 +204,5 @@ MACHINE_START(SMDK6440, "SMDK6440")
|
|||
.init_irq = s5p6440_init_irq,
|
||||
.map_io = smdk6440_map_io,
|
||||
.init_machine = smdk6440_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
.timer = &s5p_timer,
|
||||
MACHINE_END
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/module.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -32,6 +33,7 @@
|
|||
#include <mach/map.h>
|
||||
#include <mach/regs-clock.h>
|
||||
#include <mach/i2c.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
|
@ -43,6 +45,7 @@
|
|||
#include <plat/pll.h>
|
||||
#include <plat/adc.h>
|
||||
#include <plat/ts.h>
|
||||
#include <plat/s5p-time.h>
|
||||
|
||||
#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
|
@ -106,6 +109,45 @@ static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
|
|||
#endif
|
||||
};
|
||||
|
||||
static int smdk6450_backlight_init(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(S5P6450_GPF(15), "Backlight");
|
||||
if (ret) {
|
||||
printk(KERN_ERR "failed to request GPF for PWM-OUT1\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Configure GPIO pin with S5P6450_GPF15_PWM_TOUT1 */
|
||||
s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_SFN(2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void smdk6450_backlight_exit(struct device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5P6450_GPF(15), S3C_GPIO_OUTPUT);
|
||||
gpio_free(S5P6450_GPF(15));
|
||||
}
|
||||
|
||||
static struct platform_pwm_backlight_data smdk6450_backlight_data = {
|
||||
.pwm_id = 1,
|
||||
.max_brightness = 255,
|
||||
.dft_brightness = 255,
|
||||
.pwm_period_ns = 78770,
|
||||
.init = smdk6450_backlight_init,
|
||||
.exit = smdk6450_backlight_exit,
|
||||
};
|
||||
|
||||
static struct platform_device smdk6450_backlight_device = {
|
||||
.name = "pwm-backlight",
|
||||
.dev = {
|
||||
.parent = &s3c_device_timer[1].dev,
|
||||
.platform_data = &smdk6450_backlight_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *smdk6450_devices[] __initdata = {
|
||||
&s3c_device_adc,
|
||||
&s3c_device_rtc,
|
||||
|
@ -115,6 +157,8 @@ static struct platform_device *smdk6450_devices[] __initdata = {
|
|||
&s3c_device_wdt,
|
||||
&samsung_asoc_dma,
|
||||
&s5p6450_device_iis0,
|
||||
&s3c_device_timer[1],
|
||||
&smdk6450_backlight_device,
|
||||
/* s5p6450_device_spi0 will be added */
|
||||
};
|
||||
|
||||
|
@ -155,6 +199,7 @@ static void __init smdk6450_map_io(void)
|
|||
s5p_init_io(NULL, 0, S5P64X0_SYS_ID);
|
||||
s3c24xx_init_clocks(19200000);
|
||||
s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdk6450_machine_init(void)
|
||||
|
@ -178,5 +223,5 @@ MACHINE_START(SMDK6450, "SMDK6450")
|
|||
.init_irq = s5p6450_init_irq,
|
||||
.map_io = smdk6450_map_io,
|
||||
.init_machine = smdk6450_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
.timer = &s5p_timer,
|
||||
MACHINE_END
|
||||
|
|
|
@ -58,6 +58,7 @@ config MACH_SMDKC100
|
|||
select SAMSUNG_DEV_ADC
|
||||
select SAMSUNG_DEV_IDE
|
||||
select SAMSUNG_DEV_KEYPAD
|
||||
select SAMSUNG_DEV_PWM
|
||||
select SAMSUNG_DEV_TS
|
||||
select S5PC100_SETUP_FB_24BPP
|
||||
select S5PC100_SETUP_I2C1
|
||||
|
|
|
@ -348,6 +348,7 @@ static __init int s5pc100_gpiolib_init(void)
|
|||
}
|
||||
|
||||
samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips, nr_chips);
|
||||
s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -23,12 +23,15 @@
|
|||
#include <linux/fb.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/regs-fb.h>
|
||||
#include <mach/regs-gpio.h>
|
||||
|
||||
#include <video/platform_lcd.h>
|
||||
|
||||
#include <asm/irq.h>
|
||||
|
@ -107,9 +110,6 @@ static struct i2c_board_info i2c_devs1[] __initdata = {
|
|||
static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
|
||||
unsigned int power)
|
||||
{
|
||||
/* backlight */
|
||||
gpio_direction_output(S5PC100_GPD(0), power);
|
||||
|
||||
if (power) {
|
||||
/* module reset */
|
||||
gpio_direction_output(S5PC100_GPH0(6), 1);
|
||||
|
@ -179,6 +179,45 @@ static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = {
|
|||
.cols = 8,
|
||||
};
|
||||
|
||||
static int smdkc100_backlight_init(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(S5PC100_GPD(0), "Backlight");
|
||||
if (ret) {
|
||||
printk(KERN_ERR "failed to request GPF for PWM-OUT0\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Configure GPIO pin with S5PC100_GPD_TOUT_0 */
|
||||
s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_SFN(2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void smdkc100_backlight_exit(struct device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5PC100_GPD(0), S3C_GPIO_OUTPUT);
|
||||
gpio_free(S5PC100_GPD(0));
|
||||
}
|
||||
|
||||
static struct platform_pwm_backlight_data smdkc100_backlight_data = {
|
||||
.pwm_id = 0,
|
||||
.max_brightness = 255,
|
||||
.dft_brightness = 255,
|
||||
.pwm_period_ns = 78770,
|
||||
.init = smdkc100_backlight_init,
|
||||
.exit = smdkc100_backlight_exit,
|
||||
};
|
||||
|
||||
static struct platform_device smdkc100_backlight_device = {
|
||||
.name = "pwm-backlight",
|
||||
.dev = {
|
||||
.parent = &s3c_device_timer[0].dev,
|
||||
.platform_data = &smdkc100_backlight_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *smdkc100_devices[] __initdata = {
|
||||
&s3c_device_adc,
|
||||
&s3c_device_cfcon,
|
||||
|
@ -200,6 +239,8 @@ static struct platform_device *smdkc100_devices[] __initdata = {
|
|||
&s5p_device_fimc1,
|
||||
&s5p_device_fimc2,
|
||||
&s5pc100_device_spdif,
|
||||
&s3c_device_timer[0],
|
||||
&smdkc100_backlight_device,
|
||||
};
|
||||
|
||||
static struct s3c2410_ts_mach_info s3c_ts_platform __initdata = {
|
||||
|
@ -233,7 +274,6 @@ static void __init smdkc100_machine_init(void)
|
|||
s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
|
||||
|
||||
/* LCD init */
|
||||
gpio_request(S5PC100_GPD(0), "GPD");
|
||||
gpio_request(S5PC100_GPH0(6), "GPH0");
|
||||
smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
|
||||
platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
|
||||
|
|
|
@ -13,6 +13,7 @@ config CPU_S5PV210
|
|||
bool
|
||||
select S3C_PL330_DMA
|
||||
select S5P_EXT_INT
|
||||
select S5P_HRT
|
||||
select S5PV210_PM if PM
|
||||
help
|
||||
Enable S5PV210 CPU support
|
||||
|
@ -53,6 +54,11 @@ config S5PV210_SETUP_SDHCI_GPIO
|
|||
help
|
||||
Common setup code for SDHCI gpio.
|
||||
|
||||
config S5PV210_SETUP_FIMC
|
||||
bool
|
||||
help
|
||||
Common setup code for the camera interfaces.
|
||||
|
||||
menu "S5PC110 Machines"
|
||||
|
||||
config MACH_AQUILA
|
||||
|
@ -130,6 +136,7 @@ config MACH_SMDKV210
|
|||
select SAMSUNG_DEV_ADC
|
||||
select SAMSUNG_DEV_IDE
|
||||
select SAMSUNG_DEV_KEYPAD
|
||||
select SAMSUNG_DEV_PWM
|
||||
select SAMSUNG_DEV_TS
|
||||
select S5PV210_SETUP_FB_24BPP
|
||||
select S5PV210_SETUP_I2C1
|
||||
|
|
|
@ -31,6 +31,7 @@ obj-y += dev-audio.o
|
|||
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
|
||||
|
||||
obj-$(CONFIG_S5PV210_SETUP_FB_24BPP) += setup-fb-24bpp.o
|
||||
obj-$(CONFIG_S5PV210_SETUP_FIMC) += setup-fimc.o
|
||||
obj-$(CONFIG_S5PV210_SETUP_I2C1) += setup-i2c1.o
|
||||
obj-$(CONFIG_S5PV210_SETUP_I2C2) += setup-i2c2.o
|
||||
obj-$(CONFIG_S5PV210_SETUP_IDE) += setup-ide.o
|
||||
|
|
|
@ -281,6 +281,7 @@ static __init int s5pv210_gpiolib_init(void)
|
|||
}
|
||||
|
||||
samsung_gpiolib_add_4bit_chips(s5pv210_gpio_4bit, nr_chips);
|
||||
s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -146,6 +146,10 @@
|
|||
#define S5P_OM_STAT S5P_CLKREG(0xE100)
|
||||
#define S5P_USB_PHY_CONTROL S5P_CLKREG(0xE80C)
|
||||
#define S5P_DAC_CONTROL S5P_CLKREG(0xE810)
|
||||
#define S5P_MIPI_DPHY_CONTROL(x) S5P_CLKREG(0xE814)
|
||||
#define S5P_MIPI_DPHY_ENABLE (1 << 0)
|
||||
#define S5P_MIPI_DPHY_SRESETN (1 << 1)
|
||||
#define S5P_MIPI_DPHY_MRESETN (1 << 2)
|
||||
|
||||
#define S5P_INFORM0 S5P_CLKREG(0xF000)
|
||||
#define S5P_INFORM1 S5P_CLKREG(0xF004)
|
||||
|
@ -161,7 +165,6 @@
|
|||
#define S5P_MDNIE_SEL S5P_CLKREG(0x7008)
|
||||
#define S5P_MIPI_PHY_CON0 S5P_CLKREG(0x7200)
|
||||
#define S5P_MIPI_PHY_CON1 S5P_CLKREG(0x7204)
|
||||
#define S5P_MIPI_DPHY_CONTROL S5P_CLKREG(0xE814)
|
||||
|
||||
#define S5P_IDLE_CFG_TL_MASK (3 << 30)
|
||||
#define S5P_IDLE_CFG_TM_MASK (3 << 28)
|
||||
|
|
|
@ -39,6 +39,7 @@
|
|||
#include <plat/fb.h>
|
||||
#include <plat/fimc-core.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/s5p-time.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define AQUILA_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
|
@ -296,13 +297,11 @@ static struct regulator_init_data aquila_ldo17_data = {
|
|||
};
|
||||
|
||||
/* BUCK */
|
||||
static struct regulator_consumer_supply buck1_consumer[] = {
|
||||
{ .supply = "vddarm", },
|
||||
};
|
||||
static struct regulator_consumer_supply buck1_consumer =
|
||||
REGULATOR_SUPPLY("vddarm", NULL);
|
||||
|
||||
static struct regulator_consumer_supply buck2_consumer[] = {
|
||||
{ .supply = "vddint", },
|
||||
};
|
||||
static struct regulator_consumer_supply buck2_consumer =
|
||||
REGULATOR_SUPPLY("vddint", NULL);
|
||||
|
||||
static struct regulator_init_data aquila_buck1_data = {
|
||||
.constraints = {
|
||||
|
@ -313,8 +312,8 @@ static struct regulator_init_data aquila_buck1_data = {
|
|||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(buck1_consumer),
|
||||
.consumer_supplies = buck1_consumer,
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &buck1_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data aquila_buck2_data = {
|
||||
|
@ -326,8 +325,8 @@ static struct regulator_init_data aquila_buck2_data = {
|
|||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(buck2_consumer),
|
||||
.consumer_supplies = buck2_consumer,
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &buck2_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data aquila_buck3_data = {
|
||||
|
@ -391,26 +390,14 @@ static struct max8998_platform_data aquila_max8998_pdata = {
|
|||
#endif
|
||||
|
||||
static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
|
||||
{
|
||||
.dev_name = "5-001a",
|
||||
.supply = "DBVDD",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "AVDD2",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "CPVDD",
|
||||
},
|
||||
REGULATOR_SUPPLY("DBVDD", "5-001a"),
|
||||
REGULATOR_SUPPLY("AVDD2", "5-001a"),
|
||||
REGULATOR_SUPPLY("CPVDD", "5-001a"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
|
||||
{
|
||||
.dev_name = "5-001a",
|
||||
.supply = "SPKVDD1",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "SPKVDD2",
|
||||
},
|
||||
REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
|
||||
REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
|
||||
|
@ -459,15 +446,11 @@ static struct platform_device wm8994_fixed_voltage1 = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_avdd1_supply = {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "AVDD1",
|
||||
};
|
||||
static struct regulator_consumer_supply wm8994_avdd1_supply =
|
||||
REGULATOR_SUPPLY("AVDD1", "5-001a");
|
||||
|
||||
static struct regulator_consumer_supply wm8994_dcvdd_supply = {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "DCVDD",
|
||||
};
|
||||
static struct regulator_consumer_supply wm8994_dcvdd_supply =
|
||||
REGULATOR_SUPPLY("DCVDD", "5-001a");
|
||||
|
||||
static struct regulator_init_data wm8994_ldo1_data = {
|
||||
.constraints = {
|
||||
|
@ -664,6 +647,7 @@ static void __init aquila_map_io(void)
|
|||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(aquila_uartcfgs, ARRAY_SIZE(aquila_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
|
||||
}
|
||||
|
||||
static void __init aquila_machine_init(void)
|
||||
|
@ -698,5 +682,5 @@ MACHINE_START(AQUILA, "Aquila")
|
|||
.init_irq = s5pv210_init_irq,
|
||||
.map_io = aquila_map_io,
|
||||
.init_machine = aquila_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
.timer = &s5p_timer,
|
||||
MACHINE_END
|
||||
|
|
|
@ -45,6 +45,7 @@
|
|||
#include <plat/keypad.h>
|
||||
#include <plat/sdhci.h>
|
||||
#include <plat/clock.h>
|
||||
#include <plat/s5p-time.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define GONI_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
|
@ -108,6 +109,8 @@ static struct s3c_fb_pd_win goni_fb_win0 = {
|
|||
},
|
||||
.max_bpp = 32,
|
||||
.default_bpp = 16,
|
||||
.virtual_x = 480,
|
||||
.virtual_y = 2 * 800,
|
||||
};
|
||||
|
||||
static struct s3c_fb_platdata goni_lcd_pdata __initdata = {
|
||||
|
@ -269,10 +272,30 @@ static void __init goni_tsp_init(void)
|
|||
/* MAX8998 regulators */
|
||||
#if defined(CONFIG_REGULATOR_MAX8998) || defined(CONFIG_REGULATOR_MAX8998_MODULE)
|
||||
|
||||
static struct regulator_consumer_supply goni_ldo3_consumers[] = {
|
||||
REGULATOR_SUPPLY("vusb_a", "s3c-hsotg"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply goni_ldo5_consumers[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply goni_ldo8_consumers[] = {
|
||||
REGULATOR_SUPPLY("vusb_d", "s3c-hsotg"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply goni_ldo11_consumers[] = {
|
||||
REGULATOR_SUPPLY("vddio", "0-0030"), /* "CAM_IO_2.8V" */
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply goni_ldo13_consumers[] = {
|
||||
REGULATOR_SUPPLY("vdda", "0-0030"), /* "CAM_A_2.8V" */
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply goni_ldo14_consumers[] = {
|
||||
REGULATOR_SUPPLY("vdd_core", "0-0030"), /* "CAM_CIF_1.8V" */
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_ldo2_data = {
|
||||
.constraints = {
|
||||
.name = "VALIVE_1.1V",
|
||||
|
@ -292,8 +315,10 @@ static struct regulator_init_data goni_ldo3_data = {
|
|||
.min_uV = 1100000,
|
||||
.max_uV = 1100000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(goni_ldo3_consumers),
|
||||
.consumer_supplies = goni_ldo3_consumers,
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_ldo4_data = {
|
||||
|
@ -311,6 +336,7 @@ static struct regulator_init_data goni_ldo5_data = {
|
|||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(goni_ldo5_consumers),
|
||||
.consumer_supplies = goni_ldo5_consumers,
|
||||
|
@ -341,8 +367,10 @@ static struct regulator_init_data goni_ldo8_data = {
|
|||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(goni_ldo8_consumers),
|
||||
.consumer_supplies = goni_ldo8_consumers,
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_ldo9_data = {
|
||||
|
@ -351,7 +379,6 @@ static struct regulator_init_data goni_ldo9_data = {
|
|||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -371,8 +398,10 @@ static struct regulator_init_data goni_ldo11_data = {
|
|||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(goni_ldo11_consumers),
|
||||
.consumer_supplies = goni_ldo11_consumers,
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_ldo12_data = {
|
||||
|
@ -381,7 +410,6 @@ static struct regulator_init_data goni_ldo12_data = {
|
|||
.min_uV = 1200000,
|
||||
.max_uV = 1200000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -391,8 +419,10 @@ static struct regulator_init_data goni_ldo13_data = {
|
|||
.min_uV = 2800000,
|
||||
.max_uV = 2800000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(goni_ldo13_consumers),
|
||||
.consumer_supplies = goni_ldo13_consumers,
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_ldo14_data = {
|
||||
|
@ -401,8 +431,10 @@ static struct regulator_init_data goni_ldo14_data = {
|
|||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(goni_ldo14_consumers),
|
||||
.consumer_supplies = goni_ldo14_consumers,
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_ldo15_data = {
|
||||
|
@ -411,7 +443,6 @@ static struct regulator_init_data goni_ldo15_data = {
|
|||
.min_uV = 3300000,
|
||||
.max_uV = 3300000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -421,7 +452,6 @@ static struct regulator_init_data goni_ldo16_data = {
|
|||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.apply_uV = 1,
|
||||
.always_on = 1,
|
||||
},
|
||||
};
|
||||
|
||||
|
@ -436,13 +466,11 @@ static struct regulator_init_data goni_ldo17_data = {
|
|||
};
|
||||
|
||||
/* BUCK */
|
||||
static struct regulator_consumer_supply buck1_consumer[] = {
|
||||
{ .supply = "vddarm", },
|
||||
};
|
||||
static struct regulator_consumer_supply buck1_consumer =
|
||||
REGULATOR_SUPPLY("vddarm", NULL);
|
||||
|
||||
static struct regulator_consumer_supply buck2_consumer[] = {
|
||||
{ .supply = "vddint", },
|
||||
};
|
||||
static struct regulator_consumer_supply buck2_consumer =
|
||||
REGULATOR_SUPPLY("vddint", NULL);
|
||||
|
||||
static struct regulator_init_data goni_buck1_data = {
|
||||
.constraints = {
|
||||
|
@ -453,8 +481,8 @@ static struct regulator_init_data goni_buck1_data = {
|
|||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(buck1_consumer),
|
||||
.consumer_supplies = buck1_consumer,
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &buck1_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_buck2_data = {
|
||||
|
@ -466,8 +494,8 @@ static struct regulator_init_data goni_buck2_data = {
|
|||
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(buck2_consumer),
|
||||
.consumer_supplies = buck2_consumer,
|
||||
.num_consumer_supplies = 1,
|
||||
.consumer_supplies = &buck2_consumer,
|
||||
};
|
||||
|
||||
static struct regulator_init_data goni_buck3_data = {
|
||||
|
@ -531,26 +559,14 @@ static struct max8998_platform_data goni_max8998_pdata = {
|
|||
#endif
|
||||
|
||||
static struct regulator_consumer_supply wm8994_fixed_voltage0_supplies[] = {
|
||||
{
|
||||
.dev_name = "5-001a",
|
||||
.supply = "DBVDD",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "AVDD2",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "CPVDD",
|
||||
},
|
||||
REGULATOR_SUPPLY("DBVDD", "5-001a"),
|
||||
REGULATOR_SUPPLY("AVDD2", "5-001a"),
|
||||
REGULATOR_SUPPLY("CPVDD", "5-001a"),
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_fixed_voltage1_supplies[] = {
|
||||
{
|
||||
.dev_name = "5-001a",
|
||||
.supply = "SPKVDD1",
|
||||
}, {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "SPKVDD2",
|
||||
},
|
||||
REGULATOR_SUPPLY("SPKVDD1", "5-001a"),
|
||||
REGULATOR_SUPPLY("SPKVDD2", "5-001a"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data wm8994_fixed_voltage0_init_data = {
|
||||
|
@ -599,15 +615,11 @@ static struct platform_device wm8994_fixed_voltage1 = {
|
|||
},
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply wm8994_avdd1_supply = {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "AVDD1",
|
||||
};
|
||||
static struct regulator_consumer_supply wm8994_avdd1_supply =
|
||||
REGULATOR_SUPPLY("AVDD1", "5-001a");
|
||||
|
||||
static struct regulator_consumer_supply wm8994_dcvdd_supply = {
|
||||
.dev_name = "5-001a",
|
||||
.supply = "DCVDD",
|
||||
};
|
||||
static struct regulator_consumer_supply wm8994_dcvdd_supply =
|
||||
REGULATOR_SUPPLY("DCVDD", "5-001a");
|
||||
|
||||
static struct regulator_init_data wm8994_ldo1_data = {
|
||||
.constraints = {
|
||||
|
@ -794,6 +806,7 @@ static struct platform_device *goni_devices[] __initdata = {
|
|||
&goni_i2c_gpio5,
|
||||
&mmc2_fixed_voltage,
|
||||
&goni_device_gpiokeys,
|
||||
&s3c_device_i2c0,
|
||||
&s5p_device_fimc0,
|
||||
&s5p_device_fimc1,
|
||||
&s5p_device_fimc2,
|
||||
|
@ -823,6 +836,7 @@ static void __init goni_map_io(void)
|
|||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(goni_uartcfgs, ARRAY_SIZE(goni_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
|
||||
}
|
||||
|
||||
static void __init goni_machine_init(void)
|
||||
|
@ -830,6 +844,9 @@ static void __init goni_machine_init(void)
|
|||
/* Radio: call before I2C 1 registeration */
|
||||
goni_radio_init();
|
||||
|
||||
/* I2C0 */
|
||||
s3c_i2c0_set_platdata(NULL);
|
||||
|
||||
/* I2C1 */
|
||||
s3c_i2c1_set_platdata(NULL);
|
||||
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
|
||||
|
@ -873,5 +890,5 @@ MACHINE_START(GONI, "GONI")
|
|||
.init_irq = s5pv210_init_irq,
|
||||
.map_io = goni_map_io,
|
||||
.init_machine = goni_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
.timer = &s5p_timer,
|
||||
MACHINE_END
|
||||
|
|
|
@ -30,6 +30,7 @@
|
|||
#include <plat/ata.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/s5p-time.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define SMDKC110_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
|
@ -111,6 +112,7 @@ static void __init smdkc110_map_io(void)
|
|||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdkc110_machine_init(void)
|
||||
|
@ -138,5 +140,5 @@ MACHINE_START(SMDKC110, "SMDKC110")
|
|||
.init_irq = s5pv210_init_irq,
|
||||
.map_io = smdkc110_map_io,
|
||||
.init_machine = smdkc110_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
.timer = &s5p_timer,
|
||||
MACHINE_END
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/fb.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/pwm_backlight.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -43,6 +44,8 @@
|
|||
#include <plat/keypad.h>
|
||||
#include <plat/pm.h>
|
||||
#include <plat/fb.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/s5p-time.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define SMDKV210_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
|
@ -208,6 +211,45 @@ static struct s3c_fb_platdata smdkv210_lcd0_pdata __initdata = {
|
|||
.setup_gpio = s5pv210_fb_gpio_setup_24bpp,
|
||||
};
|
||||
|
||||
static int smdkv210_backlight_init(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = gpio_request(S5PV210_GPD0(3), "Backlight");
|
||||
if (ret) {
|
||||
printk(KERN_ERR "failed to request GPD for PWM-OUT 3\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Configure GPIO pin with S5PV210_GPD_0_3_TOUT_3 */
|
||||
s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_SFN(2));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void smdkv210_backlight_exit(struct device *dev)
|
||||
{
|
||||
s3c_gpio_cfgpin(S5PV210_GPD0(3), S3C_GPIO_OUTPUT);
|
||||
gpio_free(S5PV210_GPD0(3));
|
||||
}
|
||||
|
||||
static struct platform_pwm_backlight_data smdkv210_backlight_data = {
|
||||
.pwm_id = 3,
|
||||
.max_brightness = 255,
|
||||
.dft_brightness = 255,
|
||||
.pwm_period_ns = 78770,
|
||||
.init = smdkv210_backlight_init,
|
||||
.exit = smdkv210_backlight_exit,
|
||||
};
|
||||
|
||||
static struct platform_device smdkv210_backlight_device = {
|
||||
.name = "pwm-backlight",
|
||||
.dev = {
|
||||
.parent = &s3c_device_timer[3].dev,
|
||||
.platform_data = &smdkv210_backlight_data,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device *smdkv210_devices[] __initdata = {
|
||||
&s3c_device_adc,
|
||||
&s3c_device_cfcon,
|
||||
|
@ -229,6 +271,8 @@ static struct platform_device *smdkv210_devices[] __initdata = {
|
|||
&samsung_device_keypad,
|
||||
&smdkv210_dm9000,
|
||||
&smdkv210_lcd_lte480wv,
|
||||
&s3c_device_timer[3],
|
||||
&smdkv210_backlight_device,
|
||||
};
|
||||
|
||||
static void __init smdkv210_dm9000_init(void)
|
||||
|
@ -272,6 +316,7 @@ static void __init smdkv210_map_io(void)
|
|||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(smdkv210_uartcfgs, ARRAY_SIZE(smdkv210_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM2, S5P_PWM4);
|
||||
}
|
||||
|
||||
static void __init smdkv210_machine_init(void)
|
||||
|
@ -306,5 +351,5 @@ MACHINE_START(SMDKV210, "SMDKV210")
|
|||
.init_irq = s5pv210_init_irq,
|
||||
.map_io = smdkv210_map_io,
|
||||
.init_machine = smdkv210_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
.timer = &s5p_timer,
|
||||
MACHINE_END
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
#include <plat/devs.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/iic.h>
|
||||
#include <plat/s5p-time.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define TORBRECK_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
|
@ -104,6 +105,7 @@ static void __init torbreck_map_io(void)
|
|||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(torbreck_uartcfgs, ARRAY_SIZE(torbreck_uartcfgs));
|
||||
s5p_set_timer_source(S5P_PWM3, S5P_PWM4);
|
||||
}
|
||||
|
||||
static void __init torbreck_machine_init(void)
|
||||
|
@ -127,5 +129,5 @@ MACHINE_START(TORBRECK, "TORBRECK")
|
|||
.init_irq = s5pv210_init_irq,
|
||||
.map_io = torbreck_map_io,
|
||||
.init_machine = torbreck_machine_init,
|
||||
.timer = &s3c24xx_timer,
|
||||
.timer = &s5p_timer,
|
||||
MACHINE_END
|
||||
|
|
43
arch/arm/mach-s5pv210/setup-fimc.c
Normal file
43
arch/arm/mach-s5pv210/setup-fimc.c
Normal file
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* S5PV210 camera interface GPIO configuration.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/gpio.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/camport.h>
|
||||
|
||||
int s5pv210_fimc_setup_gpio(enum s5p_camport_id id)
|
||||
{
|
||||
u32 gpio8, gpio5;
|
||||
int ret;
|
||||
|
||||
switch (id) {
|
||||
case S5P_CAMPORT_A:
|
||||
gpio8 = S5PV210_GPE0(0);
|
||||
gpio5 = S5PV210_GPE1(0);
|
||||
break;
|
||||
|
||||
case S5P_CAMPORT_B:
|
||||
gpio8 = S5PV210_GPJ0(0);
|
||||
gpio5 = S5PV210_GPJ1(0);
|
||||
break;
|
||||
|
||||
default:
|
||||
WARN(1, "Wrong camport id: %d\n", id);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
ret = s3c_gpio_cfgall_range(gpio8, 8, S3C_GPIO_SFN(2),
|
||||
S3C_GPIO_PULL_UP);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return s3c_gpio_cfgall_range(gpio5, 5, S3C_GPIO_SFN(2),
|
||||
S3C_GPIO_PULL_UP);
|
||||
}
|
|
@ -1,151 +0,0 @@
|
|||
# arch/arm/mach-s5pv310/Kconfig
|
||||
#
|
||||
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
# http://www.samsung.com/
|
||||
#
|
||||
# Licensed under GPLv2
|
||||
|
||||
# Configuration options for the S5PV310
|
||||
|
||||
if ARCH_S5PV310
|
||||
|
||||
config CPU_S5PV310
|
||||
bool
|
||||
select S3C_PL330_DMA
|
||||
help
|
||||
Enable S5PV310 CPU support
|
||||
|
||||
config S5PV310_DEV_PD
|
||||
bool
|
||||
help
|
||||
Compile in platform device definitions for Power Domain
|
||||
|
||||
config S5PV310_SETUP_I2C1
|
||||
bool
|
||||
help
|
||||
Common setup code for i2c bus 1.
|
||||
|
||||
config S5PV310_SETUP_I2C2
|
||||
bool
|
||||
help
|
||||
Common setup code for i2c bus 2.
|
||||
|
||||
config S5PV310_SETUP_I2C3
|
||||
bool
|
||||
help
|
||||
Common setup code for i2c bus 3.
|
||||
|
||||
config S5PV310_SETUP_I2C4
|
||||
bool
|
||||
help
|
||||
Common setup code for i2c bus 4.
|
||||
|
||||
config S5PV310_SETUP_I2C5
|
||||
bool
|
||||
help
|
||||
Common setup code for i2c bus 5.
|
||||
|
||||
config S5PV310_SETUP_I2C6
|
||||
bool
|
||||
help
|
||||
Common setup code for i2c bus 6.
|
||||
|
||||
config S5PV310_SETUP_I2C7
|
||||
bool
|
||||
help
|
||||
Common setup code for i2c bus 7.
|
||||
|
||||
config S5PV310_SETUP_SDHCI
|
||||
bool
|
||||
select S5PV310_SETUP_SDHCI_GPIO
|
||||
help
|
||||
Internal helper functions for S5PV310 based SDHCI systems.
|
||||
|
||||
config S5PV310_SETUP_SDHCI_GPIO
|
||||
bool
|
||||
help
|
||||
Common setup code for SDHCI gpio.
|
||||
|
||||
config S5PV310_DEV_SYSMMU
|
||||
bool
|
||||
help
|
||||
Common setup code for SYSTEM MMU in S5PV310
|
||||
|
||||
# machine support
|
||||
|
||||
menu "S5PC210 Machines"
|
||||
|
||||
config MACH_SMDKC210
|
||||
bool "SMDKC210"
|
||||
select CPU_S5PV310
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S5PV310_DEV_PD
|
||||
select S5PV310_SETUP_I2C1
|
||||
select S5PV310_SETUP_SDHCI
|
||||
select S5PV310_DEV_SYSMMU
|
||||
help
|
||||
Machine support for Samsung SMDKC210
|
||||
S5PC210(MCP) is one of package option of S5PV310
|
||||
|
||||
config MACH_UNIVERSAL_C210
|
||||
bool "Mobile UNIVERSAL_C210 Board"
|
||||
select CPU_S5PV310
|
||||
select S5P_DEV_ONENAND
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S5PV310_SETUP_SDHCI
|
||||
select S3C_DEV_I2C1
|
||||
select S5PV310_SETUP_I2C1
|
||||
help
|
||||
Machine support for Samsung Mobile Universal S5PC210 Reference
|
||||
Board. S5PC210(MCP) is one of package option of S5PV310
|
||||
|
||||
endmenu
|
||||
|
||||
menu "S5PV310 Machines"
|
||||
|
||||
config MACH_SMDKV310
|
||||
bool "SMDKV310"
|
||||
select CPU_S5PV310
|
||||
select S3C_DEV_RTC
|
||||
select S3C_DEV_WDT
|
||||
select S3C_DEV_I2C1
|
||||
select S3C_DEV_HSMMC
|
||||
select S3C_DEV_HSMMC1
|
||||
select S3C_DEV_HSMMC2
|
||||
select S3C_DEV_HSMMC3
|
||||
select S5PV310_DEV_PD
|
||||
select S5PV310_DEV_SYSMMU
|
||||
select S5PV310_SETUP_I2C1
|
||||
select S5PV310_SETUP_SDHCI
|
||||
help
|
||||
Machine support for Samsung SMDKV310
|
||||
|
||||
endmenu
|
||||
|
||||
comment "Configuration for HSMMC bus width"
|
||||
|
||||
menu "Use 8-bit bus width"
|
||||
|
||||
config S5PV310_SDHCI_CH0_8BIT
|
||||
bool "Channel 0 with 8-bit bus"
|
||||
help
|
||||
Support HSMMC Channel 0 8-bit bus.
|
||||
If selected, Channel 1 is disabled.
|
||||
|
||||
config S5PV310_SDHCI_CH2_8BIT
|
||||
bool "Channel 2 with 8-bit bus"
|
||||
help
|
||||
Support HSMMC Channel 2 8-bit bus.
|
||||
If selected, Channel 3 is disabled.
|
||||
|
||||
endmenu
|
||||
|
||||
endif
|
|
@ -1,43 +0,0 @@
|
|||
# arch/arm/mach-s5pv310/Makefile
|
||||
#
|
||||
# Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
# http://www.samsung.com/
|
||||
#
|
||||
# Licensed under GPLv2
|
||||
|
||||
obj-y :=
|
||||
obj-m :=
|
||||
obj-n :=
|
||||
obj- :=
|
||||
|
||||
# Core support for S5PV310 system
|
||||
|
||||
obj-$(CONFIG_CPU_S5PV310) += cpu.o init.o clock.o irq-combiner.o
|
||||
obj-$(CONFIG_CPU_S5PV310) += setup-i2c0.o time.o gpiolib.o irq-eint.o dma.o
|
||||
obj-$(CONFIG_CPU_FREQ) += cpufreq.o
|
||||
|
||||
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
|
||||
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
|
||||
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
|
||||
|
||||
# machine support
|
||||
|
||||
obj-$(CONFIG_MACH_SMDKC210) += mach-smdkc210.o
|
||||
obj-$(CONFIG_MACH_SMDKV310) += mach-smdkv310.o
|
||||
obj-$(CONFIG_MACH_UNIVERSAL_C210) += mach-universal_c210.o
|
||||
|
||||
# device support
|
||||
|
||||
obj-y += dev-audio.o
|
||||
obj-$(CONFIG_S5PV310_DEV_PD) += dev-pd.o
|
||||
obj-$(CONFIG_S5PV310_DEV_SYSMMU) += dev-sysmmu.o
|
||||
|
||||
obj-$(CONFIG_S5PV310_SETUP_I2C1) += setup-i2c1.o
|
||||
obj-$(CONFIG_S5PV310_SETUP_I2C2) += setup-i2c2.o
|
||||
obj-$(CONFIG_S5PV310_SETUP_I2C3) += setup-i2c3.o
|
||||
obj-$(CONFIG_S5PV310_SETUP_I2C4) += setup-i2c4.o
|
||||
obj-$(CONFIG_S5PV310_SETUP_I2C5) += setup-i2c5.o
|
||||
obj-$(CONFIG_S5PV310_SETUP_I2C6) += setup-i2c6.o
|
||||
obj-$(CONFIG_S5PV310_SETUP_I2C7) += setup-i2c7.o
|
||||
obj-$(CONFIG_S5PV310_SETUP_SDHCI) += setup-sdhci.o
|
||||
obj-$(CONFIG_S5PV310_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
|
|
@ -1,304 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv310/gpiolib.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - GPIOlib support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/irq.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#include <plat/gpio-core.h>
|
||||
#include <plat/gpio-cfg.h>
|
||||
#include <plat/gpio-cfg-helpers.h>
|
||||
|
||||
static struct s3c_gpio_cfg gpio_cfg = {
|
||||
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
static struct s3c_gpio_cfg gpio_cfg_noint = {
|
||||
.set_config = s3c_gpio_setcfg_s3c64xx_4bit,
|
||||
.set_pull = s3c_gpio_setpull_updown,
|
||||
.get_pull = s3c_gpio_getpull_updown,
|
||||
};
|
||||
|
||||
/*
|
||||
* Following are the gpio banks in v310.
|
||||
*
|
||||
* The 'config' member when left to NULL, is initialized to the default
|
||||
* structure gpio_cfg in the init function below.
|
||||
*
|
||||
* The 'base' member is also initialized in the init function below.
|
||||
* Note: The initialization of 'base' member of s3c_gpio_chip structure
|
||||
* uses the above macro and depends on the banks being listed in order here.
|
||||
*/
|
||||
static struct s3c_gpio_chip s5pv310_gpio_part1_4bit[] = {
|
||||
{
|
||||
.chip = {
|
||||
.base = S5PV310_GPA0(0),
|
||||
.ngpio = S5PV310_GPIO_A0_NR,
|
||||
.label = "GPA0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPA1(0),
|
||||
.ngpio = S5PV310_GPIO_A1_NR,
|
||||
.label = "GPA1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPB(0),
|
||||
.ngpio = S5PV310_GPIO_B_NR,
|
||||
.label = "GPB",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPC0(0),
|
||||
.ngpio = S5PV310_GPIO_C0_NR,
|
||||
.label = "GPC0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPC1(0),
|
||||
.ngpio = S5PV310_GPIO_C1_NR,
|
||||
.label = "GPC1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPD0(0),
|
||||
.ngpio = S5PV310_GPIO_D0_NR,
|
||||
.label = "GPD0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPD1(0),
|
||||
.ngpio = S5PV310_GPIO_D1_NR,
|
||||
.label = "GPD1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPE0(0),
|
||||
.ngpio = S5PV310_GPIO_E0_NR,
|
||||
.label = "GPE0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPE1(0),
|
||||
.ngpio = S5PV310_GPIO_E1_NR,
|
||||
.label = "GPE1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPE2(0),
|
||||
.ngpio = S5PV310_GPIO_E2_NR,
|
||||
.label = "GPE2",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPE3(0),
|
||||
.ngpio = S5PV310_GPIO_E3_NR,
|
||||
.label = "GPE3",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPE4(0),
|
||||
.ngpio = S5PV310_GPIO_E4_NR,
|
||||
.label = "GPE4",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPF0(0),
|
||||
.ngpio = S5PV310_GPIO_F0_NR,
|
||||
.label = "GPF0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPF1(0),
|
||||
.ngpio = S5PV310_GPIO_F1_NR,
|
||||
.label = "GPF1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPF2(0),
|
||||
.ngpio = S5PV310_GPIO_F2_NR,
|
||||
.label = "GPF2",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPF3(0),
|
||||
.ngpio = S5PV310_GPIO_F3_NR,
|
||||
.label = "GPF3",
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_gpio_chip s5pv310_gpio_part2_4bit[] = {
|
||||
{
|
||||
.chip = {
|
||||
.base = S5PV310_GPJ0(0),
|
||||
.ngpio = S5PV310_GPIO_J0_NR,
|
||||
.label = "GPJ0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPJ1(0),
|
||||
.ngpio = S5PV310_GPIO_J1_NR,
|
||||
.label = "GPJ1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPK0(0),
|
||||
.ngpio = S5PV310_GPIO_K0_NR,
|
||||
.label = "GPK0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPK1(0),
|
||||
.ngpio = S5PV310_GPIO_K1_NR,
|
||||
.label = "GPK1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPK2(0),
|
||||
.ngpio = S5PV310_GPIO_K2_NR,
|
||||
.label = "GPK2",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPK3(0),
|
||||
.ngpio = S5PV310_GPIO_K3_NR,
|
||||
.label = "GPK3",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPL0(0),
|
||||
.ngpio = S5PV310_GPIO_L0_NR,
|
||||
.label = "GPL0",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPL1(0),
|
||||
.ngpio = S5PV310_GPIO_L1_NR,
|
||||
.label = "GPL1",
|
||||
},
|
||||
}, {
|
||||
.chip = {
|
||||
.base = S5PV310_GPL2(0),
|
||||
.ngpio = S5PV310_GPIO_L2_NR,
|
||||
.label = "GPL2",
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC00),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(0),
|
||||
.chip = {
|
||||
.base = S5PV310_GPX0(0),
|
||||
.ngpio = S5PV310_GPIO_X0_NR,
|
||||
.label = "GPX0",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC20),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(8),
|
||||
.chip = {
|
||||
.base = S5PV310_GPX1(0),
|
||||
.ngpio = S5PV310_GPIO_X1_NR,
|
||||
.label = "GPX1",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC40),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(16),
|
||||
.chip = {
|
||||
.base = S5PV310_GPX2(0),
|
||||
.ngpio = S5PV310_GPIO_X2_NR,
|
||||
.label = "GPX2",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
}, {
|
||||
.base = (S5P_VA_GPIO2 + 0xC60),
|
||||
.config = &gpio_cfg_noint,
|
||||
.irq_base = IRQ_EINT(24),
|
||||
.chip = {
|
||||
.base = S5PV310_GPX3(0),
|
||||
.ngpio = S5PV310_GPIO_X3_NR,
|
||||
.label = "GPX3",
|
||||
.to_irq = samsung_gpiolib_to_irq,
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static struct s3c_gpio_chip s5pv310_gpio_part3_4bit[] = {
|
||||
{
|
||||
.chip = {
|
||||
.base = S5PV310_GPZ(0),
|
||||
.ngpio = S5PV310_GPIO_Z_NR,
|
||||
.label = "GPZ",
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static __init int s5pv310_gpiolib_init(void)
|
||||
{
|
||||
struct s3c_gpio_chip *chip;
|
||||
int i;
|
||||
int nr_chips;
|
||||
|
||||
/* GPIO part 1 */
|
||||
|
||||
chip = s5pv310_gpio_part1_4bit;
|
||||
nr_chips = ARRAY_SIZE(s5pv310_gpio_part1_4bit);
|
||||
|
||||
for (i = 0; i < nr_chips; i++, chip++) {
|
||||
if (chip->config == NULL)
|
||||
chip->config = &gpio_cfg;
|
||||
if (chip->base == NULL)
|
||||
chip->base = S5P_VA_GPIO1 + (i) * 0x20;
|
||||
}
|
||||
|
||||
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part1_4bit, nr_chips);
|
||||
|
||||
/* GPIO part 2 */
|
||||
|
||||
chip = s5pv310_gpio_part2_4bit;
|
||||
nr_chips = ARRAY_SIZE(s5pv310_gpio_part2_4bit);
|
||||
|
||||
for (i = 0; i < nr_chips; i++, chip++) {
|
||||
if (chip->config == NULL)
|
||||
chip->config = &gpio_cfg;
|
||||
if (chip->base == NULL)
|
||||
chip->base = S5P_VA_GPIO2 + (i) * 0x20;
|
||||
}
|
||||
|
||||
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part2_4bit, nr_chips);
|
||||
|
||||
/* GPIO part 3 */
|
||||
|
||||
chip = s5pv310_gpio_part3_4bit;
|
||||
nr_chips = ARRAY_SIZE(s5pv310_gpio_part3_4bit);
|
||||
|
||||
for (i = 0; i < nr_chips; i++, chip++) {
|
||||
if (chip->config == NULL)
|
||||
chip->config = &gpio_cfg;
|
||||
if (chip->base == NULL)
|
||||
chip->base = S5P_VA_GPIO3 + (i) * 0x20;
|
||||
}
|
||||
|
||||
samsung_gpiolib_add_4bit_chips(s5pv310_gpio_part3_4bit, nr_chips);
|
||||
|
||||
return 0;
|
||||
}
|
||||
core_initcall(s5pv310_gpiolib_init);
|
|
@ -1,135 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/gpio.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5PV310 - GPIO lib support
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_GPIO_H
|
||||
#define __ASM_ARCH_GPIO_H __FILE__
|
||||
|
||||
#define gpio_get_value __gpio_get_value
|
||||
#define gpio_set_value __gpio_set_value
|
||||
#define gpio_cansleep __gpio_cansleep
|
||||
#define gpio_to_irq __gpio_to_irq
|
||||
|
||||
/* Practically, GPIO banks upto GPZ are the configurable gpio banks */
|
||||
|
||||
/* GPIO bank sizes */
|
||||
#define S5PV310_GPIO_A0_NR (8)
|
||||
#define S5PV310_GPIO_A1_NR (6)
|
||||
#define S5PV310_GPIO_B_NR (8)
|
||||
#define S5PV310_GPIO_C0_NR (5)
|
||||
#define S5PV310_GPIO_C1_NR (5)
|
||||
#define S5PV310_GPIO_D0_NR (4)
|
||||
#define S5PV310_GPIO_D1_NR (4)
|
||||
#define S5PV310_GPIO_E0_NR (5)
|
||||
#define S5PV310_GPIO_E1_NR (8)
|
||||
#define S5PV310_GPIO_E2_NR (6)
|
||||
#define S5PV310_GPIO_E3_NR (8)
|
||||
#define S5PV310_GPIO_E4_NR (8)
|
||||
#define S5PV310_GPIO_F0_NR (8)
|
||||
#define S5PV310_GPIO_F1_NR (8)
|
||||
#define S5PV310_GPIO_F2_NR (8)
|
||||
#define S5PV310_GPIO_F3_NR (6)
|
||||
#define S5PV310_GPIO_J0_NR (8)
|
||||
#define S5PV310_GPIO_J1_NR (5)
|
||||
#define S5PV310_GPIO_K0_NR (7)
|
||||
#define S5PV310_GPIO_K1_NR (7)
|
||||
#define S5PV310_GPIO_K2_NR (7)
|
||||
#define S5PV310_GPIO_K3_NR (7)
|
||||
#define S5PV310_GPIO_L0_NR (8)
|
||||
#define S5PV310_GPIO_L1_NR (3)
|
||||
#define S5PV310_GPIO_L2_NR (8)
|
||||
#define S5PV310_GPIO_X0_NR (8)
|
||||
#define S5PV310_GPIO_X1_NR (8)
|
||||
#define S5PV310_GPIO_X2_NR (8)
|
||||
#define S5PV310_GPIO_X3_NR (8)
|
||||
#define S5PV310_GPIO_Z_NR (7)
|
||||
|
||||
/* GPIO bank numbers */
|
||||
|
||||
#define S5PV310_GPIO_NEXT(__gpio) \
|
||||
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
|
||||
|
||||
enum s5p_gpio_number {
|
||||
S5PV310_GPIO_A0_START = 0,
|
||||
S5PV310_GPIO_A1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A0),
|
||||
S5PV310_GPIO_B_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_A1),
|
||||
S5PV310_GPIO_C0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_B),
|
||||
S5PV310_GPIO_C1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C0),
|
||||
S5PV310_GPIO_D0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_C1),
|
||||
S5PV310_GPIO_D1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D0),
|
||||
S5PV310_GPIO_E0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_D1),
|
||||
S5PV310_GPIO_E1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E0),
|
||||
S5PV310_GPIO_E2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E1),
|
||||
S5PV310_GPIO_E3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E2),
|
||||
S5PV310_GPIO_E4_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E3),
|
||||
S5PV310_GPIO_F0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_E4),
|
||||
S5PV310_GPIO_F1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F0),
|
||||
S5PV310_GPIO_F2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F1),
|
||||
S5PV310_GPIO_F3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F2),
|
||||
S5PV310_GPIO_J0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_F3),
|
||||
S5PV310_GPIO_J1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J0),
|
||||
S5PV310_GPIO_K0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_J1),
|
||||
S5PV310_GPIO_K1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K0),
|
||||
S5PV310_GPIO_K2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K1),
|
||||
S5PV310_GPIO_K3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K2),
|
||||
S5PV310_GPIO_L0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_K3),
|
||||
S5PV310_GPIO_L1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L0),
|
||||
S5PV310_GPIO_L2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L1),
|
||||
S5PV310_GPIO_X0_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_L2),
|
||||
S5PV310_GPIO_X1_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X0),
|
||||
S5PV310_GPIO_X2_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X1),
|
||||
S5PV310_GPIO_X3_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X2),
|
||||
S5PV310_GPIO_Z_START = S5PV310_GPIO_NEXT(S5PV310_GPIO_X3),
|
||||
};
|
||||
|
||||
/* S5PV310 GPIO number definitions */
|
||||
#define S5PV310_GPA0(_nr) (S5PV310_GPIO_A0_START + (_nr))
|
||||
#define S5PV310_GPA1(_nr) (S5PV310_GPIO_A1_START + (_nr))
|
||||
#define S5PV310_GPB(_nr) (S5PV310_GPIO_B_START + (_nr))
|
||||
#define S5PV310_GPC0(_nr) (S5PV310_GPIO_C0_START + (_nr))
|
||||
#define S5PV310_GPC1(_nr) (S5PV310_GPIO_C1_START + (_nr))
|
||||
#define S5PV310_GPD0(_nr) (S5PV310_GPIO_D0_START + (_nr))
|
||||
#define S5PV310_GPD1(_nr) (S5PV310_GPIO_D1_START + (_nr))
|
||||
#define S5PV310_GPE0(_nr) (S5PV310_GPIO_E0_START + (_nr))
|
||||
#define S5PV310_GPE1(_nr) (S5PV310_GPIO_E1_START + (_nr))
|
||||
#define S5PV310_GPE2(_nr) (S5PV310_GPIO_E2_START + (_nr))
|
||||
#define S5PV310_GPE3(_nr) (S5PV310_GPIO_E3_START + (_nr))
|
||||
#define S5PV310_GPE4(_nr) (S5PV310_GPIO_E4_START + (_nr))
|
||||
#define S5PV310_GPF0(_nr) (S5PV310_GPIO_F0_START + (_nr))
|
||||
#define S5PV310_GPF1(_nr) (S5PV310_GPIO_F1_START + (_nr))
|
||||
#define S5PV310_GPF2(_nr) (S5PV310_GPIO_F2_START + (_nr))
|
||||
#define S5PV310_GPF3(_nr) (S5PV310_GPIO_F3_START + (_nr))
|
||||
#define S5PV310_GPJ0(_nr) (S5PV310_GPIO_J0_START + (_nr))
|
||||
#define S5PV310_GPJ1(_nr) (S5PV310_GPIO_J1_START + (_nr))
|
||||
#define S5PV310_GPK0(_nr) (S5PV310_GPIO_K0_START + (_nr))
|
||||
#define S5PV310_GPK1(_nr) (S5PV310_GPIO_K1_START + (_nr))
|
||||
#define S5PV310_GPK2(_nr) (S5PV310_GPIO_K2_START + (_nr))
|
||||
#define S5PV310_GPK3(_nr) (S5PV310_GPIO_K3_START + (_nr))
|
||||
#define S5PV310_GPL0(_nr) (S5PV310_GPIO_L0_START + (_nr))
|
||||
#define S5PV310_GPL1(_nr) (S5PV310_GPIO_L1_START + (_nr))
|
||||
#define S5PV310_GPL2(_nr) (S5PV310_GPIO_L2_START + (_nr))
|
||||
#define S5PV310_GPX0(_nr) (S5PV310_GPIO_X0_START + (_nr))
|
||||
#define S5PV310_GPX1(_nr) (S5PV310_GPIO_X1_START + (_nr))
|
||||
#define S5PV310_GPX2(_nr) (S5PV310_GPIO_X2_START + (_nr))
|
||||
#define S5PV310_GPX3(_nr) (S5PV310_GPIO_X3_START + (_nr))
|
||||
#define S5PV310_GPZ(_nr) (S5PV310_GPIO_Z_START + (_nr))
|
||||
|
||||
/* the end of the S5PV310 specific gpios */
|
||||
#define S5PV310_GPIO_END (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + 1)
|
||||
#define S3C_GPIO_END S5PV310_GPIO_END
|
||||
|
||||
/* define the number of gpios we need to the one after the GPZ() range */
|
||||
#define ARCH_NR_GPIOS (S5PV310_GPZ(S5PV310_GPIO_Z_NR) + \
|
||||
CONFIG_SAMSUNG_GPIO_EXTRA + 1)
|
||||
|
||||
#include <asm-generic/gpio.h>
|
||||
|
||||
#endif /* __ASM_ARCH_GPIO_H */
|
|
@ -1,144 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/map.h
|
||||
*
|
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* S5PV310 - Memory map definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_MAP_H
|
||||
#define __ASM_ARCH_MAP_H __FILE__
|
||||
|
||||
#include <plat/map-base.h>
|
||||
|
||||
/*
|
||||
* S5PV310 UART offset is 0x10000 but the older S5P SoCs are 0x400.
|
||||
* So need to define it, and here is to avoid redefinition warning.
|
||||
*/
|
||||
#define S3C_UART_OFFSET (0x10000)
|
||||
|
||||
#include <plat/map-s5p.h>
|
||||
|
||||
#define S5PV310_PA_SYSRAM 0x02025000
|
||||
|
||||
#define S5PV310_PA_I2S0 0x03830000
|
||||
#define S5PV310_PA_I2S1 0xE3100000
|
||||
#define S5PV310_PA_I2S2 0xE2A00000
|
||||
|
||||
#define S5PV310_PA_PCM0 0x03840000
|
||||
#define S5PV310_PA_PCM1 0x13980000
|
||||
#define S5PV310_PA_PCM2 0x13990000
|
||||
|
||||
#define S5PV310_PA_SROM_BANK(x) (0x04000000 + ((x) * 0x01000000))
|
||||
|
||||
#define S5PC210_PA_ONENAND 0x0C000000
|
||||
#define S5PC210_PA_ONENAND_DMA 0x0C600000
|
||||
|
||||
#define S5PV310_PA_CHIPID 0x10000000
|
||||
|
||||
#define S5PV310_PA_SYSCON 0x10010000
|
||||
#define S5PV310_PA_PMU 0x10020000
|
||||
#define S5PV310_PA_CMU 0x10030000
|
||||
|
||||
#define S5PV310_PA_WATCHDOG 0x10060000
|
||||
#define S5PV310_PA_RTC 0x10070000
|
||||
|
||||
#define S5PV310_PA_DMC0 0x10400000
|
||||
|
||||
#define S5PV310_PA_COMBINER 0x10448000
|
||||
|
||||
#define S5PV310_PA_COREPERI 0x10500000
|
||||
#define S5PV310_PA_GIC_CPU 0x10500100
|
||||
#define S5PV310_PA_TWD 0x10500600
|
||||
#define S5PV310_PA_GIC_DIST 0x10501000
|
||||
#define S5PV310_PA_L2CC 0x10502000
|
||||
|
||||
#define S5PV310_PA_MDMA 0x10810000
|
||||
#define S5PV310_PA_PDMA0 0x12680000
|
||||
#define S5PV310_PA_PDMA1 0x12690000
|
||||
|
||||
#define S5PV310_PA_SYSMMU_MDMA 0x10A40000
|
||||
#define S5PV310_PA_SYSMMU_SSS 0x10A50000
|
||||
#define S5PV310_PA_SYSMMU_FIMC0 0x11A20000
|
||||
#define S5PV310_PA_SYSMMU_FIMC1 0x11A30000
|
||||
#define S5PV310_PA_SYSMMU_FIMC2 0x11A40000
|
||||
#define S5PV310_PA_SYSMMU_FIMC3 0x11A50000
|
||||
#define S5PV310_PA_SYSMMU_JPEG 0x11A60000
|
||||
#define S5PV310_PA_SYSMMU_FIMD0 0x11E20000
|
||||
#define S5PV310_PA_SYSMMU_FIMD1 0x12220000
|
||||
#define S5PV310_PA_SYSMMU_PCIe 0x12620000
|
||||
#define S5PV310_PA_SYSMMU_G2D 0x12A20000
|
||||
#define S5PV310_PA_SYSMMU_ROTATOR 0x12A30000
|
||||
#define S5PV310_PA_SYSMMU_MDMA2 0x12A40000
|
||||
#define S5PV310_PA_SYSMMU_TV 0x12E20000
|
||||
#define S5PV310_PA_SYSMMU_MFC_L 0x13620000
|
||||
#define S5PV310_PA_SYSMMU_MFC_R 0x13630000
|
||||
|
||||
#define S5PV310_PA_GPIO1 0x11400000
|
||||
#define S5PV310_PA_GPIO2 0x11000000
|
||||
#define S5PV310_PA_GPIO3 0x03860000
|
||||
|
||||
#define S5PV310_PA_MIPI_CSIS0 0x11880000
|
||||
#define S5PV310_PA_MIPI_CSIS1 0x11890000
|
||||
|
||||
#define S5PV310_PA_HSMMC(x) (0x12510000 + ((x) * 0x10000))
|
||||
|
||||
#define S5PV310_PA_SROMC 0x12570000
|
||||
|
||||
#define S5PV310_PA_UART 0x13800000
|
||||
|
||||
#define S5PV310_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
|
||||
|
||||
#define S5PV310_PA_AC97 0x139A0000
|
||||
|
||||
#define S5PV310_PA_TIMER 0x139D0000
|
||||
|
||||
#define S5PV310_PA_SDRAM 0x40000000
|
||||
|
||||
#define S5PV310_PA_SPDIF 0xE1100000
|
||||
|
||||
/* Compatibiltiy Defines */
|
||||
|
||||
#define S3C_PA_HSMMC0 S5PV310_PA_HSMMC(0)
|
||||
#define S3C_PA_HSMMC1 S5PV310_PA_HSMMC(1)
|
||||
#define S3C_PA_HSMMC2 S5PV310_PA_HSMMC(2)
|
||||
#define S3C_PA_HSMMC3 S5PV310_PA_HSMMC(3)
|
||||
#define S3C_PA_IIC S5PV310_PA_IIC(0)
|
||||
#define S3C_PA_IIC1 S5PV310_PA_IIC(1)
|
||||
#define S3C_PA_IIC2 S5PV310_PA_IIC(2)
|
||||
#define S3C_PA_IIC3 S5PV310_PA_IIC(3)
|
||||
#define S3C_PA_IIC4 S5PV310_PA_IIC(4)
|
||||
#define S3C_PA_IIC5 S5PV310_PA_IIC(5)
|
||||
#define S3C_PA_IIC6 S5PV310_PA_IIC(6)
|
||||
#define S3C_PA_IIC7 S5PV310_PA_IIC(7)
|
||||
#define S3C_PA_RTC S5PV310_PA_RTC
|
||||
#define S3C_PA_WDT S5PV310_PA_WATCHDOG
|
||||
|
||||
#define S5P_PA_CHIPID S5PV310_PA_CHIPID
|
||||
#define S5P_PA_MIPI_CSIS0 S5PV310_PA_MIPI_CSIS0
|
||||
#define S5P_PA_MIPI_CSIS1 S5PV310_PA_MIPI_CSIS1
|
||||
#define S5P_PA_ONENAND S5PC210_PA_ONENAND
|
||||
#define S5P_PA_ONENAND_DMA S5PC210_PA_ONENAND_DMA
|
||||
#define S5P_PA_SDRAM S5PV310_PA_SDRAM
|
||||
#define S5P_PA_SROMC S5PV310_PA_SROMC
|
||||
#define S5P_PA_SYSCON S5PV310_PA_SYSCON
|
||||
#define S5P_PA_TIMER S5PV310_PA_TIMER
|
||||
|
||||
/* UART */
|
||||
|
||||
#define S3C_PA_UART S5PV310_PA_UART
|
||||
|
||||
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
|
||||
#define S5P_PA_UART0 S5P_PA_UART(0)
|
||||
#define S5P_PA_UART1 S5P_PA_UART(1)
|
||||
#define S5P_PA_UART2 S5P_PA_UART(2)
|
||||
#define S5P_PA_UART3 S5P_PA_UART(3)
|
||||
#define S5P_PA_UART4 S5P_PA_UART(4)
|
||||
|
||||
#define S5P_SZ_UART SZ_256
|
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */
|
|
@ -1,42 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/regs-gpio.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - GPIO (including EINT) register definitions
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_GPIO_H
|
||||
#define __ASM_ARCH_REGS_GPIO_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
#include <mach/irqs.h>
|
||||
|
||||
#define S5PV310_EINT40CON (S5P_VA_GPIO2 + 0xE00)
|
||||
#define S5P_EINT_CON(x) (S5PV310_EINT40CON + ((x) * 0x4))
|
||||
|
||||
#define S5PV310_EINT40FLTCON0 (S5P_VA_GPIO2 + 0xE80)
|
||||
#define S5P_EINT_FLTCON(x) (S5PV310_EINT40FLTCON0 + ((x) * 0x4))
|
||||
|
||||
#define S5PV310_EINT40MASK (S5P_VA_GPIO2 + 0xF00)
|
||||
#define S5P_EINT_MASK(x) (S5PV310_EINT40MASK + ((x) * 0x4))
|
||||
|
||||
#define S5PV310_EINT40PEND (S5P_VA_GPIO2 + 0xF40)
|
||||
#define S5P_EINT_PEND(x) (S5PV310_EINT40PEND + ((x) * 0x4))
|
||||
|
||||
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
|
||||
|
||||
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
|
||||
|
||||
#define EINT_MODE S3C_GPIO_SFN(0xf)
|
||||
|
||||
#define EINT_GPIO_0(x) S5PV310_GPX0(x)
|
||||
#define EINT_GPIO_1(x) S5PV310_GPX1(x)
|
||||
#define EINT_GPIO_2(x) S5PV310_GPX2(x)
|
||||
#define EINT_GPIO_3(x) S5PV310_GPX3(x)
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_GPIO_H */
|
|
@ -1,30 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/regs-pmu.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com
|
||||
*
|
||||
* S5PV310 - Power management unit definition
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARCH_REGS_PMU_H
|
||||
#define __ASM_ARCH_REGS_PMU_H __FILE__
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
#define S5P_PMUREG(x) (S5P_VA_PMU + (x))
|
||||
|
||||
#define S5P_PMU_CAM_CONF S5P_PMUREG(0x3C00)
|
||||
#define S5P_PMU_TV_CONF S5P_PMUREG(0x3C20)
|
||||
#define S5P_PMU_MFC_CONF S5P_PMUREG(0x3C40)
|
||||
#define S5P_PMU_G3D_CONF S5P_PMUREG(0x3C60)
|
||||
#define S5P_PMU_LCD0_CONF S5P_PMUREG(0x3C80)
|
||||
#define S5P_PMU_LCD1_CONF S5P_PMUREG(0x3CA0)
|
||||
#define S5P_PMU_GPS_CONF S5P_PMUREG(0x3CE0)
|
||||
|
||||
#define S5P_INT_LOCAL_PWR_EN 0x7
|
||||
|
||||
#endif /* __ASM_ARCH_REGS_PMU_H */
|
|
@ -1,122 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv310/include/mach/sysmmu.h
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
* http://www.samsung.com/
|
||||
*
|
||||
* Samsung sysmmu driver for S5PV310
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_ARM_ARCH_SYSMMU_H
|
||||
#define __ASM_ARM_ARCH_SYSMMU_H __FILE__
|
||||
|
||||
#define S5PV310_SYSMMU_TOTAL_IPNUM 16
|
||||
#define S5P_SYSMMU_TOTAL_IPNUM S5PV310_SYSMMU_TOTAL_IPNUM
|
||||
|
||||
enum s5pv310_sysmmu_ips {
|
||||
SYSMMU_MDMA,
|
||||
SYSMMU_SSS,
|
||||
SYSMMU_FIMC0,
|
||||
SYSMMU_FIMC1,
|
||||
SYSMMU_FIMC2,
|
||||
SYSMMU_FIMC3,
|
||||
SYSMMU_JPEG,
|
||||
SYSMMU_FIMD0,
|
||||
SYSMMU_FIMD1,
|
||||
SYSMMU_PCIe,
|
||||
SYSMMU_G2D,
|
||||
SYSMMU_ROTATOR,
|
||||
SYSMMU_MDMA2,
|
||||
SYSMMU_TV,
|
||||
SYSMMU_MFC_L,
|
||||
SYSMMU_MFC_R,
|
||||
};
|
||||
|
||||
static char *sysmmu_ips_name[S5PV310_SYSMMU_TOTAL_IPNUM] = {
|
||||
"SYSMMU_MDMA" ,
|
||||
"SYSMMU_SSS" ,
|
||||
"SYSMMU_FIMC0" ,
|
||||
"SYSMMU_FIMC1" ,
|
||||
"SYSMMU_FIMC2" ,
|
||||
"SYSMMU_FIMC3" ,
|
||||
"SYSMMU_JPEG" ,
|
||||
"SYSMMU_FIMD0" ,
|
||||
"SYSMMU_FIMD1" ,
|
||||
"SYSMMU_PCIe" ,
|
||||
"SYSMMU_G2D" ,
|
||||
"SYSMMU_ROTATOR",
|
||||
"SYSMMU_MDMA2" ,
|
||||
"SYSMMU_TV" ,
|
||||
"SYSMMU_MFC_L" ,
|
||||
"SYSMMU_MFC_R" ,
|
||||
};
|
||||
|
||||
typedef enum s5pv310_sysmmu_ips sysmmu_ips;
|
||||
|
||||
struct sysmmu_tt_info {
|
||||
unsigned long *pgd;
|
||||
unsigned long pgd_paddr;
|
||||
unsigned long *pte;
|
||||
};
|
||||
|
||||
struct sysmmu_controller {
|
||||
const char *name;
|
||||
|
||||
/* channels registers */
|
||||
void __iomem *regs;
|
||||
|
||||
/* channel irq */
|
||||
unsigned int irq;
|
||||
|
||||
sysmmu_ips ips;
|
||||
|
||||
/* Translation Table Info. */
|
||||
struct sysmmu_tt_info *tt_info;
|
||||
|
||||
struct resource *mem;
|
||||
struct device *dev;
|
||||
|
||||
/* SysMMU controller enable - true : enable */
|
||||
bool enable;
|
||||
};
|
||||
|
||||
/**
|
||||
* s5p_sysmmu_enable() - enable system mmu of ip
|
||||
* @ips: The ip connected system mmu.
|
||||
*
|
||||
* This function enable system mmu to transfer address
|
||||
* from virtual address to physical address
|
||||
*/
|
||||
int s5p_sysmmu_enable(sysmmu_ips ips);
|
||||
|
||||
/**
|
||||
* s5p_sysmmu_disable() - disable sysmmu mmu of ip
|
||||
* @ips: The ip connected system mmu.
|
||||
*
|
||||
* This function disable system mmu to transfer address
|
||||
* from virtual address to physical address
|
||||
*/
|
||||
int s5p_sysmmu_disable(sysmmu_ips ips);
|
||||
|
||||
/**
|
||||
* s5p_sysmmu_set_tablebase_pgd() - set page table base address to refer page table
|
||||
* @ips: The ip connected system mmu.
|
||||
* @pgd: The page table base address.
|
||||
*
|
||||
* This function set page table base address
|
||||
* When system mmu transfer address from virtaul address to physical address,
|
||||
* system mmu refer address information from page table
|
||||
*/
|
||||
int s5p_sysmmu_set_tablebase_pgd(sysmmu_ips ips, unsigned long pgd);
|
||||
|
||||
/**
|
||||
* s5p_sysmmu_tlb_invalidate() - flush all TLB entry in system mmu
|
||||
* @ips: The ip connected system mmu.
|
||||
*
|
||||
* This function flush all TLB entry in system mmu
|
||||
*/
|
||||
int s5p_sysmmu_tlb_invalidate(sysmmu_ips ips);
|
||||
#endif /* __ASM_ARM_ARCH_SYSMMU_H */
|
|
@ -1,237 +0,0 @@
|
|||
/* linux/arch/arm/mach-s5pv310/mach-universal_c210.c
|
||||
*
|
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/serial_core.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/gpio_keys.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/regulator/machine.h>
|
||||
#include <linux/regulator/fixed.h>
|
||||
#include <linux/mmc/host.h>
|
||||
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
||||
#include <plat/regs-serial.h>
|
||||
#include <plat/s5pv310.h>
|
||||
#include <plat/cpu.h>
|
||||
#include <plat/devs.h>
|
||||
#include <plat/sdhci.h>
|
||||
|
||||
#include <mach/map.h>
|
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */
|
||||
#define UNIVERSAL_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
|
||||
S3C2410_UCON_RXILEVEL | \
|
||||
S3C2410_UCON_TXIRQMODE | \
|
||||
S3C2410_UCON_RXIRQMODE | \
|
||||
S3C2410_UCON_RXFIFO_TOI | \
|
||||
S3C2443_UCON_RXERR_IRQEN)
|
||||
|
||||
#define UNIVERSAL_ULCON_DEFAULT S3C2410_LCON_CS8
|
||||
|
||||
#define UNIVERSAL_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
|
||||
S5PV210_UFCON_TXTRIG256 | \
|
||||
S5PV210_UFCON_RXTRIG256)
|
||||
|
||||
static struct s3c2410_uartcfg universal_uartcfgs[] __initdata = {
|
||||
[0] = {
|
||||
.hwport = 0,
|
||||
.ucon = UNIVERSAL_UCON_DEFAULT,
|
||||
.ulcon = UNIVERSAL_ULCON_DEFAULT,
|
||||
.ufcon = UNIVERSAL_UFCON_DEFAULT,
|
||||
},
|
||||
[1] = {
|
||||
.hwport = 1,
|
||||
.ucon = UNIVERSAL_UCON_DEFAULT,
|
||||
.ulcon = UNIVERSAL_ULCON_DEFAULT,
|
||||
.ufcon = UNIVERSAL_UFCON_DEFAULT,
|
||||
},
|
||||
[2] = {
|
||||
.hwport = 2,
|
||||
.ucon = UNIVERSAL_UCON_DEFAULT,
|
||||
.ulcon = UNIVERSAL_ULCON_DEFAULT,
|
||||
.ufcon = UNIVERSAL_UFCON_DEFAULT,
|
||||
},
|
||||
[3] = {
|
||||
.hwport = 3,
|
||||
.ucon = UNIVERSAL_UCON_DEFAULT,
|
||||
.ulcon = UNIVERSAL_ULCON_DEFAULT,
|
||||
.ufcon = UNIVERSAL_UFCON_DEFAULT,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_button universal_gpio_keys_tables[] = {
|
||||
{
|
||||
.code = KEY_VOLUMEUP,
|
||||
.gpio = S5PV310_GPX2(0), /* XEINT16 */
|
||||
.desc = "gpio-keys: KEY_VOLUMEUP",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_VOLUMEDOWN,
|
||||
.gpio = S5PV310_GPX2(1), /* XEINT17 */
|
||||
.desc = "gpio-keys: KEY_VOLUMEDOWN",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_CONFIG,
|
||||
.gpio = S5PV310_GPX2(2), /* XEINT18 */
|
||||
.desc = "gpio-keys: KEY_CONFIG",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_CAMERA,
|
||||
.gpio = S5PV310_GPX2(3), /* XEINT19 */
|
||||
.desc = "gpio-keys: KEY_CAMERA",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
}, {
|
||||
.code = KEY_OK,
|
||||
.gpio = S5PV310_GPX3(5), /* XEINT29 */
|
||||
.desc = "gpio-keys: KEY_OK",
|
||||
.type = EV_KEY,
|
||||
.active_low = 1,
|
||||
.debounce_interval = 1,
|
||||
},
|
||||
};
|
||||
|
||||
static struct gpio_keys_platform_data universal_gpio_keys_data = {
|
||||
.buttons = universal_gpio_keys_tables,
|
||||
.nbuttons = ARRAY_SIZE(universal_gpio_keys_tables),
|
||||
};
|
||||
|
||||
static struct platform_device universal_gpio_keys = {
|
||||
.name = "gpio-keys",
|
||||
.dev = {
|
||||
.platform_data = &universal_gpio_keys_data,
|
||||
},
|
||||
};
|
||||
|
||||
/* eMMC */
|
||||
static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
|
||||
.max_width = 8,
|
||||
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_DISABLE),
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
static struct regulator_consumer_supply mmc0_supplies[] = {
|
||||
REGULATOR_SUPPLY("vmmc", "s3c-sdhci.0"),
|
||||
};
|
||||
|
||||
static struct regulator_init_data mmc0_fixed_voltage_init_data = {
|
||||
.constraints = {
|
||||
.name = "VMEM_VDD_2.8V",
|
||||
.valid_ops_mask = REGULATOR_CHANGE_STATUS,
|
||||
},
|
||||
.num_consumer_supplies = ARRAY_SIZE(mmc0_supplies),
|
||||
.consumer_supplies = mmc0_supplies,
|
||||
};
|
||||
|
||||
static struct fixed_voltage_config mmc0_fixed_voltage_config = {
|
||||
.supply_name = "MASSMEMORY_EN",
|
||||
.microvolts = 2800000,
|
||||
.gpio = S5PV310_GPE1(3),
|
||||
.enable_high = true,
|
||||
.init_data = &mmc0_fixed_voltage_init_data,
|
||||
};
|
||||
|
||||
static struct platform_device mmc0_fixed_voltage = {
|
||||
.name = "reg-fixed-voltage",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &mmc0_fixed_voltage_config,
|
||||
},
|
||||
};
|
||||
|
||||
/* SD */
|
||||
static struct s3c_sdhci_platdata universal_hsmmc2_data __initdata = {
|
||||
.max_width = 4,
|
||||
.host_caps = MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_DISABLE,
|
||||
.ext_cd_gpio = S5PV310_GPX3(4), /* XEINT_28 */
|
||||
.ext_cd_gpio_invert = 1,
|
||||
.cd_type = S3C_SDHCI_CD_GPIO,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
||||
/* WiFi */
|
||||
static struct s3c_sdhci_platdata universal_hsmmc3_data __initdata = {
|
||||
.max_width = 4,
|
||||
.host_caps = MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_DISABLE,
|
||||
.cd_type = S3C_SDHCI_CD_EXTERNAL,
|
||||
};
|
||||
|
||||
static void __init universal_sdhci_init(void)
|
||||
{
|
||||
s3c_sdhci0_set_platdata(&universal_hsmmc0_data);
|
||||
s3c_sdhci2_set_platdata(&universal_hsmmc2_data);
|
||||
s3c_sdhci3_set_platdata(&universal_hsmmc3_data);
|
||||
}
|
||||
|
||||
/* I2C0 */
|
||||
static struct i2c_board_info i2c0_devs[] __initdata = {
|
||||
/* Camera, To be updated */
|
||||
};
|
||||
|
||||
/* I2C1 */
|
||||
static struct i2c_board_info i2c1_devs[] __initdata = {
|
||||
/* Gyro, To be updated */
|
||||
};
|
||||
|
||||
static struct platform_device *universal_devices[] __initdata = {
|
||||
/* Samsung Platform Devices */
|
||||
&mmc0_fixed_voltage,
|
||||
&s3c_device_hsmmc0,
|
||||
&s3c_device_hsmmc2,
|
||||
&s3c_device_hsmmc3,
|
||||
|
||||
/* Universal Devices */
|
||||
&universal_gpio_keys,
|
||||
&s5p_device_onenand,
|
||||
};
|
||||
|
||||
static void __init universal_map_io(void)
|
||||
{
|
||||
s5p_init_io(NULL, 0, S5P_VA_CHIPID);
|
||||
s3c24xx_init_clocks(24000000);
|
||||
s3c24xx_init_uarts(universal_uartcfgs, ARRAY_SIZE(universal_uartcfgs));
|
||||
}
|
||||
|
||||
static void __init universal_machine_init(void)
|
||||
{
|
||||
universal_sdhci_init();
|
||||
|
||||
i2c_register_board_info(0, i2c0_devs, ARRAY_SIZE(i2c0_devs));
|
||||
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
|
||||
|
||||
/* Last */
|
||||
platform_add_devices(universal_devices, ARRAY_SIZE(universal_devices));
|
||||
}
|
||||
|
||||
MACHINE_START(UNIVERSAL_C210, "UNIVERSAL_C210")
|
||||
/* Maintainer: Kyungmin Park <kyungmin.park@samsung.com> */
|
||||
.boot_params = S5P_PA_SDRAM + 0x100,
|
||||
.init_irq = s5pv310_init_irq,
|
||||
.map_io = universal_map_io,
|
||||
.init_machine = universal_machine_init,
|
||||
.timer = &s5pv310_timer,
|
||||
MACHINE_END
|
|
@ -812,7 +812,7 @@ config CACHE_L2X0
|
|||
bool "Enable the L2x0 outer cache controller"
|
||||
depends on REALVIEW_EB_ARM11MP || MACH_REALVIEW_PB11MP || MACH_REALVIEW_PB1176 || \
|
||||
REALVIEW_EB_A9MP || SOC_IMX35 || SOC_IMX31 || MACH_REALVIEW_PBX || \
|
||||
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_S5PV310 || ARCH_TEGRA || \
|
||||
ARCH_NOMADIK || ARCH_OMAP4 || ARCH_EXYNOS4 || ARCH_TEGRA || \
|
||||
ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || ARCH_SHMOBILE
|
||||
default y
|
||||
select OUTER_CACHE
|
||||
|
|
|
@ -56,13 +56,6 @@ config S3C24XX_DCLK
|
|||
help
|
||||
Clock code for supporting DCLK/CLKOUT on S3C24XX architectures
|
||||
|
||||
config S3C24XX_PWM
|
||||
bool "PWM device support"
|
||||
select HAVE_PWM
|
||||
help
|
||||
Support for exporting the PWM timer blocks via the pwm device
|
||||
system.
|
||||
|
||||
# gpio configurations
|
||||
|
||||
config S3C24XX_GPIO_EXTRA
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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Reference in a new issue