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cxl: read PHB indications from the device tree 

Configure the P9 XSL_DSNCTL register with PHB indications found
in the device tree, or else use legacy hard-coded values.

Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Philippe Bergheaud 2018-03-02 10:56:12 +01:00 committed by Michael Ellerman
parent d6a90bb83b
commit 9dbcbfa1fe
3 changed files with 45 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/misc/cxl/cxl.h
View File

@ -1069,7 +1069,7 @@ int cxl_psl_purge(struct cxl_afu *afu);
int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
u32 *phb_index, u64 *capp_unit_id);
int cxl_slot_is_switched(struct pci_dev *dev);
int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg);
int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg);
u64 cxl_calculate_sr(bool master, bool kernel, bool real_mode, bool p9);
void cxl_native_irq_dump_regs_psl9(struct cxl_context *ctx);

2
drivers/misc/cxl/cxllib.c
View File

@ -99,7 +99,7 @@ int cxllib_get_xsl_config(struct pci_dev *dev, struct cxllib_xsl_config *cfg)
if (rc)
return rc;
rc = cxl_get_xsl9_dsnctl(capp_unit_id, &cfg->dsnctl);
rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &cfg->dsnctl);
if (rc)
return rc;
if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {

48
drivers/misc/cxl/pci.c
View File

@ -407,21 +407,59 @@ int cxl_calc_capp_routing(struct pci_dev *dev, u64 *chipid,
return 0;
}
int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg)
static DEFINE_MUTEX(indications_mutex);
static int get_phb_indications(struct pci_dev *dev, u64 *capiind, u64 *asnind,
u64 *nbwind)
{
static u64 nbw, asn, capi = 0;
struct device_node *np;
const __be32 *prop;
mutex_lock(&indications_mutex);
if (!capi) {
if (!(np = pnv_pci_get_phb_node(dev))) {
mutex_unlock(&indications_mutex);
return -ENODEV;
}
prop = of_get_property(np, "ibm,phb-indications", NULL);
if (!prop) {
nbw = 0x0300UL; /* legacy values */
asn = 0x0400UL;
capi = 0x0200UL;
} else {
nbw = (u64)be32_to_cpu(prop[2]);
asn = (u64)be32_to_cpu(prop[1]);
capi = (u64)be32_to_cpu(prop[0]);
}
of_node_put(np);
}
*capiind = capi;
*asnind = asn;
*nbwind = nbw;
mutex_unlock(&indications_mutex);
return 0;
}
int cxl_get_xsl9_dsnctl(struct pci_dev *dev, u64 capp_unit_id, u64 *reg)
{
u64 xsl_dsnctl;
u64 capiind, asnind, nbwind;
/*
* CAPI Identifier bits [0:7]
* bit 61:60 MSI bits --> 0
* bit 59 TVT selector --> 0
*/
if (get_phb_indications(dev, &capiind, &asnind, &nbwind))
return -ENODEV;
/*
* Tell XSL where to route data to.
* The field chipid should match the PHB CAPI_CMPM register
*/
xsl_dsnctl = ((u64)0x2 << (63-7)); /* Bit 57 */
xsl_dsnctl = (capiind << (63-15)); /* Bit 57 */
xsl_dsnctl |= (capp_unit_id << (63-15));
/* nMMU_ID Defaults to: b’000001001’*/
@ -435,14 +473,14 @@ int cxl_get_xsl9_dsnctl(u64 capp_unit_id, u64 *reg)
* nbwind=0x03, bits [57:58], must include capi indicator.
* Not supported on P9 DD1.
*/
xsl_dsnctl |= ((u64)0x03 << (63-47));
xsl_dsnctl |= (nbwind << (63-55));
/*
* Upper 16b address bits of ASB_Notify messages sent to the
* system. Need to match the PHB’s ASN Compare/Mask Register.
* Not supported on P9 DD1.
*/
xsl_dsnctl |= ((u64)0x04 << (63-55));
xsl_dsnctl |= asnind;
}
*reg = xsl_dsnctl;
@ -463,7 +501,7 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,
if (rc)
return rc;
rc = cxl_get_xsl9_dsnctl(capp_unit_id, &xsl_dsnctl);
rc = cxl_get_xsl9_dsnctl(dev, capp_unit_id, &xsl_dsnctl);
if (rc)
return rc;