irqchip updates for 4.15, take #3
- New Socionext Synquacer EXIU driver - stm32 new platform support and fixes - One GICv4 bugfix - A couple of MIPS GIC cleanups -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAloEPrsVHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDZ+wP/Ryg9wZ87jUuWXE0iK9U//4GXk5p t5I8bv+ajzxVDZgmoruN8rxGOVIoB9vfPj2IKAbP/Je3fAVgmEnhn57T3/qxuoQj VsO2QyUeY5uqoZrvFkha/J3YFiZQ0gXXwFDCBKE9F/aXUx+z4YSE2SXMLI16p5LZ wD340BJ6RBgzcdu/iIpHP9mWbK+h4OCwOt8UG1m4aOQkCQxwO4onbzC7ck17vnyU /w+AKjQBjjMzVCqPgY/Thj+rP3bPpQ3H0YUN7yxMuwpJX2vPan++SLIJIXNsnXo2 E4goqDoCYN/jvA0SKF2b3+7ylLAI4+CI2IKADYiSk7CqjtXl7GeyR0dAj3E9/MGE ymNAo05dxDVfx+qNu8SqPRfqksXcK0eK1gR0069Y2+8THIArybyF7q+bPvCTHtQb 0vZkBHHyUq2turMueomqxHP5FyUVe+4eTpQvTpkgnO1nHcDjkranyK4lMIgFi0ST OQfm3ZftmPE290PQKm+BCyJpgVYeSXiVuZUpev3SLzpMTLKZRVn2KVjOz9w5Mrse COT7LYGUkiRAVocI2Z2Ch9NNSQnTjE+tKShQEUr24uALuqWAeUl5OPhh5iiZjRcj HwHFv5huXP+0vt4IGpF60P91hLBGVQGpAkRMPc2GNKTv6Aynf0HSgW9Ksi5NKnHz chIm8ZAYPuqfFBjm =Rym/ -----END PGP SIGNATURE----- Merge tag 'irqchip-4.15-3' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/core Pull irqchip updates for 4.15, take #3 from Marc Zyngier: - New Socionext Synquacer EXIU driver - stm32 new platform support and fixes - One GICv4 bugfix - A couple of MIPS GIC cleanups
This commit is contained in:
Thomas Gleixner
commit
9dc505d6df
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@ -0,0 +1,32 @@
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Socionext SynQuacer External Interrupt Unit (EXIU)
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The Socionext Synquacer SoC has an external interrupt unit (EXIU)
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that forwards a block of 32 configurable input lines to 32 adjacent
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level-high type GICv3 SPIs.
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Required properties:
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- compatible : Should be "socionext,synquacer-exiu".
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- reg : Specifies base physical address and size of the
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control registers.
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- interrupt-controller : Identifies the node as an interrupt controller.
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- #interrupt-cells : Specifies the number of cells needed to encode an
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interrupt source. The value must be 3.
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- interrupt-parent : phandle of the GIC these interrupts are routed to.
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- socionext,spi-base : The SPI number of the first SPI of the 32 adjacent
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ones the EXIU forwards its interrups to.
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Notes:
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- Only SPIs can use the EXIU as an interrupt parent.
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Example:
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exiu: interrupt-controller@510c0000 {
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compatible = "socionext,synquacer-exiu";
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reg = <0x0 0x510c0000 0x0 0x20>;
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interrupt-controller;
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interrupt-parent = <&gic>;
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#interrupt-cells = <3>;
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socionext,spi-base = <112>;
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};
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@ -2,7 +2,9 @@ STM32 External Interrupt Controller
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Required properties:
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- compatible: Should be "st,stm32-exti"
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- compatible: Should be:
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"st,stm32-exti"
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"st,stm32h7-exti"
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- reg: Specifies base physical address and size of the registers
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- interrupt-controller: Indentifies the node as an interrupt controller
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- #interrupt-cells: Specifies the number of cells to encode an interrupt
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@ -161,6 +161,9 @@ config ARCH_SEATTLE
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config ARCH_SHMOBILE
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bool
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config ARCH_SYNQUACER
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bool "Socionext SynQuacer SoC Family"
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config ARCH_RENESAS
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bool "Renesas SoC Platforms"
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select ARCH_SHMOBILE
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@ -306,6 +306,7 @@ config EZNPS_GIC
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config STM32_EXTI
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bool
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select IRQ_DOMAIN
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select GENERIC_IRQ_CHIP
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config QCOM_IRQ_COMBINER
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bool "QCOM IRQ combiner support"
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@ -79,4 +79,5 @@ obj-$(CONFIG_ARCH_ASPEED) += irq-aspeed-vic.o irq-aspeed-i2c-ic.o
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obj-$(CONFIG_STM32_EXTI) += irq-stm32-exti.o
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obj-$(CONFIG_QCOM_IRQ_COMBINER) += qcom-irq-combiner.o
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obj-$(CONFIG_IRQ_UNIPHIER_AIDET) += irq-uniphier-aidet.o
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obj-$(CONFIG_ARCH_SYNQUACER) += irq-sni-exiu.o
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obj-$(CONFIG_MESON_IRQ_GPIO) += irq-meson-gpio.o
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@ -2802,7 +2802,7 @@ static int its_vpe_irq_domain_activate(struct irq_domain *domain,
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/* If we use the list map, we issue VMAPP on demand... */
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if (its_list_map)
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return true;
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return 0;
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/* Map the VPE to the first possible CPU */
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vpe->col_idx = cpumask_first(cpu_online_mask);
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@ -6,6 +6,9 @@
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* Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
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*/
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#define pr_fmt(fmt) "irq-mips-gic: " fmt
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#include <linux/bitmap.h>
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#include <linux/clocksource.h>
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#include <linux/cpuhotplug.h>
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@ -685,7 +688,7 @@ static int __init gic_of_init(struct device_node *node,
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cpu_vec = find_first_zero_bit(&reserved, hweight_long(ST0_IM));
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if (cpu_vec == hweight_long(ST0_IM)) {
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pr_err("No CPU vectors available for GIC\n");
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pr_err("No CPU vectors available\n");
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return -ENODEV;
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}
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@ -698,8 +701,10 @@ static int __init gic_of_init(struct device_node *node,
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gic_base = read_gcr_gic_base() &
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~CM_GCR_GIC_BASE_GICEN;
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gic_len = 0x20000;
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pr_warn("Using inherited base address %pa\n",
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&gic_base);
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} else {
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pr_err("Failed to get GIC memory range\n");
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pr_err("Failed to get memory range\n");
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return -ENODEV;
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}
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} else {
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@ -757,7 +762,7 @@ static int __init gic_of_init(struct device_node *node,
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gic_shared_intrs, 0,
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&gic_irq_domain_ops, NULL);
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if (!gic_irq_domain) {
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pr_err("Failed to add GIC IRQ domain");
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pr_err("Failed to add IRQ domain");
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return -ENXIO;
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}
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@ -766,7 +771,7 @@ static int __init gic_of_init(struct device_node *node,
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GIC_NUM_LOCAL_INTRS + gic_shared_intrs,
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node, &gic_ipi_domain_ops, NULL);
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if (!gic_ipi_domain) {
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pr_err("Failed to add GIC IPI domain");
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pr_err("Failed to add IPI domain");
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return -ENXIO;
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}
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@ -0,0 +1,227 @@
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/*
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* Driver for Socionext External Interrupt Unit (EXIU)
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*
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* Copyright (c) 2017 Linaro, Ltd. <ard.biesheuvel@linaro.org>
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*
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* Based on irq-tegra.c:
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* Copyright (C) 2011 Google, Inc.
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* Copyright (C) 2010,2013, NVIDIA Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/irqdomain.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#define NUM_IRQS 32
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#define EIMASK 0x00
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#define EISRCSEL 0x04
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#define EIREQSTA 0x08
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#define EIRAWREQSTA 0x0C
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#define EIREQCLR 0x10
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#define EILVL 0x14
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#define EIEDG 0x18
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#define EISIR 0x1C
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struct exiu_irq_data {
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void __iomem *base;
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u32 spi_base;
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};
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static void exiu_irq_eoi(struct irq_data *d)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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writel(BIT(d->hwirq), data->base + EIREQCLR);
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irq_chip_eoi_parent(d);
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}
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static void exiu_irq_mask(struct irq_data *d)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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u32 val;
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val = readl_relaxed(data->base + EIMASK) | BIT(d->hwirq);
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writel_relaxed(val, data->base + EIMASK);
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irq_chip_mask_parent(d);
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}
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static void exiu_irq_unmask(struct irq_data *d)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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u32 val;
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val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
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writel_relaxed(val, data->base + EIMASK);
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irq_chip_unmask_parent(d);
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}
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static void exiu_irq_enable(struct irq_data *d)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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u32 val;
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/* clear interrupts that were latched while disabled */
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writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
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val = readl_relaxed(data->base + EIMASK) & ~BIT(d->hwirq);
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writel_relaxed(val, data->base + EIMASK);
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irq_chip_enable_parent(d);
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}
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static int exiu_irq_set_type(struct irq_data *d, unsigned int type)
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{
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struct exiu_irq_data *data = irq_data_get_irq_chip_data(d);
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u32 val;
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val = readl_relaxed(data->base + EILVL);
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if (type == IRQ_TYPE_EDGE_RISING || type == IRQ_TYPE_LEVEL_HIGH)
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val |= BIT(d->hwirq);
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else
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val &= ~BIT(d->hwirq);
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writel_relaxed(val, data->base + EILVL);
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val = readl_relaxed(data->base + EIEDG);
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if (type == IRQ_TYPE_LEVEL_LOW || type == IRQ_TYPE_LEVEL_HIGH)
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val &= ~BIT(d->hwirq);
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else
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val |= BIT(d->hwirq);
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writel_relaxed(val, data->base + EIEDG);
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writel_relaxed(BIT(d->hwirq), data->base + EIREQCLR);
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return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
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}
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static struct irq_chip exiu_irq_chip = {
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.name = "EXIU",
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.irq_eoi = exiu_irq_eoi,
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.irq_enable = exiu_irq_enable,
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.irq_mask = exiu_irq_mask,
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.irq_unmask = exiu_irq_unmask,
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.irq_set_type = exiu_irq_set_type,
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.irq_set_affinity = irq_chip_set_affinity_parent,
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.flags = IRQCHIP_SET_TYPE_MASKED |
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IRQCHIP_SKIP_SET_WAKE |
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IRQCHIP_EOI_THREADED |
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IRQCHIP_MASK_ON_SUSPEND,
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};
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static int exiu_domain_translate(struct irq_domain *domain,
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struct irq_fwspec *fwspec,
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unsigned long *hwirq,
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unsigned int *type)
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{
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struct exiu_irq_data *info = domain->host_data;
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if (is_of_node(fwspec->fwnode)) {
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if (fwspec->param_count != 3)
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return -EINVAL;
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if (fwspec->param[0] != GIC_SPI)
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return -EINVAL; /* No PPI should point to this domain */
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*hwirq = fwspec->param[1] - info->spi_base;
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*type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
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return 0;
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}
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return -EINVAL;
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}
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static int exiu_domain_alloc(struct irq_domain *dom, unsigned int virq,
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unsigned int nr_irqs, void *data)
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{
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struct irq_fwspec *fwspec = data;
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struct irq_fwspec parent_fwspec;
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struct exiu_irq_data *info = dom->host_data;
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irq_hw_number_t hwirq;
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if (fwspec->param_count != 3)
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return -EINVAL; /* Not GIC compliant */
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if (fwspec->param[0] != GIC_SPI)
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return -EINVAL; /* No PPI should point to this domain */
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WARN_ON(nr_irqs != 1);
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hwirq = fwspec->param[1] - info->spi_base;
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irq_domain_set_hwirq_and_chip(dom, virq, hwirq, &exiu_irq_chip, info);
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parent_fwspec = *fwspec;
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parent_fwspec.fwnode = dom->parent->fwnode;
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return irq_domain_alloc_irqs_parent(dom, virq, nr_irqs, &parent_fwspec);
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}
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static const struct irq_domain_ops exiu_domain_ops = {
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.translate = exiu_domain_translate,
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.alloc = exiu_domain_alloc,
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.free = irq_domain_free_irqs_common,
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};
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static int __init exiu_init(struct device_node *node,
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struct device_node *parent)
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{
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struct irq_domain *parent_domain, *domain;
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struct exiu_irq_data *data;
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int err;
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if (!parent) {
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pr_err("%pOF: no parent, giving up\n", node);
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return -ENODEV;
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}
|
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|
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parent_domain = irq_find_host(parent);
|
||||
if (!parent_domain) {
|
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pr_err("%pOF: unable to obtain parent domain\n", node);
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||||
return -ENXIO;
|
||||
}
|
||||
|
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data = kzalloc(sizeof(*data), GFP_KERNEL);
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if (!data)
|
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return -ENOMEM;
|
||||
|
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if (of_property_read_u32(node, "socionext,spi-base", &data->spi_base)) {
|
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pr_err("%pOF: failed to parse 'spi-base' property\n", node);
|
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err = -ENODEV;
|
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goto out_free;
|
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}
|
||||
|
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data->base = of_iomap(node, 0);
|
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if (IS_ERR(data->base)) {
|
||||
err = PTR_ERR(data->base);
|
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goto out_free;
|
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}
|
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|
||||
/* clear and mask all interrupts */
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writel_relaxed(0xFFFFFFFF, data->base + EIREQCLR);
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writel_relaxed(0xFFFFFFFF, data->base + EIMASK);
|
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|
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domain = irq_domain_add_hierarchy(parent_domain, 0, NUM_IRQS, node,
|
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&exiu_domain_ops, data);
|
||||
if (!domain) {
|
||||
pr_err("%pOF: failed to allocate domain\n", node);
|
||||
err = -ENOMEM;
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
pr_info("%pOF: %d interrupts forwarded to %pOF\n", node, NUM_IRQS,
|
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parent);
|
||||
|
||||
return 0;
|
||||
|
||||
out_unmap:
|
||||
iounmap(data->base);
|
||||
out_free:
|
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kfree(data);
|
||||
return err;
|
||||
}
|
||||
IRQCHIP_DECLARE(exiu, "socionext,synquacer-exiu", exiu_init);
|
||||
|
|
@ -14,27 +14,99 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
|
||||
#define EXTI_IMR 0x0
|
||||
#define EXTI_EMR 0x4
|
||||
#define EXTI_RTSR 0x8
|
||||
#define EXTI_FTSR 0xc
|
||||
#define EXTI_SWIER 0x10
|
||||
#define EXTI_PR 0x14
|
||||
#define IRQS_PER_BANK 32
|
||||
|
||||
struct stm32_exti_bank {
|
||||
u32 imr_ofst;
|
||||
u32 emr_ofst;
|
||||
u32 rtsr_ofst;
|
||||
u32 ftsr_ofst;
|
||||
u32 swier_ofst;
|
||||
u32 pr_ofst;
|
||||
};
|
||||
|
||||
static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
|
||||
.imr_ofst = 0x00,
|
||||
.emr_ofst = 0x04,
|
||||
.rtsr_ofst = 0x08,
|
||||
.ftsr_ofst = 0x0C,
|
||||
.swier_ofst = 0x10,
|
||||
.pr_ofst = 0x14,
|
||||
};
|
||||
|
||||
static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
|
||||
&stm32f4xx_exti_b1,
|
||||
};
|
||||
|
||||
static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
|
||||
.imr_ofst = 0x80,
|
||||
.emr_ofst = 0x84,
|
||||
.rtsr_ofst = 0x00,
|
||||
.ftsr_ofst = 0x04,
|
||||
.swier_ofst = 0x08,
|
||||
.pr_ofst = 0x88,
|
||||
};
|
||||
|
||||
static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
|
||||
.imr_ofst = 0x90,
|
||||
.emr_ofst = 0x94,
|
||||
.rtsr_ofst = 0x20,
|
||||
.ftsr_ofst = 0x24,
|
||||
.swier_ofst = 0x28,
|
||||
.pr_ofst = 0x98,
|
||||
};
|
||||
|
||||
static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
|
||||
.imr_ofst = 0xA0,
|
||||
.emr_ofst = 0xA4,
|
||||
.rtsr_ofst = 0x40,
|
||||
.ftsr_ofst = 0x44,
|
||||
.swier_ofst = 0x48,
|
||||
.pr_ofst = 0xA8,
|
||||
};
|
||||
|
||||
static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
|
||||
&stm32h7xx_exti_b1,
|
||||
&stm32h7xx_exti_b2,
|
||||
&stm32h7xx_exti_b3,
|
||||
};
|
||||
|
||||
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
|
||||
{
|
||||
const struct stm32_exti_bank *stm32_bank = gc->private;
|
||||
|
||||
return irq_reg_readl(gc, stm32_bank->pr_ofst);
|
||||
}
|
||||
|
||||
static void stm32_exti_irq_ack(struct irq_chip_generic *gc, u32 mask)
|
||||
{
|
||||
const struct stm32_exti_bank *stm32_bank = gc->private;
|
||||
|
||||
irq_reg_writel(gc, mask, stm32_bank->pr_ofst);
|
||||
}
|
||||
|
||||
static void stm32_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
struct irq_domain *domain = irq_desc_get_handler_data(desc);
|
||||
struct irq_chip_generic *gc = domain->gc->gc[0];
|
||||
struct irq_chip *chip = irq_desc_get_chip(desc);
|
||||
unsigned int virq, nbanks = domain->gc->num_chips;
|
||||
struct irq_chip_generic *gc;
|
||||
const struct stm32_exti_bank *stm32_bank;
|
||||
unsigned long pending;
|
||||
int n;
|
||||
int n, i, irq_base = 0;
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
while ((pending = irq_reg_readl(gc, EXTI_PR))) {
|
||||
for_each_set_bit(n, &pending, BITS_PER_LONG) {
|
||||
generic_handle_irq(irq_find_mapping(domain, n));
|
||||
irq_reg_writel(gc, BIT(n), EXTI_PR);
|
||||
for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
|
||||
gc = irq_get_domain_generic_chip(domain, irq_base);
|
||||
stm32_bank = gc->private;
|
||||
|
||||
while ((pending = stm32_exti_pending(gc))) {
|
||||
for_each_set_bit(n, &pending, IRQS_PER_BANK) {
|
||||
virq = irq_find_mapping(domain, irq_base + n);
|
||||
generic_handle_irq(virq);
|
||||
stm32_exti_irq_ack(gc, BIT(n));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -44,13 +116,14 @@ static void stm32_irq_handler(struct irq_desc *desc)
|
|||
static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
|
||||
int pin = data->hwirq;
|
||||
const struct stm32_exti_bank *stm32_bank = gc->private;
|
||||
int pin = data->hwirq % IRQS_PER_BANK;
|
||||
u32 rtsr, ftsr;
|
||||
|
||||
irq_gc_lock(gc);
|
||||
|
||||
rtsr = irq_reg_readl(gc, EXTI_RTSR);
|
||||
ftsr = irq_reg_readl(gc, EXTI_FTSR);
|
||||
rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
|
||||
ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
|
||||
|
||||
switch (type) {
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
|
|
@ -70,8 +143,8 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
irq_reg_writel(gc, rtsr, EXTI_RTSR);
|
||||
irq_reg_writel(gc, ftsr, EXTI_FTSR);
|
||||
irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
|
||||
irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
|
||||
|
||||
irq_gc_unlock(gc);
|
||||
|
||||
|
|
@ -81,17 +154,18 @@ static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
|
|||
static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
|
||||
{
|
||||
struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
|
||||
int pin = data->hwirq;
|
||||
u32 emr;
|
||||
const struct stm32_exti_bank *stm32_bank = gc->private;
|
||||
int pin = data->hwirq % IRQS_PER_BANK;
|
||||
u32 imr;
|
||||
|
||||
irq_gc_lock(gc);
|
||||
|
||||
emr = irq_reg_readl(gc, EXTI_EMR);
|
||||
imr = irq_reg_readl(gc, stm32_bank->imr_ofst);
|
||||
if (on)
|
||||
emr |= BIT(pin);
|
||||
imr |= BIT(pin);
|
||||
else
|
||||
emr &= ~BIT(pin);
|
||||
irq_reg_writel(gc, emr, EXTI_EMR);
|
||||
imr &= ~BIT(pin);
|
||||
irq_reg_writel(gc, imr, stm32_bank->imr_ofst);
|
||||
|
||||
irq_gc_unlock(gc);
|
||||
|
||||
|
|
@ -101,11 +175,12 @@ static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
|
|||
static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
|
||||
unsigned int nr_irqs, void *data)
|
||||
{
|
||||
struct irq_chip_generic *gc = d->gc->gc[0];
|
||||
struct irq_chip_generic *gc;
|
||||
struct irq_fwspec *fwspec = data;
|
||||
irq_hw_number_t hwirq;
|
||||
|
||||
hwirq = fwspec->param[0];
|
||||
gc = irq_get_domain_generic_chip(d, hwirq);
|
||||
|
||||
irq_map_generic_chip(d, virq, hwirq);
|
||||
irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
|
||||
|
|
@ -129,8 +204,9 @@ struct irq_domain_ops irq_exti_domain_ops = {
|
|||
.free = stm32_exti_free,
|
||||
};
|
||||
|
||||
static int __init stm32_exti_init(struct device_node *node,
|
||||
struct device_node *parent)
|
||||
static int
|
||||
__init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
|
||||
int bank_nr, struct device_node *node)
|
||||
{
|
||||
unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
|
||||
int nr_irqs, nr_exti, ret, i;
|
||||
|
|
@ -144,23 +220,16 @@ static int __init stm32_exti_init(struct device_node *node,
|
|||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Determine number of irqs supported */
|
||||
writel_relaxed(~0UL, base + EXTI_RTSR);
|
||||
nr_exti = fls(readl_relaxed(base + EXTI_RTSR));
|
||||
writel_relaxed(0, base + EXTI_RTSR);
|
||||
|
||||
pr_info("%pOF: %d External IRQs detected\n", node, nr_exti);
|
||||
|
||||
domain = irq_domain_add_linear(node, nr_exti,
|
||||
domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
|
||||
&irq_exti_domain_ops, NULL);
|
||||
if (!domain) {
|
||||
pr_err("%s: Could not register interrupt domain.\n",
|
||||
node->name);
|
||||
node->name);
|
||||
ret = -ENOMEM;
|
||||
goto out_unmap;
|
||||
}
|
||||
|
||||
ret = irq_alloc_domain_generic_chips(domain, nr_exti, 1, "exti",
|
||||
ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
|
||||
handle_edge_irq, clr, 0, 0);
|
||||
if (ret) {
|
||||
pr_err("%pOF: Could not allocate generic interrupt chip.\n",
|
||||
|
|
@ -168,18 +237,41 @@ static int __init stm32_exti_init(struct device_node *node,
|
|||
goto out_free_domain;
|
||||
}
|
||||
|
||||
gc = domain->gc->gc[0];
|
||||
gc->reg_base = base;
|
||||
gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
|
||||
gc->chip_types->chip.name = gc->chip_types[0].chip.name;
|
||||
gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
|
||||
gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
|
||||
gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
|
||||
gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
|
||||
gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
|
||||
gc->chip_types->regs.ack = EXTI_PR;
|
||||
gc->chip_types->regs.mask = EXTI_IMR;
|
||||
gc->chip_types->handler = handle_edge_irq;
|
||||
for (i = 0; i < bank_nr; i++) {
|
||||
const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
|
||||
u32 irqs_mask;
|
||||
|
||||
gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
|
||||
|
||||
gc->reg_base = base;
|
||||
gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
|
||||
gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
|
||||
gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
|
||||
gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
|
||||
gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
|
||||
gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
|
||||
gc->chip_types->regs.ack = stm32_bank->pr_ofst;
|
||||
gc->chip_types->regs.mask = stm32_bank->imr_ofst;
|
||||
gc->private = (void *)stm32_bank;
|
||||
|
||||
/* Determine number of irqs supported */
|
||||
writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
|
||||
irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
|
||||
nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
|
||||
|
||||
/*
|
||||
* This IP has no reset, so after hot reboot we should
|
||||
* clear registers to avoid residue
|
||||
*/
|
||||
writel_relaxed(0, base + stm32_bank->imr_ofst);
|
||||
writel_relaxed(0, base + stm32_bank->emr_ofst);
|
||||
writel_relaxed(0, base + stm32_bank->rtsr_ofst);
|
||||
writel_relaxed(0, base + stm32_bank->ftsr_ofst);
|
||||
writel_relaxed(~0UL, base + stm32_bank->pr_ofst);
|
||||
|
||||
pr_info("%s: bank%d, External IRQs available:%#x\n",
|
||||
node->full_name, i, irqs_mask);
|
||||
}
|
||||
|
||||
nr_irqs = of_irq_count(node);
|
||||
for (i = 0; i < nr_irqs; i++) {
|
||||
|
|
@ -198,4 +290,20 @@ out_unmap:
|
|||
return ret;
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(stm32_exti, "st,stm32-exti", stm32_exti_init);
|
||||
static int __init stm32f4_exti_of_init(struct device_node *np,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return stm32_exti_init(stm32f4xx_exti_banks,
|
||||
ARRAY_SIZE(stm32f4xx_exti_banks), np);
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
|
||||
|
||||
static int __init stm32h7_exti_of_init(struct device_node *np,
|
||||
struct device_node *parent)
|
||||
{
|
||||
return stm32_exti_init(stm32h7xx_exti_banks,
|
||||
ARRAY_SIZE(stm32h7xx_exti_banks), np);
|
||||
}
|
||||
|
||||
IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
|
||||
|
|
|
|||
Loading…
Reference in New Issue