iommu/vt-d: Move device_domain_info to header
This allows the per device iommu data and some helpers to be used in other files. Cc: Ashok Raj <ashok.raj@intel.com> Cc: Jacob Pan <jacob.jun.pan@linux.intel.com> Cc: Kevin Tian <kevin.tian@intel.com> Cc: Liu Yi L <yi.l.liu@intel.com> Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reviewed-by: Liu Yi L <yi.l.liu@intel.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Lu Baolu
Joerg Roedel
parent
af39507305
commit
9ddbfb4213
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@ -381,61 +381,6 @@ static int hw_pass_through = 1;
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for (idx = 0; idx < g_num_of_iommus; idx++) \
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if (domain->iommu_refcnt[idx])
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struct dmar_domain {
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int nid; /* node id */
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unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED];
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/* Refcount of devices per iommu */
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u16 iommu_did[DMAR_UNITS_SUPPORTED];
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/* Domain ids per IOMMU. Use u16 since
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* domain ids are 16 bit wide according
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* to VT-d spec, section 9.3 */
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bool has_iotlb_device;
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struct list_head devices; /* all devices' list */
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struct iova_domain iovad; /* iova's that belong to this domain */
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struct dma_pte *pgd; /* virtual address */
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int gaw; /* max guest address width */
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/* adjusted guest address width, 0 is level 2 30-bit */
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int agaw;
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int flags; /* flags to find out type of domain */
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int iommu_coherency;/* indicate coherency of iommu access */
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int iommu_snooping; /* indicate snooping control feature*/
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int iommu_count; /* reference count of iommu */
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int iommu_superpage;/* Level of superpages supported:
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0 == 4KiB (no superpages), 1 == 2MiB,
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2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
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u64 max_addr; /* maximum mapped address */
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struct iommu_domain domain; /* generic domain data structure for
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iommu core */
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};
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/* PCI domain-device relationship */
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struct device_domain_info {
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struct list_head link; /* link to domain siblings */
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struct list_head global; /* link to global list */
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u8 bus; /* PCI bus number */
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u8 devfn; /* PCI devfn number */
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u16 pfsid; /* SRIOV physical function source ID */
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u8 pasid_supported:3;
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u8 pasid_enabled:1;
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u8 pri_supported:1;
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u8 pri_enabled:1;
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u8 ats_supported:1;
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u8 ats_enabled:1;
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u8 ats_qdep;
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struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
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struct intel_iommu *iommu; /* IOMMU used by this device */
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struct dmar_domain *domain; /* pointer to domain */
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};
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struct dmar_rmrr_unit {
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struct list_head list; /* list of rmrr units */
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struct acpi_dmar_header *hdr; /* ACPI header */
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@ -604,7 +549,7 @@ static void set_iommu_domain(struct intel_iommu *iommu, u16 did,
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domains[did & 0xff] = domain;
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}
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static inline void *alloc_pgtable_page(int node)
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void *alloc_pgtable_page(int node)
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{
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struct page *page;
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void *vaddr = NULL;
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@ -615,7 +560,7 @@ static inline void *alloc_pgtable_page(int node)
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return vaddr;
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}
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static inline void free_pgtable_page(void *vaddr)
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void free_pgtable_page(void *vaddr)
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{
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free_page((unsigned long)vaddr);
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}
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@ -698,7 +643,7 @@ int iommu_calculate_agaw(struct intel_iommu *iommu)
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}
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/* This functionin only returns single iommu in a domain */
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static struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
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struct intel_iommu *domain_get_iommu(struct dmar_domain *domain)
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{
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int iommu_id;
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@ -3528,7 +3473,7 @@ static unsigned long intel_alloc_iova(struct device *dev,
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return iova_pfn;
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}
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static struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
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struct dmar_domain *get_valid_domain_for_dev(struct device *dev)
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{
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struct dmar_domain *domain, *tmp;
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struct dmar_rmrr_unit *rmrr;
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@ -31,6 +31,7 @@
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#include <linux/list.h>
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#include <linux/iommu.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/dmar.h>
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#include <asm/cacheflush.h>
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#include <asm/iommu.h>
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@ -387,6 +388,42 @@ struct pasid_entry;
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struct pasid_state_entry;
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struct page_req_dsc;
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struct dmar_domain {
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int nid; /* node id */
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unsigned iommu_refcnt[DMAR_UNITS_SUPPORTED];
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/* Refcount of devices per iommu */
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u16 iommu_did[DMAR_UNITS_SUPPORTED];
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/* Domain ids per IOMMU. Use u16 since
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* domain ids are 16 bit wide according
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* to VT-d spec, section 9.3 */
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bool has_iotlb_device;
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struct list_head devices; /* all devices' list */
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struct iova_domain iovad; /* iova's that belong to this domain */
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struct dma_pte *pgd; /* virtual address */
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int gaw; /* max guest address width */
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/* adjusted guest address width, 0 is level 2 30-bit */
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int agaw;
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int flags; /* flags to find out type of domain */
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int iommu_coherency;/* indicate coherency of iommu access */
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int iommu_snooping; /* indicate snooping control feature*/
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int iommu_count; /* reference count of iommu */
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int iommu_superpage;/* Level of superpages supported:
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0 == 4KiB (no superpages), 1 == 2MiB,
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2 == 1GiB, 3 == 512GiB, 4 == 1TiB */
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u64 max_addr; /* maximum mapped address */
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struct iommu_domain domain; /* generic domain data structure for
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iommu core */
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};
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struct intel_iommu {
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void __iomem *reg; /* Pointer to hardware regs, virtual addr */
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u64 reg_phys; /* physical address of hw register set */
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@ -435,6 +472,25 @@ struct intel_iommu {
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u32 flags; /* Software defined flags */
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};
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/* PCI domain-device relationship */
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struct device_domain_info {
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struct list_head link; /* link to domain siblings */
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struct list_head global; /* link to global list */
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u8 bus; /* PCI bus number */
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u8 devfn; /* PCI devfn number */
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u16 pfsid; /* SRIOV physical function source ID */
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u8 pasid_supported:3;
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u8 pasid_enabled:1;
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u8 pri_supported:1;
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u8 pri_enabled:1;
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u8 ats_supported:1;
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u8 ats_enabled:1;
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u8 ats_qdep;
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struct device *dev; /* it's NULL for PCIe-to-PCI bridge */
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struct intel_iommu *iommu; /* IOMMU used by this device */
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struct dmar_domain *domain; /* pointer to domain */
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};
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static inline void __iommu_flush_cache(
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struct intel_iommu *iommu, void *addr, int size)
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{
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@ -460,6 +516,11 @@ extern int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
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extern int dmar_ir_support(void);
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struct dmar_domain *get_valid_domain_for_dev(struct device *dev);
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void *alloc_pgtable_page(int node);
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void free_pgtable_page(void *vaddr);
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struct intel_iommu *domain_get_iommu(struct dmar_domain *domain);
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#ifdef CONFIG_INTEL_IOMMU_SVM
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extern int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu);
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extern int intel_svm_free_pasid_tables(struct intel_iommu *iommu);
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