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arm64: dts: imx8: add conn lpcg clocks
Add conn lpcg clocks Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Fabio Estevam <fabio.estevam@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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438ae46b8e
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9de8a22675
1 changed files with 101 additions and 3 deletions
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@ -4,15 +4,34 @@
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* Dong Aisheng <aisheng.dong@nxp.com>
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*/
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#include <dt-bindings/clock/imx8-lpcg.h>
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#include <dt-bindings/firmware/imx/rsrc.h>
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conn_subsys: bus@5b000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x5b000000 0x0 0x5b000000 0x1000000>;
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conn_lpcg: clock-controller@5b200000 {
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reg = <0x5b200000 0xb0000>;
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#clock-cells = <1>;
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conn_axi_clk: clock-conn-axi {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <333333333>;
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clock-output-names = "conn_axi_clk";
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};
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conn_ahb_clk: clock-conn-ahb {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <166666666>;
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clock-output-names = "conn_ahb_clk";
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};
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conn_ipg_clk: clock-conn-ipg {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <83333333>;
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clock-output-names = "conn_ipg_clk";
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};
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usdhc1: mmc@5b010000 {
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@ -83,4 +102,83 @@ fec2: ethernet@5b050000 {
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power-domains = <&pd IMX_SC_R_ENET_1>;
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status = "disabled";
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};
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/* LPCG clocks */
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conn_lpcg: clock-controller-legacy@5b200000 {
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reg = <0x5b200000 0xb0000>;
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#clock-cells = <1>;
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};
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sdhc0_lpcg: clock-controller@5b200000 {
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reg = <0x5b200000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_CONN_SDHC0_CLK>,
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<&conn_ipg_clk>, <&conn_axi_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "sdhc0_lpcg_per_clk",
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"sdhc0_lpcg_ipg_clk",
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"sdhc0_lpcg_ahb_clk";
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power-domains = <&pd IMX_SC_R_SDHC_0>;
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};
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sdhc1_lpcg: clock-controller@5b210000 {
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reg = <0x5b210000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_CONN_SDHC1_CLK>,
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<&conn_ipg_clk>, <&conn_axi_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "sdhc1_lpcg_per_clk",
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"sdhc1_lpcg_ipg_clk",
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"sdhc1_lpcg_ahb_clk";
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power-domains = <&pd IMX_SC_R_SDHC_1>;
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};
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sdhc2_lpcg: clock-controller@5b220000 {
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reg = <0x5b220000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_CONN_SDHC2_CLK>,
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<&conn_ipg_clk>, <&conn_axi_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "sdhc2_lpcg_per_clk",
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"sdhc2_lpcg_ipg_clk",
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"sdhc2_lpcg_ahb_clk";
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power-domains = <&pd IMX_SC_R_SDHC_2>;
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};
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enet0_lpcg: clock-controller@5b230000 {
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reg = <0x5b230000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
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<&clk IMX_CONN_ENET0_ROOT_CLK>,
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<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "enet0_ipg_root_clk",
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"enet0_tx_clk",
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"enet0_ahb_clk",
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"enet0_ipg_clk",
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"enet0_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_ENET_0>;
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};
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enet1_lpcg: clock-controller@5b240000 {
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reg = <0x5b240000 0x10000>;
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#clock-cells = <1>;
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clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
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<&clk IMX_CONN_ENET1_ROOT_CLK>,
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<&conn_axi_clk>, <&conn_ipg_clk>, <&conn_ipg_clk>;
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clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
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<IMX_LPCG_CLK_2>, <IMX_LPCG_CLK_4>,
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<IMX_LPCG_CLK_5>;
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clock-output-names = "enet1_ipg_root_clk",
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"enet1_tx_clk",
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"enet1_ahb_clk",
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"enet1_ipg_clk",
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"enet1_ipg_s_clk";
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power-domains = <&pd IMX_SC_R_ENET_1>;
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};
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};
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