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selftests: bpf: move sub-register zero extension checks into subreg.c

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It is better to centralize all sub-register zero extension checks into an
independent file.

This patch takes the first step to move existing sub-register zero
extension checks into subreg.c.

Acked-by: Jakub Kicinski <jakub.kicinski@netronome.com>
Reviewed-by: Quentin Monnet <quentin.monnet@netronome.com>
Signed-off-by: Jiong Wang <jiong.wang@netronome.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
This commit is contained in:
Jiong Wang 2019-05-29 10:57:08 +01:00 committed by Daniel Borkmann
parent bd95e678e0
commit 9e084bb980
2 changed files with 39 additions and 39 deletions
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39
tools/testing/selftests/bpf/verifier/basic_instr.c
View file

@ -132,42 +132,3 @@
.prog_type = BPF_PROG_TYPE_SCHED_CLS,
.result = ACCEPT,
},
{
"and32 reg zero extend check",
.insns = {
BPF_MOV64_IMM(BPF_REG_0, -1),
BPF_MOV64_IMM(BPF_REG_2, -2),
BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2),
BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
BPF_EXIT_INSN(),
},
.prog_type = BPF_PROG_TYPE_SCHED_CLS,
.result = ACCEPT,
.retval = 0,
},
{
"or32 reg zero extend check",
.insns = {
BPF_MOV64_IMM(BPF_REG_0, -1),
BPF_MOV64_IMM(BPF_REG_2, -2),
BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2),
BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
BPF_EXIT_INSN(),
},
.prog_type = BPF_PROG_TYPE_SCHED_CLS,
.result = ACCEPT,
.retval = 0,
},
{
"xor32 reg zero extend check",
.insns = {
BPF_MOV64_IMM(BPF_REG_0, -1),
BPF_MOV64_IMM(BPF_REG_2, 0),
BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2),
BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
BPF_EXIT_INSN(),
},
.prog_type = BPF_PROG_TYPE_SCHED_CLS,
.result = ACCEPT,
.retval = 0,
},

39
tools/testing/selftests/bpf/verifier/subreg.c Normal file
View file

@ -0,0 +1,39 @@
{
"or32 reg zero extend check",
.insns = {
BPF_MOV64_IMM(BPF_REG_0, -1),
BPF_MOV64_IMM(BPF_REG_2, -2),
BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2),
BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
BPF_EXIT_INSN(),
},
.prog_type = BPF_PROG_TYPE_SCHED_CLS,
.result = ACCEPT,
.retval = 0,
},
{
"and32 reg zero extend check",
.insns = {
BPF_MOV64_IMM(BPF_REG_0, -1),
BPF_MOV64_IMM(BPF_REG_2, -2),
BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2),
BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
BPF_EXIT_INSN(),
},
.prog_type = BPF_PROG_TYPE_SCHED_CLS,
.result = ACCEPT,
.retval = 0,
},
{
"xor32 reg zero extend check",
.insns = {
BPF_MOV64_IMM(BPF_REG_0, -1),
BPF_MOV64_IMM(BPF_REG_2, 0),
BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2),
BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32),
BPF_EXIT_INSN(),
},
.prog_type = BPF_PROG_TYPE_SCHED_CLS,
.result = ACCEPT,
.retval = 0,
},