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drm/i915/dg2: add DG2 platform info
DG2 has Xe_LPD display (version 13) and Xe_HPG (version 12.55) graphics. There are two variants (treated as subplatforms in the code): DG2-G10 and DG2-G11 that require independent programming in some areas (e.g., workarounds). Bspec: 44472, 44474, 46197, 48028, 48077 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20210721223043.834562-4-matthew.d.roper@intel.com
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086df54e20
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5 changed files with 68 additions and 1 deletions
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@ -1392,6 +1392,11 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_ALDERLAKE_S(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_S)
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#define IS_ALDERLAKE_P(dev_priv) IS_PLATFORM(dev_priv, INTEL_ALDERLAKE_P)
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#define IS_XEHPSDV(dev_priv) IS_PLATFORM(dev_priv, INTEL_XEHPSDV)
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#define IS_DG2(dev_priv) IS_PLATFORM(dev_priv, INTEL_DG2)
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#define IS_DG2_G10(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G10)
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#define IS_DG2_G11(dev_priv) \
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IS_SUBPLATFORM(dev_priv, INTEL_DG2, INTEL_SUBPLATFORM_G11)
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#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
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#define IS_BDW_ULT(dev_priv) \
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@ -1505,6 +1510,28 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
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#define IS_XEHPSDV_GT_STEP(p, since, until) \
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(IS_XEHPSDV(p) && IS_GT_STEP(__i915, since, until))
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/*
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* DG2 hardware steppings are a bit unusual. The hardware design was forked
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* to create two variants (G10 and G11) which have distinct workaround sets.
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* The G11 fork of the DG2 design resets the GT stepping back to "A0" for its
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* first iteration, even though it's more similar to a G10 B0 stepping in terms
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* of functionality and workarounds. However the display stepping does not
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* reset in the same manner --- a specific stepping like "B0" has a consistent
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* meaning regardless of whether it belongs to a G10 or G11 DG2.
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*
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* TLDR: All GT workarounds and stepping-specific logic must be applied in
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* relation to a specific subplatform (G10 or G11), whereas display workarounds
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* and stepping-specific logic will be applied with a general DG2-wide stepping
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* number.
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*/
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#define IS_DG2_GT_STEP(__i915, variant, since, until) \
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(IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
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IS_GT_STEP(__i915, since, until))
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#define IS_DG2_DISP_STEP(__i915, since, until) \
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(IS_DG2(__i915) && \
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IS_DISPLAY_STEP(__i915, since, until))
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#define IS_LP(dev_priv) (INTEL_INFO(dev_priv)->is_lp)
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#define IS_GEN9_LP(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && IS_LP(dev_priv))
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#define IS_GEN9_BC(dev_priv) (GRAPHICS_VER(dev_priv) == 9 && !IS_LP(dev_priv))
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@ -1006,6 +1006,22 @@ static const struct intel_device_info xehpsdv_info = {
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.require_force_probe = 1,
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};
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__maybe_unused
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static const struct intel_device_info dg2_info = {
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XE_HP_FEATURES,
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XE_HPM_FEATURES,
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XE_LPD_FEATURES,
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DGFX_FEATURES,
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.graphics_rel = 55,
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.media_rel = 55,
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PLATFORM(INTEL_DG2),
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.platform_engine_mask =
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BIT(RCS0) | BIT(BCS0) |
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BIT(VECS0) | BIT(VECS1) |
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BIT(VCS0) | BIT(VCS2),
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.require_force_probe = 1,
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};
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#undef PLATFORM
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/*
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@ -69,6 +69,7 @@ static const char * const platform_names[] = {
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PLATFORM_NAME(ALDERLAKE_S),
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PLATFORM_NAME(ALDERLAKE_P),
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PLATFORM_NAME(XEHPSDV),
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PLATFORM_NAME(DG2),
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};
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#undef PLATFORM_NAME
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@ -89,6 +89,7 @@ enum intel_platform {
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INTEL_ALDERLAKE_S,
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INTEL_ALDERLAKE_P,
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INTEL_XEHPSDV,
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INTEL_DG2,
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INTEL_MAX_PLATFORMS
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};
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@ -107,6 +108,10 @@ enum intel_platform {
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/* CNL/ICL */
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#define INTEL_SUBPLATFORM_PORTF (0)
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/* DG2 */
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#define INTEL_SUBPLATFORM_G10 0
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#define INTEL_SUBPLATFORM_G11 1
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enum intel_ppgtt_type {
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INTEL_PPGTT_NONE = I915_GEM_PPGTT_NONE,
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INTEL_PPGTT_ALIASING = I915_GEM_PPGTT_ALIASING,
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@ -108,6 +108,18 @@ static const struct intel_step_info xehpsdv_revids[] = {
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[0x8] = { .gt_step = STEP_C0 },
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};
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static const struct intel_step_info dg2_g10_revid_step_tbl[] = {
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[0x0] = { .gt_step = STEP_A0, .display_step = STEP_A0 },
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[0x1] = { .gt_step = STEP_A1, .display_step = STEP_A0 },
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[0x4] = { .gt_step = STEP_B0, .display_step = STEP_B0 },
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[0x8] = { .gt_step = STEP_C0, .display_step = STEP_C0 },
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};
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static const struct intel_step_info dg2_g11_revid_step_tbl[] = {
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[0x0] = { .gt_step = STEP_A0, .display_step = STEP_B0 },
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[0x4] = { .gt_step = STEP_B0, .display_step = STEP_C0 },
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};
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void intel_step_init(struct drm_i915_private *i915)
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{
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const struct intel_step_info *revids = NULL;
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@ -115,7 +127,13 @@ void intel_step_init(struct drm_i915_private *i915)
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int revid = INTEL_REVID(i915);
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struct intel_step_info step = {};
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if (IS_XEHPSDV(i915)) {
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if (IS_DG2_G10(i915)) {
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revids = dg2_g10_revid_step_tbl;
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size = ARRAY_SIZE(dg2_g10_revid_step_tbl);
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} else if (IS_DG2_G11(i915)) {
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revids = dg2_g11_revid_step_tbl;
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size = ARRAY_SIZE(dg2_g11_revid_step_tbl);
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} else if (IS_XEHPSDV(i915)) {
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revids = xehpsdv_revids;
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size = ARRAY_SIZE(xehpsdv_revids);
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} else if (IS_ALDERLAKE_P(i915)) {
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