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MIPS: Remove execution hazard barriers for Octeon.
The Octeon has no execution hazards, so we can remove them and save an instruction per TLB handler invocation. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Reviewed by: David VomLehn <dvomlehn@cisco.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -47,6 +47,7 @@
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#define cpu_has_mips32r2 0
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#define cpu_has_mips64r1 0
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#define cpu_has_mips64r2 1
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#define cpu_has_mips_r2_exec_hazard 0
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#define cpu_has_dsp 0
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#define cpu_has_mipsmt 0
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#define cpu_has_userlocal 0
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