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perf intel-pt: Add gp registers to synthesized PEBS sample
Add general purpose register information from PEBS data in the Intel PT trace to the synthesized PEBS sample. Signed-off-by: Adrian Hunter <adrian.hunter@intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Link: http://lkml.kernel.org/r/20190610072803.10456-8-adrian.hunter@intel.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -35,6 +35,8 @@
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#include "config.h"
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#include "config.h"
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#include "time-utils.h"
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#include "time-utils.h"
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#include "../arch/x86/include/uapi/asm/perf_regs.h"
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#include "intel-pt-decoder/intel-pt-log.h"
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#include "intel-pt-decoder/intel-pt-log.h"
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#include "intel-pt-decoder/intel-pt-decoder.h"
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#include "intel-pt-decoder/intel-pt-decoder.h"
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#include "intel-pt-decoder/intel-pt-insn-decoder.h"
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#include "intel-pt-decoder/intel-pt-insn-decoder.h"
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@ -1547,6 +1549,60 @@ static int intel_pt_synth_pwrx_sample(struct intel_pt_queue *ptq)
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pt->pwr_events_sample_type);
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pt->pwr_events_sample_type);
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}
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}
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/*
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* PEBS gp_regs array indexes plus 1 so that 0 means not present. Refer
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* intel_pt_add_gp_regs().
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*/
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static const int pebs_gp_regs[] = {
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[PERF_REG_X86_FLAGS] = 1,
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[PERF_REG_X86_IP] = 2,
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[PERF_REG_X86_AX] = 3,
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[PERF_REG_X86_CX] = 4,
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[PERF_REG_X86_DX] = 5,
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[PERF_REG_X86_BX] = 6,
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[PERF_REG_X86_SP] = 7,
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[PERF_REG_X86_BP] = 8,
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[PERF_REG_X86_SI] = 9,
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[PERF_REG_X86_DI] = 10,
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[PERF_REG_X86_R8] = 11,
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[PERF_REG_X86_R9] = 12,
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[PERF_REG_X86_R10] = 13,
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[PERF_REG_X86_R11] = 14,
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[PERF_REG_X86_R12] = 15,
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[PERF_REG_X86_R13] = 16,
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[PERF_REG_X86_R14] = 17,
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[PERF_REG_X86_R15] = 18,
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};
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static u64 *intel_pt_add_gp_regs(struct regs_dump *intr_regs, u64 *pos,
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const struct intel_pt_blk_items *items,
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u64 regs_mask)
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{
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const u64 *gp_regs = items->val[INTEL_PT_GP_REGS_POS];
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u32 mask = items->mask[INTEL_PT_GP_REGS_POS];
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u32 bit;
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int i;
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for (i = 0, bit = 1; i < PERF_REG_X86_64_MAX; i++, bit <<= 1) {
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/* Get the PEBS gp_regs array index */
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int n = pebs_gp_regs[i] - 1;
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if (n < 0)
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continue;
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/*
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* Add only registers that were requested (i.e. 'regs_mask') and
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* that were provided (i.e. 'mask'), and update the resulting
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* mask (i.e. 'intr_regs->mask') accordingly.
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*/
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if (mask & 1 << n && regs_mask & bit) {
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intr_regs->mask |= bit;
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*pos++ = gp_regs[n];
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}
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}
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return pos;
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}
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static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq)
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static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq)
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{
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{
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const struct intel_pt_blk_items *items = &ptq->state->items;
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const struct intel_pt_blk_items *items = &ptq->state->items;
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@ -1597,6 +1653,19 @@ static int intel_pt_synth_pebs_sample(struct intel_pt_queue *ptq)
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sample.time = tsc_to_perf_time(timestamp, &pt->tc);
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sample.time = tsc_to_perf_time(timestamp, &pt->tc);
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}
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}
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if (sample_type & PERF_SAMPLE_REGS_INTR &&
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items->mask[INTEL_PT_GP_REGS_POS]) {
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u64 regs[sizeof(sample.intr_regs.mask)];
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u64 regs_mask = evsel->attr.sample_regs_intr;
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sample.intr_regs.abi = items->is_32_bit ?
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PERF_SAMPLE_REGS_ABI_32 :
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PERF_SAMPLE_REGS_ABI_64;
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sample.intr_regs.regs = regs;
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intel_pt_add_gp_regs(&sample.intr_regs, regs, items, regs_mask);
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}
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return intel_pt_deliver_synth_event(pt, ptq, event, &sample, sample_type);
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return intel_pt_deliver_synth_event(pt, ptq, event, &sample, sample_type);
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}
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}
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