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ARM: orion: Fix for certain sequence of request_irq can cause irq storm
The problem is that hardware handled by arm/plat-orion/gpio.c, require ack for edge irq, and no ack for level irq. The code handle this issue, by two "struct irq_chip_type" per one "struct irq_chip_generic". For one "struct irq_chip_generic" irq_ack pointer is setted, for another it is NULL. But we have only one mask_cache per two "struct irq_chip_type". So if we 1)unmask interrupt A for "edge type" trigger, 2)unmask interrupt B for "level type" trigger, 3)unmask interrupt C for "edge type", we, because of usage of generic irq_gc_mask_clr_bit/irq_gc_mask_set_bit, have hardware configured to trigger interrupt B on "edge type", because of shared mask_cache. But kernel think that B is "level type", so when interrupt B occur via "edge" reason, we don't ack it, and B triggered again and again. Signed-off-by: Evgeniy A. Dushistov <dushistov@mail.ru> Link: https://lkml.kernel.org/r/20140726155659.GA22977@fifteen Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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5129ee22ce
commit
9ece8839b1
1 changed files with 32 additions and 4 deletions
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@ -497,6 +497,34 @@ static void orion_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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#define orion_gpio_dbg_show NULL
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#endif
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static void orion_gpio_unmask_irq(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 reg_val;
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u32 mask = d->mask;
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irq_gc_lock(gc);
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reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
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reg_val |= mask;
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irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
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irq_gc_unlock(gc);
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}
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static void orion_gpio_mask_irq(struct irq_data *d)
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{
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struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
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struct irq_chip_type *ct = irq_data_get_chip_type(d);
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u32 mask = d->mask;
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u32 reg_val;
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irq_gc_lock(gc);
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reg_val = irq_reg_readl(gc->reg_base + ct->regs.mask);
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reg_val &= ~mask;
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irq_reg_writel(reg_val, gc->reg_base + ct->regs.mask);
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irq_gc_unlock(gc);
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}
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void __init orion_gpio_init(struct device_node *np,
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int gpio_base, int ngpio,
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void __iomem *base, int mask_offset,
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@ -565,8 +593,8 @@ void __init orion_gpio_init(struct device_node *np,
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ct = gc->chip_types;
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ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
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ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_mask = orion_gpio_mask_irq;
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ct->chip.irq_unmask = orion_gpio_unmask_irq;
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ct->chip.irq_set_type = gpio_irq_set_type;
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ct->chip.name = ochip->chip.label;
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@ -575,8 +603,8 @@ void __init orion_gpio_init(struct device_node *np,
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ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
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ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
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ct->chip.irq_ack = irq_gc_ack_clr_bit;
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ct->chip.irq_mask = irq_gc_mask_clr_bit;
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ct->chip.irq_unmask = irq_gc_mask_set_bit;
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ct->chip.irq_mask = orion_gpio_mask_irq;
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ct->chip.irq_unmask = orion_gpio_unmask_irq;
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ct->chip.irq_set_type = gpio_irq_set_type;
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ct->handler = handle_edge_irq;
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ct->chip.name = ochip->chip.label;
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