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media: rc: meson-ir: rename Meson IR Controller register macros
There are more registers to come in the next Meson IR Controller. For defining clearly, rename register macros. Signed-off-by: Zelong Dong <zelong.dong@amlogic.com> Signed-off-by: Sean Young <sean@mess.org> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
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8091020c78
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9ed61d1fd6
1 changed files with 40 additions and 37 deletions
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@ -24,31 +24,30 @@
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#define IR_DEC_LDR_REPEAT 0x08
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#define IR_DEC_BIT_0 0x0c
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#define IR_DEC_REG0 0x10
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#define REG0_RATE_MASK GENMASK(11, 0)
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#define IR_DEC_REG0_BASE_TIME GENMASK(11, 0)
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#define IR_DEC_FRAME 0x14
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#define IR_DEC_STATUS 0x18
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#define STATUS_IR_DEC_IN BIT(8)
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#define IR_DEC_STATUS_PULSE BIT(8)
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#define IR_DEC_REG1 0x1c
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#define REG1_TIME_IV_MASK GENMASK(28, 16)
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#define REG1_ENABLE BIT(15)
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#define REG1_MODE_MASK GENMASK(8, 7)
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#define REG1_MODE_SHIFT 7
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#define REG1_IRQSEL_MASK GENMASK(3, 2)
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#define REG1_RESET BIT(0)
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#define IR_DEC_REG1_TIME_IV GENMASK(28, 16)
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#define IR_DEC_REG1_ENABLE BIT(15)
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#define IR_DEC_REG1_MODE GENMASK(8, 7)
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#define IR_DEC_REG1_IRQSEL GENMASK(3, 2)
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#define IR_DEC_REG1_RESET BIT(0)
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/* The following regs are only available on Meson 8b and newer */
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#define IR_DEC_REG2 0x20
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#define REG2_MODE_MASK GENMASK(3, 0)
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#define REG2_MODE_SHIFT 0
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#define IR_DEC_REG2_MODE GENMASK(3, 0)
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#define DECODE_MODE_NEC 0x0
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#define DECODE_MODE_RAW 0x2
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#define DEC_MODE_NEC 0x0
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#define DEC_MODE_RAW 0x2
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#define REG1_IRQSEL_NEC_MODE 0
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#define REG1_IRQSEL_RISE_FALL 1
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#define REG1_IRQSEL_FALL 2
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#define REG1_IRQSEL_RISE 3
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#define IRQSEL_NEC_MODE 0
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#define IRQSEL_RISE_FALL 1
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#define IRQSEL_FALL 2
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#define IRQSEL_RISE 3
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#define MESON_TRATE 10 /* us */
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#define MESON_RAW_TRATE 10 /* us */
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#define MESON_HW_TRATE 20 /* us */
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struct meson_ir {
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void __iomem *reg;
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@ -76,11 +75,11 @@ static irqreturn_t meson_ir_irq(int irqno, void *dev_id)
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spin_lock(&ir->lock);
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duration = readl_relaxed(ir->reg + IR_DEC_REG1);
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duration = FIELD_GET(REG1_TIME_IV_MASK, duration);
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rawir.duration = duration * MESON_TRATE;
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duration = FIELD_GET(IR_DEC_REG1_TIME_IV, duration);
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rawir.duration = duration * MESON_RAW_TRATE;
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status = readl_relaxed(ir->reg + IR_DEC_STATUS);
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rawir.pulse = !!(status & STATUS_IR_DEC_IN);
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rawir.pulse = !!(status & IR_DEC_STATUS_PULSE);
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ir_raw_event_store_with_timeout(ir->rc, &rawir);
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@ -122,7 +121,7 @@ static int meson_ir_probe(struct platform_device *pdev)
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map_name = of_get_property(node, "linux,rc-map-name", NULL);
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ir->rc->map_name = map_name ? map_name : RC_MAP_EMPTY;
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ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
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ir->rc->rx_resolution = MESON_TRATE;
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ir->rc->rx_resolution = MESON_RAW_TRATE;
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ir->rc->min_timeout = 1;
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ir->rc->timeout = IR_DEFAULT_TIMEOUT;
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ir->rc->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
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@ -144,24 +143,27 @@ static int meson_ir_probe(struct platform_device *pdev)
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}
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/* Reset the decoder */
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meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, REG1_RESET);
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meson_ir_set_mask(ir, IR_DEC_REG1, REG1_RESET, 0);
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meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET,
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IR_DEC_REG1_RESET);
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meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_RESET, 0);
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/* Set general operation mode (= raw/software decoding) */
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if (of_device_is_compatible(node, "amlogic,meson6-ir"))
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meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
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FIELD_PREP(REG1_MODE_MASK, DECODE_MODE_RAW));
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meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE,
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FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_RAW));
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else
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meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
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FIELD_PREP(REG2_MODE_MASK, DECODE_MODE_RAW));
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meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE,
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FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_RAW));
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/* Set rate */
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meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, MESON_TRATE - 1);
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meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
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MESON_RAW_TRATE - 1);
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/* IRQ on rising and falling edges */
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meson_ir_set_mask(ir, IR_DEC_REG1, REG1_IRQSEL_MASK,
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FIELD_PREP(REG1_IRQSEL_MASK, REG1_IRQSEL_RISE_FALL));
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meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_IRQSEL,
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FIELD_PREP(IR_DEC_REG1_IRQSEL, IRQSEL_RISE_FALL));
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/* Enable the decoder */
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meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, REG1_ENABLE);
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meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE,
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IR_DEC_REG1_ENABLE);
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dev_info(dev, "receiver initialized\n");
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@ -175,7 +177,7 @@ static void meson_ir_remove(struct platform_device *pdev)
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/* Disable the decoder */
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spin_lock_irqsave(&ir->lock, flags);
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meson_ir_set_mask(ir, IR_DEC_REG1, REG1_ENABLE, 0);
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meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_ENABLE, 0);
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spin_unlock_irqrestore(&ir->lock, flags);
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}
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@ -193,14 +195,15 @@ static void meson_ir_shutdown(struct platform_device *pdev)
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* bootloader a chance to power the system back on
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*/
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if (of_device_is_compatible(node, "amlogic,meson6-ir"))
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meson_ir_set_mask(ir, IR_DEC_REG1, REG1_MODE_MASK,
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DECODE_MODE_NEC << REG1_MODE_SHIFT);
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meson_ir_set_mask(ir, IR_DEC_REG1, IR_DEC_REG1_MODE,
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FIELD_PREP(IR_DEC_REG1_MODE, DEC_MODE_NEC));
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else
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meson_ir_set_mask(ir, IR_DEC_REG2, REG2_MODE_MASK,
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DECODE_MODE_NEC << REG2_MODE_SHIFT);
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meson_ir_set_mask(ir, IR_DEC_REG2, IR_DEC_REG2_MODE,
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FIELD_PREP(IR_DEC_REG2_MODE, DEC_MODE_NEC));
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/* Set rate to default value */
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meson_ir_set_mask(ir, IR_DEC_REG0, REG0_RATE_MASK, 0x13);
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meson_ir_set_mask(ir, IR_DEC_REG0, IR_DEC_REG0_BASE_TIME,
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MESON_HW_TRATE - 1);
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spin_unlock_irqrestore(&ir->lock, flags);
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}
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