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drm/amd/powerplay: rv dal-pplib interface refactor powerplay part
[WHY] clarify dal input parameters to pplib interface, remove un-used parameters. dal knows exactly which parameters needed and their effects at pplib and smu sides. current dal sequence for dcn1_update_clock to pplib: 1.smu10_display_clock_voltage_request for dcefclk 2.smu10_display_clock_voltage_request for fclk 3.phm_store_dal_configuration_data { set_min_deep_sleep_dcfclk set_active_display_count store_cc6_data --- this data never be referenced new sequence will be: 1. set_display_count --- need add new pplib interface 2. set_min_deep_sleep_dcfclk -- new pplib interface 3. set_hard_min_dcfclk_by_freq 4. set_hard_min_fclk_by_freq after this code refactor, smu10_display_clock_voltage_request, phm_store_dal_configuration_data will not be needed for rv. [HOW] step 1: add new functions at pplib interface step 2: add new functions at amdgpu dm and dc Signed-off-by: hersen wu <hersenxs.wu@amd.com> Reviewed-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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parent
49ebca7986
commit
9ed9203c3e
6 changed files with 165 additions and 9 deletions
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@ -276,6 +276,10 @@ struct amd_pm_funcs {
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struct amd_pp_simple_clock_info *clocks);
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int (*notify_smu_enable_pwe)(void *handle);
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int (*enable_mgpu_fan_boost)(void *handle);
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int (*set_active_display_count)(void *handle, uint32_t count);
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int (*set_hard_min_dcefclk_by_freq)(void *handle, uint32_t clock);
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int (*set_hard_min_fclk_by_freq)(void *handle, uint32_t clock);
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int (*set_min_deep_sleep_dcefclk)(void *handle, uint32_t clock);
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};
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#endif
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@ -725,7 +725,7 @@ static int pp_dpm_force_clock_level(void *handle,
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}
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
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pr_info("force clock level is for dpm manual mode only.\n");
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pr_debug("force clock level is for dpm manual mode only.\n");
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return -EINVAL;
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}
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@ -899,7 +899,7 @@ static int pp_set_power_profile_mode(void *handle, long *input, uint32_t size)
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}
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if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
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pr_info("power profile setting is for manual dpm mode only.\n");
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pr_debug("power profile setting is for manual dpm mode only.\n");
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return ret;
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}
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@ -1072,7 +1072,7 @@ static int pp_get_current_clocks(void *handle,
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&hw_clocks, PHM_PerformanceLevelDesignation_Activity);
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if (ret) {
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pr_info("Error in phm_get_clock_info \n");
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pr_debug("Error in phm_get_clock_info \n");
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mutex_unlock(&hwmgr->smu_lock);
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return -EINVAL;
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}
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@ -1332,6 +1332,78 @@ static int pp_enable_mgpu_fan_boost(void *handle)
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return 0;
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}
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static int pp_set_min_deep_sleep_dcefclk(void *handle, uint32_t clock)
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{
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struct pp_hwmgr *hwmgr = handle;
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if (!hwmgr || !hwmgr->pm_en)
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return -EINVAL;
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if (hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk == NULL) {
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pr_debug("%s was not implemented.\n", __func__);
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return -EINVAL;;
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}
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mutex_lock(&hwmgr->smu_lock);
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hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
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mutex_unlock(&hwmgr->smu_lock);
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return 0;
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}
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static int pp_set_hard_min_dcefclk_by_freq(void *handle, uint32_t clock)
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{
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struct pp_hwmgr *hwmgr = handle;
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if (!hwmgr || !hwmgr->pm_en)
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return -EINVAL;
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if (hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq == NULL) {
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pr_debug("%s was not implemented.\n", __func__);
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return -EINVAL;;
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}
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mutex_lock(&hwmgr->smu_lock);
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hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
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mutex_unlock(&hwmgr->smu_lock);
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return 0;
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}
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static int pp_set_hard_min_fclk_by_freq(void *handle, uint32_t clock)
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{
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struct pp_hwmgr *hwmgr = handle;
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if (!hwmgr || !hwmgr->pm_en)
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return -EINVAL;
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if (hwmgr->hwmgr_func->set_hard_min_fclk_by_freq == NULL) {
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pr_debug("%s was not implemented.\n", __func__);
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return -EINVAL;;
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}
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mutex_lock(&hwmgr->smu_lock);
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hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
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mutex_unlock(&hwmgr->smu_lock);
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return 0;
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}
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static int pp_set_active_display_count(void *handle, uint32_t count)
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{
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struct pp_hwmgr *hwmgr = handle;
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int ret = 0;
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if (!hwmgr || !hwmgr->pm_en)
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return -EINVAL;
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mutex_lock(&hwmgr->smu_lock);
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ret = phm_set_active_display_count(hwmgr, count);
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mutex_unlock(&hwmgr->smu_lock);
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return ret;
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}
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static const struct amd_pm_funcs pp_dpm_funcs = {
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.load_firmware = pp_dpm_load_fw,
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.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
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@ -1378,4 +1450,8 @@ static const struct amd_pm_funcs pp_dpm_funcs = {
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.get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
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.notify_smu_enable_pwe = pp_notify_smu_enable_pwe,
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.enable_mgpu_fan_boost = pp_enable_mgpu_fan_boost,
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.set_active_display_count = pp_set_active_display_count,
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.set_min_deep_sleep_dcefclk = pp_set_min_deep_sleep_dcefclk,
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.set_hard_min_dcefclk_by_freq = pp_set_hard_min_dcefclk_by_freq,
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.set_hard_min_fclk_by_freq = pp_set_hard_min_fclk_by_freq,
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};
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@ -286,8 +286,8 @@ int phm_store_dal_configuration_data(struct pp_hwmgr *hwmgr,
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if (display_config == NULL)
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return -EINVAL;
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if (NULL != hwmgr->hwmgr_func->set_deep_sleep_dcefclk)
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hwmgr->hwmgr_func->set_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
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if (NULL != hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk)
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hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, display_config->min_dcef_deep_sleep_set_clk);
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for (index = 0; index < display_config->num_path_including_non_display; index++) {
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if (display_config->displays[index].controller_id != 0)
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@ -478,3 +478,44 @@ int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr)
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return hwmgr->hwmgr_func->disable_smc_firmware_ctf(hwmgr);
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}
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int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (!hwmgr->hwmgr_func->set_active_display_count)
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return -EINVAL;
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return hwmgr->hwmgr_func->set_active_display_count(hwmgr, count);
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}
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int phm_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (!hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk)
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return -EINVAL;
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return hwmgr->hwmgr_func->set_min_deep_sleep_dcefclk(hwmgr, clock);
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}
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int phm_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (!hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq)
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return -EINVAL;
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return hwmgr->hwmgr_func->set_hard_min_dcefclk_by_freq(hwmgr, clock);
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}
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int phm_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
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{
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PHM_FUNC_CHECK(hwmgr);
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if (!hwmgr->hwmgr_func->set_hard_min_fclk_by_freq)
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return -EINVAL;
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return hwmgr->hwmgr_func->set_hard_min_fclk_by_freq(hwmgr, clock);
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}
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@ -216,12 +216,12 @@ static inline uint32_t convert_10k_to_mhz(uint32_t clock)
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return (clock + 99) / 100;
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}
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static int smu10_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
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static int smu10_set_min_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
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{
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struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
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if (smu10_data->need_min_deep_sleep_dcefclk &&
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smu10_data->deep_sleep_dcefclk != convert_10k_to_mhz(clock)) {
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smu10_data->deep_sleep_dcefclk != convert_10k_to_mhz(clock)) {
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smu10_data->deep_sleep_dcefclk = convert_10k_to_mhz(clock);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetMinDeepSleepDcefclk,
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@ -230,6 +230,34 @@ static int smu10_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
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return 0;
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}
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static int smu10_set_hard_min_dcefclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
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{
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struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
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if (smu10_data->dcf_actual_hard_min_freq &&
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smu10_data->dcf_actual_hard_min_freq != convert_10k_to_mhz(clock)) {
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smu10_data->dcf_actual_hard_min_freq = convert_10k_to_mhz(clock);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinDcefclkByFreq,
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smu10_data->dcf_actual_hard_min_freq);
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}
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return 0;
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}
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static int smu10_set_hard_min_fclk_by_freq(struct pp_hwmgr *hwmgr, uint32_t clock)
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{
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struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
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if (smu10_data->f_actual_hard_min_freq &&
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smu10_data->f_actual_hard_min_freq != convert_10k_to_mhz(clock)) {
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smu10_data->f_actual_hard_min_freq = convert_10k_to_mhz(clock);
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smum_send_msg_to_smc_with_parameter(hwmgr,
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PPSMC_MSG_SetHardMinFclkByFreq,
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smu10_data->f_actual_hard_min_freq);
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}
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return 0;
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}
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static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
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{
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struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
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@ -1206,7 +1234,7 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
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.get_max_high_clocks = smu10_get_max_high_clocks,
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.read_sensor = smu10_read_sensor,
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.set_active_display_count = smu10_set_active_display_count,
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.set_deep_sleep_dcefclk = smu10_set_deep_sleep_dcefclk,
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.set_min_deep_sleep_dcefclk = smu10_set_min_deep_sleep_dcefclk,
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.dynamic_state_management_enable = smu10_enable_dpm_tasks,
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.power_off_asic = smu10_power_off_asic,
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.asic_setup = smu10_setup_asic_task,
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@ -1217,6 +1245,8 @@ static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
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.display_clock_voltage_request = smu10_display_clock_voltage_request,
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.powergate_gfx = smu10_gfx_off_control,
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.powergate_sdma = smu10_powergate_sdma,
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.set_hard_min_dcefclk_by_freq = smu10_set_hard_min_dcefclk_by_freq,
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.set_hard_min_fclk_by_freq = smu10_set_hard_min_fclk_by_freq,
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};
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int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
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@ -463,5 +463,8 @@ extern int phm_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
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extern int phm_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks);
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extern int phm_disable_smc_firmware_ctf(struct pp_hwmgr *hwmgr);
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extern int phm_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count);
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#endif /* _HARDWARE_MANAGER_H_ */
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@ -309,7 +309,7 @@ struct pp_hwmgr_func {
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int (*avfs_control)(struct pp_hwmgr *hwmgr, bool enable);
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int (*disable_smc_firmware_ctf)(struct pp_hwmgr *hwmgr);
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int (*set_active_display_count)(struct pp_hwmgr *hwmgr, uint32_t count);
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int (*set_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
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int (*set_min_deep_sleep_dcefclk)(struct pp_hwmgr *hwmgr, uint32_t clock);
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int (*start_thermal_controller)(struct pp_hwmgr *hwmgr, struct PP_TemperatureRange *range);
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int (*notify_cac_buffer_info)(struct pp_hwmgr *hwmgr,
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uint32_t virtual_addr_low,
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@ -332,6 +332,8 @@ struct pp_hwmgr_func {
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int (*smus_notify_pwe)(struct pp_hwmgr *hwmgr);
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int (*powergate_sdma)(struct pp_hwmgr *hwmgr, bool bgate);
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int (*enable_mgpu_fan_boost)(struct pp_hwmgr *hwmgr);
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int (*set_hard_min_dcefclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
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int (*set_hard_min_fclk_by_freq)(struct pp_hwmgr *hwmgr, uint32_t clock);
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};
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struct pp_table_func {
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