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wifi: rtw89: set response rate selection
With suitable response rate, it can acknowledge peer packets are received. Otherwise, peer could re-transmit again due to missing of ACK frames. To achieve this, refer to RX rate and CMAC table to choose the smaller as initial response rate. Signed-off-by: Chia-Yuan Li <leo.li@realtek.com> Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220908051257.25353-6-pkshih@realtek.com
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755fda37b9
commit
9ef9edb9e8
5 changed files with 54 additions and 2 deletions
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@ -2553,6 +2553,11 @@ struct rtw89_imr_info {
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u32 tmac_imr_set;
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};
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struct rtw89_rrsr_cfgs {
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struct rtw89_reg3_def ref_rate;
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struct rtw89_reg3_def rsc;
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};
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struct rtw89_dig_regs {
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u32 seg0_pd_reg;
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u32 pd_lower_bound_mask;
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@ -2677,6 +2682,7 @@ struct rtw89_chip_info {
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const struct rtw89_reg_def *dcfo_comp;
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u8 dcfo_comp_sft;
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const struct rtw89_imr_info *imr_info;
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const struct rtw89_rrsr_cfgs *rrsr_cfgs;
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};
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union rtw89_bus_info {
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@ -1979,6 +1979,8 @@ static int tmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
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static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
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{
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const struct rtw89_chip_info *chip = rtwdev->chip;
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const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs;
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u32 reg, val, sifs;
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int ret;
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@ -2009,6 +2011,11 @@ static int trxptcl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
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reg = rtw89_mac_reg_by_idx(R_AX_RXTRIG_TEST_USER_2, mac_idx);
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rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN);
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reg = rtw89_mac_reg_by_idx(rrsr->ref_rate.addr, mac_idx);
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rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data);
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reg = rtw89_mac_reg_by_idx(rrsr->rsc.addr, mac_idx);
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rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data);
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return 0;
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}
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@ -2087,6 +2094,7 @@ static int rmac_init(struct rtw89_dev *rtwdev, u8 mac_idx)
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static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)
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{
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enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
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u32 val, reg;
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int ret;
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@ -2101,6 +2109,11 @@ static int cmac_com_init(struct rtw89_dev *rtwdev, u8 mac_idx)
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val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK);
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rtw89_write32(rtwdev, reg, val);
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if (chip_id == RTL8852A || chip_id == RTL8852B) {
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reg = rtw89_mac_reg_by_idx(R_AX_PTCL_RRSR1, mac_idx);
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rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN);
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}
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return 0;
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}
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@ -1833,6 +1833,13 @@
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#define B_AX_TXSC_40M_MASK GENMASK(7, 4)
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#define B_AX_TXSC_20M_MASK GENMASK(3, 0)
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#define R_AX_PTCL_RRSR1 0xC090
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#define R_AX_PTCL_RRSR1_C1 0xE090
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#define B_AX_RRSR_RATE_EN_MASK GENMASK(11, 8)
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#define RRSR_OFDM_CCK_EN 3
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#define B_AX_RSC_MASK GENMASK(7, 6)
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#define B_AX_RRSR_CCK_MASK GENMASK(3, 0)
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#define R_AX_CMAC_ERR_IMR 0xC160
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#define R_AX_CMAC_ERR_IMR_C1 0xE160
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#define B_AX_WMAC_TX_ERR_IND_EN BIT(7)
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@ -2563,6 +2570,20 @@
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#define WMAC_SPEC_SIFS_OFDM_52C 0x11
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#define WMAC_SPEC_SIFS_CCK 0xA
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#define R_AX_TRXPTCL_RRSR_CTL_0 0xCC08
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#define R_AX_TRXPTCL_RRSR_CTL_0_C1 0xEC08
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#define B_AX_RESP_TX_MACID_CCA_TH_EN BIT(31)
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#define B_AX_RESP_TX_PWRMODE_MASK GENMASK(30, 28)
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#define B_AX_FTM_RRSR_RATE_EN_MASK GENMASK(27, 24)
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#define B_AX_NESS_MASK GENMASK(23, 22)
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#define B_AX_WMAC_RESP_DOPPLEB_AX_EN BIT(21)
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#define B_AX_WMAC_RESP_DCM_EN BIT(20)
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#define B_AX_WMAC_RRSB_AX_CCK_MASK GENMASK(19, 16)
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#define B_AX_WMAC_RESP_RATE_EN_MASK GENMASK(15, 12)
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#define B_AX_WMAC_RESP_RSC_MASK GENMASK(11, 10)
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#define B_AX_WMAC_RESP_REF_RATE_SEL BIT(9)
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#define B_AX_WMAC_RESP_REF_RATE_MASK GENMASK(8, 0)
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#define R_AX_MAC_LOOPBACK 0xCC20
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#define R_AX_MAC_LOOPBACK_C1 0xEC20
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#define B_AX_MACLBK_EN BIT(0)
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@ -453,6 +453,11 @@ static const struct rtw89_imr_info rtw8852a_imr_info = {
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.tmac_imr_set = B_AX_TMAC_IMR_SET,
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};
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static const struct rtw89_rrsr_cfgs rtw8852a_rrsr_cfgs = {
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.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
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.rsc = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_RSC_MASK, 2},
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};
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static const struct rtw89_dig_regs rtw8852a_dig_regs = {
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.seg0_pd_reg = R_SEG0R_PD,
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.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
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@ -2224,7 +2229,8 @@ const struct rtw89_chip_info rtw8852a_chip_info = {
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.page_regs = &rtw8852a_page_regs,
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.dcfo_comp = &rtw8852a_dcfo_comp,
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.dcfo_comp_sft = 3,
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.imr_info = &rtw8852a_imr_info
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.imr_info = &rtw8852a_imr_info,
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.rrsr_cfgs = &rtw8852a_rrsr_cfgs,
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};
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EXPORT_SYMBOL(rtw8852a_chip_info);
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@ -131,6 +131,11 @@ static const struct rtw89_imr_info rtw8852c_imr_info = {
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.tmac_imr_set = B_AX_TMAC_IMR_SET_V1,
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};
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static const struct rtw89_rrsr_cfgs rtw8852c_rrsr_cfgs = {
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.ref_rate = {R_AX_TRXPTCL_RRSR_CTL_0, B_AX_WMAC_RESP_REF_RATE_SEL, 0},
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.rsc = {R_AX_PTCL_RRSR1, B_AX_RSC_MASK, 2},
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};
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static const struct rtw89_dig_regs rtw8852c_dig_regs = {
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.seg0_pd_reg = R_SEG0R_PD,
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.pd_lower_bound_mask = B_SEG0R_PD_LOWER_BOUND_MSK,
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@ -3068,7 +3073,8 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
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.page_regs = &rtw8852c_page_regs,
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.dcfo_comp = &rtw8852c_dcfo_comp,
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.dcfo_comp_sft = 5,
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.imr_info = &rtw8852c_imr_info
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.imr_info = &rtw8852c_imr_info,
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.rrsr_cfgs = &rtw8852c_rrsr_cfgs,
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};
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EXPORT_SYMBOL(rtw8852c_chip_info);
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