mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-05 08:26:59 +00:00
intel-pinctrl for v6.5-1
* Fix of OPEN DRAIN pin mode setting in a few drivers * Reduce a scope of spin lock in the Bay Trail driver * Decrease a code footprint by refactoring in a few drivers * Expand string choices and reuse that in the Bay Trail driver The following is an automated git shortlog grouped by driver: baytrail: - invert if condition - add warning for BYT_VAL_REG retrieval failure - reduce scope of spinlock in ->dbg_show() hook - Use str_hi_lo() helper - Use BIT() in BYT_PULL_ASSIGN_* definitions - Unify style of error and debug messages cherryview: - Drop goto label - Return correct value if pin in push-pull mode - Don't use IRQ core constanst for invalid IRQ intel: - refine ->irq_set_type() hook - refine ->set_mux() hook - Add Intel Meteor Lake-S pin controller support lib/string_helpers: - Add str_high_low() helper - Split out string_choices.h - Add missing header files to MAINTAINERS database merrifield: - Use BUFCFG_PINMODE_GPIO in ->pin_dbg_show() - Fix open-drain pin mode configuration moorefield: - Use BUFCFG_PINMODE_GPIO in ->pin_dbg_show() - Fix open-drain pin mode configuration -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEEqaflIX74DDDzMJJtb7wzTHR8rCgFAmSRp98ACgkQb7wzTHR8 rCj6Dw//Xi5Rf3XcUIi0XAOVX0JR6iTJ9DuxLteGDesnKKah6zdNa5ncE6zy6KFc X9ulqLpVMwwPc8nl2bnxan8v905L7Ox8iL6M/BR6k51Gv67ud5DSd7Q2bxqXfYc3 qenZL+GMIe5Cz1UpPJtmnwlGyLAlRE8OByZvEtGrjmJ6W1OnuESmW58T15AjLkiL I9xTNFwXXuQOl2FOWk/uOdvNZaXIo/cKgvS9dO/PDQDxgjO19NvEwLKqdj2gZsY0 QGDg5iFlZ8mkfVtk8Xsvgd23rpWHuTANMLgG6xQtjxs2idpUDQgF5AC4bvg0chi5 sC7KbvW1qDXPfmhgL3LHx3EYc9uoc3CpAV5sC8A+QfvBwwzDwtzg0rV2Mg8vMs8U A2UjcggyfvyzYwB02lIccx1Vk2/8zhdT8mmyqiK4FZbDOJGZ7hELEIhlmF56x9dJ aN9AiZbNJKhF8NtXM1KFGTHmVit2+OrbGSodQoTDRW/Hg2DjddlssqIgMQIFq5EB zx6iYIxO94+FDpLrgwgGH8pwgm1YPkKfDvYYfk/NYGjYMrSFtg5AShyzQ6PlUC2R 0QSoa6NdLvHR7kwXUru2vlt4DOX7UtrOEURwt3nLzEFgOPDs0S1+pqO6JQWcADSf udQfwGNo3o9m34L5DF5Ubzm6xq1QjW4Pkz/h/dkjkxE6NeWexuY= =pJDH -----END PGP SIGNATURE----- Merge tag 'intel-pinctrl-v6.5-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel into devel intel-pinctrl for v6.5-1 * Fix of OPEN DRAIN pin mode setting in a few drivers * Reduce a scope of spin lock in the Bay Trail driver * Decrease a code footprint by refactoring in a few drivers * Expand string choices and reuse that in the Bay Trail driver The following is an automated git shortlog grouped by driver: baytrail: - invert if condition - add warning for BYT_VAL_REG retrieval failure - reduce scope of spinlock in ->dbg_show() hook - Use str_hi_lo() helper - Use BIT() in BYT_PULL_ASSIGN_* definitions - Unify style of error and debug messages cherryview: - Drop goto label - Return correct value if pin in push-pull mode - Don't use IRQ core constanst for invalid IRQ intel: - refine ->irq_set_type() hook - refine ->set_mux() hook - Add Intel Meteor Lake-S pin controller support lib/string_helpers: - Add str_high_low() helper - Split out string_choices.h - Add missing header files to MAINTAINERS database merrifield: - Use BUFCFG_PINMODE_GPIO in ->pin_dbg_show() - Fix open-drain pin mode configuration moorefield: - Use BUFCFG_PINMODE_GPIO in ->pin_dbg_show() - Fix open-drain pin mode configuration
This commit is contained in:
commit
9f0648f13e
9 changed files with 373 additions and 132 deletions
|
@ -8670,6 +8670,9 @@ F: drivers/input/touchscreen/resistive-adc-touch.c
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GENERIC STRING LIBRARY
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R: Andy Shevchenko <andy@kernel.org>
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S: Maintained
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F: include/linux/string.h
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F: include/linux/string_choices.h
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F: include/linux/string_helpers.h
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F: lib/string.c
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F: lib/string_helpers.c
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F: lib/test_string.c
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@ -18,6 +18,7 @@
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#include <linux/pm_runtime.h>
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#include <linux/property.h>
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#include <linux/seq_file.h>
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#include <linux/string_helpers.h>
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#include <linux/pinctrl/pinctrl.h>
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#include <linux/pinctrl/pinmux.h>
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@ -52,10 +53,9 @@
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#define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
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#define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
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#define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
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#define BYT_PULL_ASSIGN_SHIFT 7
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#define BYT_PULL_ASSIGN_MASK GENMASK(8, 7)
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#define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
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#define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
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#define BYT_PULL_ASSIGN_DOWN BIT(8)
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#define BYT_PULL_ASSIGN_UP BIT(7)
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#define BYT_PIN_MUX GENMASK(2, 0)
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/* BYT_VAL_REG register bits */
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@ -668,8 +668,7 @@ static void byt_set_group_simple_mux(struct intel_pinctrl *vg,
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padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
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if (!padcfg0) {
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dev_warn(vg->dev,
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"Group %s, pin %i not muxed (no padcfg0)\n",
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dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
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group.grp.name, i);
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continue;
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}
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@ -698,8 +697,7 @@ static void byt_set_group_mixed_mux(struct intel_pinctrl *vg,
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padcfg0 = byt_gpio_reg(vg, group.grp.pins[i], BYT_CONF0_REG);
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if (!padcfg0) {
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dev_warn(vg->dev,
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"Group %s, pin %i not muxed (no padcfg0)\n",
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dev_warn(vg->dev, "Group %s, pin %i not muxed (can't retrieve CONF0)\n",
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group.grp.name, i);
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continue;
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}
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@ -755,9 +753,7 @@ static void byt_gpio_clear_triggering(struct intel_pinctrl *vg, unsigned int off
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value = readl(reg);
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/* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
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if (value & BYT_DIRECT_IRQ_EN)
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/* nothing to do */ ;
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else
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if (!(value & BYT_DIRECT_IRQ_EN))
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value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
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writel(value, reg);
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@ -791,7 +787,7 @@ static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
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value |= gpio_mux;
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writel(value, reg);
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dev_warn(vg->dev, FW_BUG "pin %u forcibly re-configured as GPIO\n", offset);
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dev_warn(vg->dev, FW_BUG "Pin %i: forcibly re-configured as GPIO\n", offset);
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}
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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@ -823,7 +819,9 @@ static void byt_gpio_direct_irq_check(struct intel_pinctrl *vg,
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* themselves in the foot.
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*/
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if (readl(conf_reg) & BYT_DIRECT_IRQ_EN)
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dev_info_once(vg->dev, "Potential Error: Setting GPIO with direct_irq_en to output");
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dev_info_once(vg->dev,
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"Potential Error: Pin %i: forcibly set GPIO with DIRECT_IRQ_EN to output\n",
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offset);
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}
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static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
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@ -1026,9 +1024,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
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if (val & BYT_INPUT_EN) {
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val &= ~BYT_INPUT_EN;
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writel(val, val_reg);
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dev_warn(vg->dev,
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"pin %u forcibly set to input mode\n",
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offset);
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dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
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}
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conf &= ~BYT_PULL_ASSIGN_MASK;
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@ -1048,9 +1044,7 @@ static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
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if (val & BYT_INPUT_EN) {
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val &= ~BYT_INPUT_EN;
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writel(val, val_reg);
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dev_warn(vg->dev,
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"pin %u forcibly set to input mode\n",
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offset);
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dev_warn(vg->dev, "Pin %i: forcibly set to input mode\n", offset);
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}
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conf &= ~BYT_PULL_ASSIGN_MASK;
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@ -1245,39 +1239,35 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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for (i = 0; i < vg->soc->npins; i++) {
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const struct intel_community *comm;
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void __iomem *conf_reg, *val_reg;
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const char *pull_str = NULL;
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const char *pull = NULL;
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void __iomem *reg;
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unsigned long flags;
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const char *label;
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unsigned int pin;
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raw_spin_lock_irqsave(&byt_lock, flags);
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pin = vg->soc->pins[i].number;
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reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
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if (!reg) {
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seq_printf(s,
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"Could not retrieve pin %i conf0 reg\n",
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pin);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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continue;
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}
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conf0 = readl(reg);
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reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
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if (!reg) {
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seq_printf(s,
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"Could not retrieve pin %i val reg\n", pin);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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conf_reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
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if (!conf_reg) {
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seq_printf(s, "Pin %i: can't retrieve CONF0\n", pin);
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continue;
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}
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val = readl(reg);
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val_reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
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if (!val_reg) {
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seq_printf(s, "Pin %i: can't retrieve VAL\n", pin);
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continue;
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}
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raw_spin_lock_irqsave(&byt_lock, flags);
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conf0 = readl(conf_reg);
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val = readl(val_reg);
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raw_spin_unlock_irqrestore(&byt_lock, flags);
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comm = byt_get_community(vg, pin);
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if (!comm) {
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seq_printf(s,
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"Could not get community for pin %i\n", pin);
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seq_printf(s, "Pin %i: can't retrieve community\n", pin);
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continue;
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}
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label = gpiochip_is_requested(chip, i);
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@ -1314,7 +1304,7 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
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label,
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val & BYT_INPUT_EN ? " " : "in",
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val & BYT_OUTPUT_EN ? " " : "out",
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val & BYT_LEVEL ? "hi" : "lo",
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str_hi_lo(val & BYT_LEVEL),
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comm->pad_map[i], comm->pad_map[i] * 16,
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conf0 & 0x7,
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conf0 & BYT_TRIG_NEG ? " fall" : " ",
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@ -1429,7 +1419,7 @@ static int byt_irq_type(struct irq_data *d, unsigned int type)
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value = readl(reg);
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WARN(value & BYT_DIRECT_IRQ_EN,
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"Bad pad config for io mode, force direct_irq_en bit clearing");
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"Bad pad config for IO mode, force DIRECT_IRQ_EN bit clearing");
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/* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
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* are used to indicate high and low level triggering
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@ -1476,9 +1466,7 @@ static void byt_gpio_irq_handler(struct irq_desc *desc)
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reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
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if (!reg) {
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dev_warn(vg->dev,
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"Pin %i: could not retrieve interrupt status register\n",
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base);
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dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
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continue;
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}
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@ -1501,7 +1489,7 @@ static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 c
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sizeof(direct_irq_mux));
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match = memchr(direct_irq_mux, pin, sizeof(direct_irq_mux));
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if (!match) {
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dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set but no IRQ assigned, clearing\n", pin);
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dev_warn(vg->dev, FW_BUG "Pin %i: DIRECT_IRQ_EN set but no IRQ assigned, clearing\n", pin);
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return false;
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}
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@ -1528,7 +1516,8 @@ static bool byt_direct_irq_sanity_check(struct intel_pinctrl *vg, int pin, u32 c
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trig = conf0 & BYT_TRIG_MASK;
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if (trig != (BYT_TRIG_POS | BYT_TRIG_LVL) &&
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trig != (BYT_TRIG_NEG | BYT_TRIG_LVL)) {
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dev_warn(vg->dev, FW_BUG "pin %i: direct_irq_en set without trigger (conf0: %xh), clearing\n",
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dev_warn(vg->dev,
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FW_BUG "Pin %i: DIRECT_IRQ_EN set without trigger (CONF0: %#08x), clearing\n",
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pin, conf0);
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return false;
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}
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@ -1555,9 +1544,7 @@ static void byt_init_irq_valid_mask(struct gpio_chip *chip,
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reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
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if (!reg) {
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dev_warn(vg->dev,
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"Pin %i: could not retrieve conf0 register\n",
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i);
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dev_warn(vg->dev, "Pin %i: could not retrieve CONF0\n", i);
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continue;
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}
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@ -1588,9 +1575,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
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reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
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if (!reg) {
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dev_warn(vg->dev,
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"Pin %i: could not retrieve irq status reg\n",
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base);
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dev_warn(vg->dev, "Pin %i: can't retrieve INT_STAT%u\n", base / 32, base);
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continue;
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}
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@ -1600,7 +1585,7 @@ static int byt_gpio_irq_init_hw(struct gpio_chip *chip)
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value = readl(reg);
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if (value)
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dev_err(vg->dev,
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"GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
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"GPIO interrupt error, pins misconfigured. INT_STAT%u: %#08x\n",
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base / 32, value);
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}
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@ -1764,15 +1749,17 @@ static int byt_gpio_suspend(struct device *dev)
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reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
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if (!reg) {
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dev_warn(vg->dev,
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"Pin %i: could not retrieve conf0 register\n",
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i);
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dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
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continue;
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}
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value = readl(reg) & BYT_CONF0_RESTORE_MASK;
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vg->context.pads[i].conf0 = value;
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reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
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if (!reg) {
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dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
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continue;
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}
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value = readl(reg) & BYT_VAL_RESTORE_MASK;
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vg->context.pads[i].val = value;
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}
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@ -1796,9 +1783,7 @@ static int byt_gpio_resume(struct device *dev)
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reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
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if (!reg) {
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dev_warn(vg->dev,
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"Pin %i: could not retrieve conf0 register\n",
|
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i);
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dev_warn(vg->dev, "Pin %i: can't retrieve CONF0\n", i);
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continue;
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}
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value = readl(reg);
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|
@ -1807,10 +1792,14 @@ static int byt_gpio_resume(struct device *dev)
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value &= ~BYT_CONF0_RESTORE_MASK;
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value |= vg->context.pads[i].conf0;
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writel(value, reg);
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dev_info(dev, "restored pin %d conf0 %#08x", i, value);
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dev_info(dev, "restored pin %d CONF0 %#08x", i, value);
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}
|
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|
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reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
|
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if (!reg) {
|
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dev_warn(vg->dev, "Pin %i: can't retrieve VAL\n", i);
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continue;
|
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}
|
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value = readl(reg);
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if ((value & BYT_VAL_RESTORE_MASK) !=
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vg->context.pads[i].val) {
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|
@ -1820,8 +1809,7 @@ static int byt_gpio_resume(struct device *dev)
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v |= vg->context.pads[i].val;
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if (v != value) {
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writel(v, reg);
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dev_dbg(dev, "restored pin %d val %#08x\n",
|
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i, v);
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dev_dbg(dev, "restored pin %d VAL %#08x\n", i, v);
|
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}
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}
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}
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|
|
|
@ -75,7 +75,7 @@ struct intel_pad_context {
|
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u32 padctrl1;
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};
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||||
|
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#define CHV_INVALID_HWIRQ ((unsigned int)INVALID_HWIRQ)
|
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#define CHV_INVALID_HWIRQ (~0U)
|
||||
|
||||
/**
|
||||
* struct intel_community_context - community context for Cherryview
|
||||
|
@ -949,11 +949,6 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
|||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
if (!(ctrl1 & CHV_PADCTRL1_ODEN))
|
||||
return -EINVAL;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_BIAS_HIGH_IMPEDANCE: {
|
||||
u32 cfg;
|
||||
|
||||
|
@ -963,6 +958,16 @@ static int chv_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
|||
return -EINVAL;
|
||||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
if (ctrl1 & CHV_PADCTRL1_ODEN)
|
||||
return -EINVAL;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
if (!(ctrl1 & CHV_PADCTRL1_ODEN))
|
||||
return -EINVAL;
|
||||
break;
|
||||
}
|
||||
|
||||
default:
|
||||
|
@ -1408,8 +1413,10 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
|
|||
raw_spin_lock_irqsave(&chv_lock, flags);
|
||||
|
||||
ret = chv_gpio_set_intr_line(pctrl, hwirq);
|
||||
if (ret)
|
||||
goto out_unlock;
|
||||
if (ret) {
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* Pins which can be used as shared interrupt are configured in
|
||||
|
@ -1450,10 +1457,9 @@ static int chv_gpio_irq_type(struct irq_data *d, unsigned int type)
|
|||
else if (type & IRQ_TYPE_LEVEL_MASK)
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
out_unlock:
|
||||
raw_spin_unlock_irqrestore(&chv_lock, flags);
|
||||
|
||||
return ret;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct irq_chip chv_gpio_irq_chip = {
|
||||
|
|
|
@ -55,12 +55,11 @@
|
|||
|
||||
/* Offset from pad_regs */
|
||||
#define PADCFG0 0x000
|
||||
#define PADCFG0_RXEVCFG_SHIFT 25
|
||||
#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
|
||||
#define PADCFG0_RXEVCFG_LEVEL 0
|
||||
#define PADCFG0_RXEVCFG_EDGE 1
|
||||
#define PADCFG0_RXEVCFG_DISABLED 2
|
||||
#define PADCFG0_RXEVCFG_EDGE_BOTH 3
|
||||
#define PADCFG0_RXEVCFG_LEVEL (0 << 25)
|
||||
#define PADCFG0_RXEVCFG_EDGE (1 << 25)
|
||||
#define PADCFG0_RXEVCFG_DISABLED (2 << 25)
|
||||
#define PADCFG0_RXEVCFG_EDGE_BOTH (3 << 25)
|
||||
#define PADCFG0_PREGFRXSEL BIT(24)
|
||||
#define PADCFG0_RXINV BIT(23)
|
||||
#define PADCFG0_GPIROUTIOXAPIC BIT(20)
|
||||
|
@ -411,18 +410,19 @@ static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
|
|||
/* Now enable the mux setting for each pin in the group */
|
||||
for (i = 0; i < grp->grp.npins; i++) {
|
||||
void __iomem *padcfg0;
|
||||
u32 value;
|
||||
u32 value, pmode;
|
||||
|
||||
padcfg0 = intel_get_padcfg(pctrl, grp->grp.pins[i], PADCFG0);
|
||||
value = readl(padcfg0);
|
||||
|
||||
value = readl(padcfg0);
|
||||
value &= ~PADCFG0_PMODE_MASK;
|
||||
|
||||
if (grp->modes)
|
||||
value |= grp->modes[i] << PADCFG0_PMODE_SHIFT;
|
||||
pmode = grp->modes[i];
|
||||
else
|
||||
value |= grp->mode << PADCFG0_PMODE_SHIFT;
|
||||
pmode = grp->mode;
|
||||
|
||||
value |= pmode << PADCFG0_PMODE_SHIFT;
|
||||
writel(value, padcfg0);
|
||||
}
|
||||
|
||||
|
@ -1126,9 +1126,9 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
|
|||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
|
||||
unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
|
||||
u32 rxevcfg, rxinv, value;
|
||||
unsigned long flags;
|
||||
void __iomem *reg;
|
||||
u32 value;
|
||||
|
||||
reg = intel_get_padcfg(pctrl, pin, PADCFG0);
|
||||
if (!reg)
|
||||
|
@ -1144,27 +1144,31 @@ static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
|
|||
return -EPERM;
|
||||
}
|
||||
|
||||
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
|
||||
rxevcfg = PADCFG0_RXEVCFG_EDGE_BOTH;
|
||||
} else if (type & IRQ_TYPE_EDGE_FALLING) {
|
||||
rxevcfg = PADCFG0_RXEVCFG_EDGE;
|
||||
} else if (type & IRQ_TYPE_EDGE_RISING) {
|
||||
rxevcfg = PADCFG0_RXEVCFG_EDGE;
|
||||
} else if (type & IRQ_TYPE_LEVEL_MASK) {
|
||||
rxevcfg = PADCFG0_RXEVCFG_LEVEL;
|
||||
} else {
|
||||
rxevcfg = PADCFG0_RXEVCFG_DISABLED;
|
||||
}
|
||||
|
||||
if (type == IRQ_TYPE_EDGE_FALLING || type == IRQ_TYPE_LEVEL_LOW)
|
||||
rxinv = PADCFG0_RXINV;
|
||||
else
|
||||
rxinv = 0;
|
||||
|
||||
raw_spin_lock_irqsave(&pctrl->lock, flags);
|
||||
|
||||
intel_gpio_set_gpio_mode(reg);
|
||||
|
||||
value = readl(reg);
|
||||
|
||||
value &= ~(PADCFG0_RXEVCFG_MASK | PADCFG0_RXINV);
|
||||
|
||||
if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
|
||||
value |= PADCFG0_RXEVCFG_EDGE_BOTH << PADCFG0_RXEVCFG_SHIFT;
|
||||
} else if (type & IRQ_TYPE_EDGE_FALLING) {
|
||||
value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
|
||||
value |= PADCFG0_RXINV;
|
||||
} else if (type & IRQ_TYPE_EDGE_RISING) {
|
||||
value |= PADCFG0_RXEVCFG_EDGE << PADCFG0_RXEVCFG_SHIFT;
|
||||
} else if (type & IRQ_TYPE_LEVEL_MASK) {
|
||||
if (type & IRQ_TYPE_LEVEL_LOW)
|
||||
value |= PADCFG0_RXINV;
|
||||
} else {
|
||||
value |= PADCFG0_RXEVCFG_DISABLED << PADCFG0_RXEVCFG_SHIFT;
|
||||
}
|
||||
value = (value & ~PADCFG0_RXEVCFG_MASK) | rxevcfg;
|
||||
value = (value & ~PADCFG0_RXINV) | rxinv;
|
||||
|
||||
writel(value, reg);
|
||||
|
||||
|
|
|
@ -549,7 +549,7 @@ static void mrfld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
|
|||
}
|
||||
|
||||
mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
|
||||
if (!mode)
|
||||
if (mode == BUFCFG_PINMODE_GPIO)
|
||||
seq_puts(s, "GPIO ");
|
||||
else
|
||||
seq_printf(s, "mode %d ", mode);
|
||||
|
@ -710,6 +710,11 @@ static int mrfld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
|||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
if (value & BUFCFG_OD_EN)
|
||||
return -EINVAL;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
if (!(value & BUFCFG_OD_EN))
|
||||
return -EINVAL;
|
||||
|
@ -791,10 +796,14 @@ static int mrfld_config_set_pin(struct mrfld_pinctrl *mp, unsigned int pin,
|
|||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
mask |= BUFCFG_OD_EN;
|
||||
bits &= ~BUFCFG_OD_EN;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
mask |= BUFCFG_OD_EN;
|
||||
if (arg)
|
||||
bits |= BUFCFG_OD_EN;
|
||||
bits |= BUFCFG_OD_EN;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_SLEW_RATE:
|
||||
|
@ -826,6 +835,7 @@ static int mrfld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
|||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
case PIN_CONFIG_SLEW_RATE:
|
||||
ret = mrfld_config_set_pin(mp, pin, configs[i]);
|
||||
|
|
|
@ -20,6 +20,12 @@
|
|||
#define MTL_P_GPI_IS 0x200
|
||||
#define MTL_P_GPI_IE 0x210
|
||||
|
||||
#define MTL_S_PAD_OWN 0x0b0
|
||||
#define MTL_S_PADCFGLOCK 0x0f0
|
||||
#define MTL_S_HOSTSW_OWN 0x110
|
||||
#define MTL_S_GPI_IS 0x200
|
||||
#define MTL_S_GPI_IE 0x210
|
||||
|
||||
#define MTL_GPP(r, s, e, g) \
|
||||
{ \
|
||||
.reg_num = (r), \
|
||||
|
@ -28,9 +34,12 @@
|
|||
.gpio_base = (g), \
|
||||
}
|
||||
|
||||
#define MTL_COMMUNITY(b, s, e, g) \
|
||||
#define MTL_P_COMMUNITY(b, s, e, g) \
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_P)
|
||||
|
||||
#define MTL_S_COMMUNITY(b, s, e, g) \
|
||||
INTEL_COMMUNITY_GPPS(b, s, e, g, MTL_S)
|
||||
|
||||
/* Meteor Lake-P */
|
||||
static const struct pinctrl_pin_desc mtlp_pins[] = {
|
||||
/* CPU */
|
||||
|
@ -369,11 +378,11 @@ static const struct intel_padgroup mtlp_community5_gpps[] = {
|
|||
};
|
||||
|
||||
static const struct intel_community mtlp_communities[] = {
|
||||
MTL_COMMUNITY(0, 0, 52, mtlp_community0_gpps),
|
||||
MTL_COMMUNITY(1, 53, 102, mtlp_community1_gpps),
|
||||
MTL_COMMUNITY(2, 103, 183, mtlp_community3_gpps),
|
||||
MTL_COMMUNITY(3, 184, 203, mtlp_community4_gpps),
|
||||
MTL_COMMUNITY(4, 204, 288, mtlp_community5_gpps),
|
||||
MTL_P_COMMUNITY(0, 0, 52, mtlp_community0_gpps),
|
||||
MTL_P_COMMUNITY(1, 53, 102, mtlp_community1_gpps),
|
||||
MTL_P_COMMUNITY(2, 103, 183, mtlp_community3_gpps),
|
||||
MTL_P_COMMUNITY(3, 184, 203, mtlp_community4_gpps),
|
||||
MTL_P_COMMUNITY(4, 204, 288, mtlp_community5_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data mtlp_soc_data = {
|
||||
|
@ -383,8 +392,199 @@ static const struct intel_pinctrl_soc_data mtlp_soc_data = {
|
|||
.ncommunities = ARRAY_SIZE(mtlp_communities),
|
||||
};
|
||||
|
||||
/* Meteor Lake-S */
|
||||
static const struct pinctrl_pin_desc mtls_pins[] = {
|
||||
/* GPP_A */
|
||||
PINCTRL_PIN(0, "DIR_ESPI_IO_0"),
|
||||
PINCTRL_PIN(1, "DIR_ESPI_IO_1"),
|
||||
PINCTRL_PIN(2, "DIR_ESPI_IO_2"),
|
||||
PINCTRL_PIN(3, "DIR_ESPI_IO_3"),
|
||||
PINCTRL_PIN(4, "DIR_ESPI_CS0_B"),
|
||||
PINCTRL_PIN(5, "DIR_ESPI_CLK"),
|
||||
PINCTRL_PIN(6, "DIR_ESPI_RCLK"),
|
||||
PINCTRL_PIN(7, "DIR_ESPI_RESET_B"),
|
||||
PINCTRL_PIN(8, "SLP_S0_B"),
|
||||
PINCTRL_PIN(9, "DMI_PERSTB"),
|
||||
PINCTRL_PIN(10, "CATERR_B"),
|
||||
PINCTRL_PIN(11, "THERMTRIP_B"),
|
||||
PINCTRL_PIN(12, "CPU_C10_GATE_B"),
|
||||
PINCTRL_PIN(13, "PS_ONB"),
|
||||
PINCTRL_PIN(14, "GPP_SA_14"),
|
||||
PINCTRL_PIN(15, "GPP_SA_15"),
|
||||
PINCTRL_PIN(16, "GPP_SA_16"),
|
||||
PINCTRL_PIN(17, "GPP_SA_17"),
|
||||
PINCTRL_PIN(18, "GPP_SA_18"),
|
||||
PINCTRL_PIN(19, "GPP_SA_19"),
|
||||
PINCTRL_PIN(20, "GPP_SA_20"),
|
||||
PINCTRL_PIN(21, "GPP_SA_21"),
|
||||
PINCTRL_PIN(22, "FUSA_DIAGTEST_EN"),
|
||||
PINCTRL_PIN(23, "FUSA_DIAGTEST_MODE"),
|
||||
PINCTRL_PIN(24, "RTCCLKIN"),
|
||||
PINCTRL_PIN(25, "RESET_SYNC_B"),
|
||||
PINCTRL_PIN(26, "PCH_PWROK"),
|
||||
PINCTRL_PIN(27, "DIR_ESPI_CLK_LOOPBACK"),
|
||||
/* vGPIO_0 */
|
||||
PINCTRL_PIN(28, "LPC_ME_FTPM_ENABLE"),
|
||||
PINCTRL_PIN(29, "LPC_DTFUS_CORE_SPITPM_DIS"),
|
||||
PINCTRL_PIN(30, "LPC_SPI_STRAP_TOS"),
|
||||
PINCTRL_PIN(31, "ITSS_KU1_SHTDWN"),
|
||||
PINCTRL_PIN(32, "LPC_PRR_TS_OVR"),
|
||||
PINCTRL_PIN(33, "ESPI_PMC_EC_SCI"),
|
||||
PINCTRL_PIN(34, "ESPI_PMC_EC_SCI1"),
|
||||
PINCTRL_PIN(35, "vGPIO_SPARE0"),
|
||||
PINCTRL_PIN(36, "vGPIO_SPARE1"),
|
||||
PINCTRL_PIN(37, "vGPIO_SPARE2"),
|
||||
PINCTRL_PIN(38, "vGPIO_SPARE3"),
|
||||
PINCTRL_PIN(39, "vGPIO_SPARE8"),
|
||||
PINCTRL_PIN(40, "vGPIO_SPARE9"),
|
||||
PINCTRL_PIN(41, "vGPIO_SPARE10"),
|
||||
PINCTRL_PIN(42, "vGPIO_SPARE11"),
|
||||
PINCTRL_PIN(43, "vGPIO_SPARE12"),
|
||||
PINCTRL_PIN(44, "vGPIO_SPARE13"),
|
||||
PINCTRL_PIN(45, "vGPIO_SPARE14"),
|
||||
PINCTRL_PIN(46, "vGPIO_SPARE15"),
|
||||
/* GPP_C */
|
||||
PINCTRL_PIN(47, "GPP_SC_0"),
|
||||
PINCTRL_PIN(48, "GPP_SC_1"),
|
||||
PINCTRL_PIN(49, "GPP_SC_2"),
|
||||
PINCTRL_PIN(50, "GPP_SC_3"),
|
||||
PINCTRL_PIN(51, "GPP_SC_4"),
|
||||
PINCTRL_PIN(52, "GPP_SC_5"),
|
||||
PINCTRL_PIN(53, "GPP_SC_6"),
|
||||
PINCTRL_PIN(54, "GPP_SC_7"),
|
||||
PINCTRL_PIN(55, "GPP_SC_8"),
|
||||
PINCTRL_PIN(56, "GPP_SC_9"),
|
||||
PINCTRL_PIN(57, "GPP_SC_10"),
|
||||
PINCTRL_PIN(58, "GPP_SC_11"),
|
||||
PINCTRL_PIN(59, "GPP_SC_12"),
|
||||
PINCTRL_PIN(60, "GPP_SC_13"),
|
||||
PINCTRL_PIN(61, "GPP_SC_14"),
|
||||
PINCTRL_PIN(62, "GPP_SC_15"),
|
||||
PINCTRL_PIN(63, "GPP_SC_16"),
|
||||
PINCTRL_PIN(64, "GPP_SC_17"),
|
||||
PINCTRL_PIN(65, "GPP_SC_18"),
|
||||
PINCTRL_PIN(66, "GPP_SC_19"),
|
||||
PINCTRL_PIN(67, "GPP_SC_20"),
|
||||
PINCTRL_PIN(68, "GPP_SC_21"),
|
||||
PINCTRL_PIN(69, "GPP_SC_22"),
|
||||
PINCTRL_PIN(70, "GPP_SC_23"),
|
||||
PINCTRL_PIN(71, "GPP_SC_24"),
|
||||
PINCTRL_PIN(72, "GPP_SC_25"),
|
||||
PINCTRL_PIN(73, "GPP_SC_26"),
|
||||
/* GPP_B */
|
||||
PINCTRL_PIN(74, "GPP_SB_0"),
|
||||
PINCTRL_PIN(75, "GPP_SB_1"),
|
||||
PINCTRL_PIN(76, "GPP_SB_2"),
|
||||
PINCTRL_PIN(77, "GPP_SB_3"),
|
||||
PINCTRL_PIN(78, "GPP_SB_4"),
|
||||
PINCTRL_PIN(79, "GPP_SB_5"),
|
||||
PINCTRL_PIN(80, "GPP_SB_6"),
|
||||
PINCTRL_PIN(81, "GPP_SB_7"),
|
||||
PINCTRL_PIN(82, "GPP_SB_8"),
|
||||
PINCTRL_PIN(83, "GPP_SB_9"),
|
||||
PINCTRL_PIN(84, "GPP_SB_10"),
|
||||
PINCTRL_PIN(85, "GPP_SB_11"),
|
||||
PINCTRL_PIN(86, "GPP_SB_12"),
|
||||
PINCTRL_PIN(87, "GPP_SB_13"),
|
||||
PINCTRL_PIN(88, "GPP_SB_14"),
|
||||
PINCTRL_PIN(89, "GPP_SB_15"),
|
||||
PINCTRL_PIN(90, "GPP_SB_16"),
|
||||
PINCTRL_PIN(91, "PROCHOT_B"),
|
||||
PINCTRL_PIN(92, "BPKI3C_SDA"),
|
||||
PINCTRL_PIN(93, "BPKI3C_SCL"),
|
||||
/* vGPIO_3 */
|
||||
PINCTRL_PIN(94, "TS0_IN_INT"),
|
||||
PINCTRL_PIN(95, "TS1_IN_INT"),
|
||||
/* GPP_D */
|
||||
PINCTRL_PIN(96, "TIME_SYNC_0"),
|
||||
PINCTRL_PIN(97, "TIME_SYNC_1"),
|
||||
PINCTRL_PIN(98, "DSI_DE_TE_2_GENLOCK_REF"),
|
||||
PINCTRL_PIN(99, "DSI_DE_TE_1_DISP_UTILS"),
|
||||
PINCTRL_PIN(100, "DSI_GENLOCK_2"),
|
||||
PINCTRL_PIN(101, "DSI_GENLOCK_3"),
|
||||
PINCTRL_PIN(102, "SRCCLKREQ2_B"),
|
||||
PINCTRL_PIN(103, "SRCCLKREQ3_B"),
|
||||
PINCTRL_PIN(104, "GPP_SD_8"),
|
||||
PINCTRL_PIN(105, "GPP_SD_9"),
|
||||
PINCTRL_PIN(106, "GPP_SD_10"),
|
||||
PINCTRL_PIN(107, "GPP_SD_11"),
|
||||
PINCTRL_PIN(108, "GPP_SD_12"),
|
||||
PINCTRL_PIN(109, "GPP_SD_13"),
|
||||
PINCTRL_PIN(110, "GPP_SD_14"),
|
||||
PINCTRL_PIN(111, "GPP_SD_15"),
|
||||
PINCTRL_PIN(112, "GPP_SD_16"),
|
||||
PINCTRL_PIN(113, "GPP_SD_17"),
|
||||
PINCTRL_PIN(114, "BOOTHALT_B"),
|
||||
PINCTRL_PIN(115, "GPP_SD_19"),
|
||||
PINCTRL_PIN(116, "GPP_SD_20"),
|
||||
PINCTRL_PIN(117, "AUDCLK"),
|
||||
PINCTRL_PIN(118, "AUDIN"),
|
||||
PINCTRL_PIN(119, "AUDOUT"),
|
||||
/* JTAG_CPU */
|
||||
PINCTRL_PIN(120, "PECI"),
|
||||
PINCTRL_PIN(121, "VIDSOUT"),
|
||||
PINCTRL_PIN(122, "VIDSCK"),
|
||||
PINCTRL_PIN(123, "VIDALERT_B"),
|
||||
PINCTRL_PIN(124, "JTAG_MBPB0"),
|
||||
PINCTRL_PIN(125, "JTAG_MBPB1"),
|
||||
PINCTRL_PIN(126, "JTAG_MBPB2"),
|
||||
PINCTRL_PIN(127, "JTAG_MBPB3"),
|
||||
PINCTRL_PIN(128, "JTAG_TDO"),
|
||||
PINCTRL_PIN(129, "PRDY_B"),
|
||||
PINCTRL_PIN(130, "PREQ_B"),
|
||||
PINCTRL_PIN(131, "JTAG_TDI"),
|
||||
PINCTRL_PIN(132, "JTAG_TMS"),
|
||||
PINCTRL_PIN(133, "JTAG_TCK"),
|
||||
PINCTRL_PIN(134, "DBG_PMODE"),
|
||||
PINCTRL_PIN(135, "JTAG_TRST_B"),
|
||||
/* vGPIO_4 */
|
||||
PINCTRL_PIN(136, "ISCLK_ESPI_XTAL_CLKREQ"),
|
||||
PINCTRL_PIN(137, "ESPI_ISCLK_XTAL_CLKACK"),
|
||||
PINCTRL_PIN(138, "vGPIO_SPARE4"),
|
||||
PINCTRL_PIN(139, "vGPIO_SPARE5"),
|
||||
PINCTRL_PIN(140, "vGPIO_SPARE6"),
|
||||
PINCTRL_PIN(141, "vGPIO_SPARE7"),
|
||||
PINCTRL_PIN(142, "vGPIO_SPARE16"),
|
||||
PINCTRL_PIN(143, "vGPIO_SPARE17"),
|
||||
PINCTRL_PIN(144, "vGPIO_SPARE18"),
|
||||
PINCTRL_PIN(145, "vGPIO_SPARE19"),
|
||||
PINCTRL_PIN(146, "vGPIO_SPARE20"),
|
||||
PINCTRL_PIN(147, "vGPIO_SPARE21"),
|
||||
};
|
||||
|
||||
static const struct intel_padgroup mtls_community0_gpps[] = {
|
||||
MTL_GPP(0, 0, 27, 0), /* GPP_A */
|
||||
MTL_GPP(1, 28, 46, 32), /* vGPIO_0 */
|
||||
MTL_GPP(2, 47, 73, 64), /* GPP_C */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup mtls_community1_gpps[] = {
|
||||
MTL_GPP(0, 74, 93, 96), /* GPP_B */
|
||||
MTL_GPP(1, 94, 95, 128), /* vGPIO_3 */
|
||||
MTL_GPP(2, 96, 119, 160), /* GPP_D */
|
||||
};
|
||||
|
||||
static const struct intel_padgroup mtls_community3_gpps[] = {
|
||||
MTL_GPP(0, 120, 135, 192), /* JTAG_CPU */
|
||||
MTL_GPP(1, 136, 147, 224), /* vGPIO_4 */
|
||||
};
|
||||
|
||||
static const struct intel_community mtls_communities[] = {
|
||||
MTL_S_COMMUNITY(0, 0, 73, mtls_community0_gpps),
|
||||
MTL_S_COMMUNITY(1, 74, 119, mtls_community1_gpps),
|
||||
MTL_S_COMMUNITY(2, 120, 147, mtls_community3_gpps),
|
||||
};
|
||||
|
||||
static const struct intel_pinctrl_soc_data mtls_soc_data = {
|
||||
.pins = mtls_pins,
|
||||
.npins = ARRAY_SIZE(mtls_pins),
|
||||
.communities = mtls_communities,
|
||||
.ncommunities = ARRAY_SIZE(mtls_communities),
|
||||
};
|
||||
|
||||
static const struct acpi_device_id mtl_pinctrl_acpi_match[] = {
|
||||
{ "INTC1083", (kernel_ulong_t)&mtlp_soc_data },
|
||||
{ "INTC1082", (kernel_ulong_t)&mtls_soc_data },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(acpi, mtl_pinctrl_acpi_match);
|
||||
|
|
|
@ -504,7 +504,7 @@ static void mofld_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
|
|||
}
|
||||
|
||||
mode = (value & BUFCFG_PINMODE_MASK) >> BUFCFG_PINMODE_SHIFT;
|
||||
if (!mode)
|
||||
if (mode == BUFCFG_PINMODE_GPIO)
|
||||
seq_puts(s, "GPIO ");
|
||||
else
|
||||
seq_printf(s, "mode %d ", mode);
|
||||
|
@ -661,6 +661,11 @@ static int mofld_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
|
|||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
if (value & BUFCFG_OD_EN)
|
||||
return -EINVAL;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
if (!(value & BUFCFG_OD_EN))
|
||||
return -EINVAL;
|
||||
|
@ -734,10 +739,14 @@ static int mofld_config_set_pin(struct mofld_pinctrl *mp, unsigned int pin,
|
|||
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
mask |= BUFCFG_OD_EN;
|
||||
bits &= ~BUFCFG_OD_EN;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
mask |= BUFCFG_OD_EN;
|
||||
if (arg)
|
||||
bits |= BUFCFG_OD_EN;
|
||||
bits |= BUFCFG_OD_EN;
|
||||
break;
|
||||
|
||||
case PIN_CONFIG_SLEW_RATE:
|
||||
|
@ -769,6 +778,7 @@ static int mofld_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
|
|||
case PIN_CONFIG_BIAS_DISABLE:
|
||||
case PIN_CONFIG_BIAS_PULL_UP:
|
||||
case PIN_CONFIG_BIAS_PULL_DOWN:
|
||||
case PIN_CONFIG_DRIVE_PUSH_PULL:
|
||||
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
|
||||
case PIN_CONFIG_SLEW_RATE:
|
||||
ret = mofld_config_set_pin(mp, pin, configs[i]);
|
||||
|
|
44
include/linux/string_choices.h
Normal file
44
include/linux/string_choices.h
Normal file
|
@ -0,0 +1,44 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
#ifndef _LINUX_STRING_CHOICES_H_
|
||||
#define _LINUX_STRING_CHOICES_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
static inline const char *str_enable_disable(bool v)
|
||||
{
|
||||
return v ? "enable" : "disable";
|
||||
}
|
||||
|
||||
static inline const char *str_enabled_disabled(bool v)
|
||||
{
|
||||
return v ? "enabled" : "disabled";
|
||||
}
|
||||
|
||||
static inline const char *str_hi_lo(bool v)
|
||||
{
|
||||
return v ? "hi" : "lo";
|
||||
}
|
||||
#define str_lo_hi(v) str_hi_lo(!(v))
|
||||
|
||||
static inline const char *str_high_low(bool v)
|
||||
{
|
||||
return v ? "high" : "low";
|
||||
}
|
||||
#define str_low_high(v) str_high_low(!(v))
|
||||
|
||||
static inline const char *str_read_write(bool v)
|
||||
{
|
||||
return v ? "read" : "write";
|
||||
}
|
||||
|
||||
static inline const char *str_on_off(bool v)
|
||||
{
|
||||
return v ? "on" : "off";
|
||||
}
|
||||
|
||||
static inline const char *str_yes_no(bool v)
|
||||
{
|
||||
return v ? "yes" : "no";
|
||||
}
|
||||
|
||||
#endif
|
|
@ -4,6 +4,7 @@
|
|||
|
||||
#include <linux/bits.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <linux/string_choices.h>
|
||||
#include <linux/string.h>
|
||||
#include <linux/types.h>
|
||||
|
||||
|
@ -113,29 +114,4 @@ void kfree_strarray(char **array, size_t n);
|
|||
|
||||
char **devm_kasprintf_strarray(struct device *dev, const char *prefix, size_t n);
|
||||
|
||||
static inline const char *str_yes_no(bool v)
|
||||
{
|
||||
return v ? "yes" : "no";
|
||||
}
|
||||
|
||||
static inline const char *str_on_off(bool v)
|
||||
{
|
||||
return v ? "on" : "off";
|
||||
}
|
||||
|
||||
static inline const char *str_enable_disable(bool v)
|
||||
{
|
||||
return v ? "enable" : "disable";
|
||||
}
|
||||
|
||||
static inline const char *str_enabled_disabled(bool v)
|
||||
{
|
||||
return v ? "enabled" : "disabled";
|
||||
}
|
||||
|
||||
static inline const char *str_read_write(bool v)
|
||||
{
|
||||
return v ? "read" : "write";
|
||||
}
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Reference in a new issue