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nfp: bpf: encode LMEM accesses
NFP LMEM is a large, indirectly accessed register file. There are two basic indirect access registers. Each access operation may either use offset (up to 8 or 16 words) or perform post decrement/increment. Add encodings of LMEM indexes as instruction operands. Signed-off-by: Jakub Kicinski <jakub.kicinski@netronome.com> Reviewed-by: Simon Horman <simon.horman@netronome.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2 changed files with 85 additions and 0 deletions
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@ -48,6 +48,7 @@ const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE] = {
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static u16 nfp_swreg_to_unreg(swreg reg, bool is_dst)
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{
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bool lm_id, lm_dec = false;
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u16 val = swreg_value(reg);
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switch (swreg_type(reg)) {
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@ -59,6 +60,33 @@ static u16 nfp_swreg_to_unreg(swreg reg, bool is_dst)
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return UR_REG_NN | val;
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case NN_REG_XFER:
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return UR_REG_XFR | val;
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case NN_REG_LMEM:
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lm_id = swreg_lm_idx(reg);
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switch (swreg_lm_mode(reg)) {
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case NN_LM_MOD_NONE:
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if (val & ~UR_REG_LM_IDX_MAX) {
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pr_err("LM offset too large\n");
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return 0;
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}
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return UR_REG_LM | FIELD_PREP(UR_REG_LM_IDX, lm_id) |
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val;
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case NN_LM_MOD_DEC:
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lm_dec = true;
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/* fall through */
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case NN_LM_MOD_INC:
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if (val) {
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pr_err("LM offset in inc/dev mode\n");
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return 0;
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}
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return UR_REG_LM | UR_REG_LM_POST_MOD |
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FIELD_PREP(UR_REG_LM_IDX, lm_id) |
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FIELD_PREP(UR_REG_LM_POST_MOD_DEC, lm_dec);
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default:
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pr_err("bad LM mode for unrestricted operands %d\n",
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swreg_lm_mode(reg));
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return 0;
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}
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case NN_REG_IMM:
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if (val & ~0xff) {
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pr_err("immediate too large\n");
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@ -108,6 +136,7 @@ int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg,
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static u16 nfp_swreg_to_rereg(swreg reg, bool is_dst, bool has_imm8, bool *i8)
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{
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u16 val = swreg_value(reg);
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bool lm_id;
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switch (swreg_type(reg)) {
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case NN_REG_GPR_A:
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@ -116,6 +145,21 @@ static u16 nfp_swreg_to_rereg(swreg reg, bool is_dst, bool has_imm8, bool *i8)
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return val;
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case NN_REG_XFER:
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return RE_REG_XFR | val;
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case NN_REG_LMEM:
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lm_id = swreg_lm_idx(reg);
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if (swreg_lm_mode(reg) != NN_LM_MOD_NONE) {
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pr_err("bad LM mode for restricted operands %d\n",
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swreg_lm_mode(reg));
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return 0;
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}
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if (val & ~RE_REG_LM_IDX_MAX) {
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pr_err("LM offset too large\n");
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return 0;
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}
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return RE_REG_LM | FIELD_PREP(RE_REG_LM_IDX, lm_id) | val;
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case NN_REG_IMM:
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if (val & ~(0x7f | has_imm8 << 7)) {
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pr_err("immediate too large\n");
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@ -44,9 +44,17 @@
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#define RE_REG_IMM_encode(x) \
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(RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1))
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#define RE_REG_IMM_MAX 0x07fULL
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#define RE_REG_LM 0x050
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#define RE_REG_LM_IDX 0x008
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#define RE_REG_LM_IDX_MAX 0x7
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#define RE_REG_XFR 0x080
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#define UR_REG_XFR 0x180
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#define UR_REG_LM 0x200
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#define UR_REG_LM_IDX 0x020
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#define UR_REG_LM_POST_MOD 0x010
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#define UR_REG_LM_POST_MOD_DEC 0x001
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#define UR_REG_LM_IDX_MAX 0xf
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#define UR_REG_NN 0x280
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#define UR_REG_NO_DST 0x300
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#define UR_REG_IMM UR_REG_NO_DST
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@ -235,6 +243,8 @@ enum lcsr_wr_src {
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/* Software register representation, independent of operand type */
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#define NN_REG_TYPE GENMASK(31, 24)
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#define NN_REG_LM_IDX BIT(22)
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#define NN_REG_LM_MOD GENMASK(21, 20)
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#define NN_REG_VAL GENMASK(7, 0)
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enum nfp_bpf_reg_type {
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@ -245,6 +255,13 @@ enum nfp_bpf_reg_type {
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NN_REG_XFER = BIT(3),
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NN_REG_IMM = BIT(4),
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NN_REG_NONE = BIT(5),
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NN_REG_LMEM = BIT(6),
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};
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enum nfp_bpf_lm_mode {
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NN_LM_MOD_NONE = 0,
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NN_LM_MOD_INC,
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NN_LM_MOD_DEC,
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};
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#define reg_both(x) __enc_swreg((x), NN_REG_GPR_BOTH)
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@ -254,6 +271,10 @@ enum nfp_bpf_reg_type {
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#define reg_xfer(x) __enc_swreg((x), NN_REG_XFER)
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#define reg_imm(x) __enc_swreg((x), NN_REG_IMM)
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#define reg_none() __enc_swreg(0, NN_REG_NONE)
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#define reg_lm(x, off) __enc_swreg_lm((x), NN_LM_MOD_NONE, (off))
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#define reg_lm_inc(x) __enc_swreg_lm((x), NN_LM_MOD_INC, 0)
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#define reg_lm_dec(x) __enc_swreg_lm((x), NN_LM_MOD_DEC, 0)
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#define __reg_lm(x, mod, off) __enc_swreg_lm((x), (mod), (off))
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typedef __u32 __bitwise swreg;
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@ -262,6 +283,16 @@ static inline swreg __enc_swreg(u16 id, u8 type)
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return (__force swreg)(id | FIELD_PREP(NN_REG_TYPE, type));
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}
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static inline swreg __enc_swreg_lm(u8 id, enum nfp_bpf_lm_mode mode, u8 off)
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{
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WARN_ON(id > 1 || (off && mode != NN_LM_MOD_NONE));
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return (__force swreg)(FIELD_PREP(NN_REG_TYPE, NN_REG_LMEM) |
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FIELD_PREP(NN_REG_LM_IDX, id) |
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FIELD_PREP(NN_REG_LM_MOD, mode) |
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off);
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}
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static inline u32 swreg_raw(swreg reg)
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{
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return (__force u32)reg;
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@ -277,6 +308,16 @@ static inline u16 swreg_value(swreg reg)
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return FIELD_GET(NN_REG_VAL, swreg_raw(reg));
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}
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static inline bool swreg_lm_idx(swreg reg)
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{
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return FIELD_GET(NN_REG_LM_IDX, swreg_raw(reg));
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}
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static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg)
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{
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return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg));
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}
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struct nfp_insn_ur_regs {
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enum alu_dst_ab dst_ab;
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u16 dst;
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