mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-12 21:57:43 +00:00
Merge branch 'pci/controller/rockchip'
- Remove writes to unused registers (Rick Wertenbroek) - Write endpoint Device ID using correct register (Rick Wertenbroek) - Assert PCI Configuration Enable bit after probe so endpoint responds instead of generating Request Retry Status messages (Rick Wertenbroek) - Poll waiting for PHY PLLs to lock (Rick Wertenbroek) - Update RK3399 example DT binding to be valid (Rick Wertenbroek) - Use RK3399 PCIE_CLIENT_LEGACY_INT_CTRL to generate INTx instead of manually generating PCIe message (Rick Wertenbroek) - Use multiple windows to avoid address translation conflicts (Rick Wertenbroek) - Use u32 (not u16) when accessing 32-bit registers (Rick Wertenbroek) - Hide MSI-X Capability, since RK3399 can't generate MSI-X (Rick Wertenbroek) - Set endpoint controller required alignment to 256 (Damien Le Moal) * pci/controller/rockchip: PCI: rockchip: Set address alignment for endpoint mode PCI: rockchip: Don't advertise MSI-X in PCIe capabilities PCI: rockchip: Use u32 variable to access 32-bit registers PCI: rockchip: Fix window mapping and address translation for endpoint PCI: rockchip: Fix legacy IRQ generation for RK3399 PCIe endpoint core dt-bindings: PCI: Update the RK3399 example to a valid one PCI: rockchip: Add poll and timeout to wait for PHY PLLs to be locked PCI: rockchip: Assert PCI Configuration Enable bit after probe PCI: rockchip: Write PCI Device ID to correct register PCI: rockchip: Remove writes to unused registers
This commit is contained in:
Bjorn Helgaas
commit
9f5eb1bf55
4 changed files with 154 additions and 137 deletions
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@ -47,7 +47,7 @@ examples:
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pcie-ep@f8000000 {
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compatible = "rockchip,rk3399-pcie-ep";
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reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
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reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0xfa000000 0x0 0x2000000>;
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reg-names = "apb-base", "mem-base";
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clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
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<&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
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@ -63,6 +63,8 @@ examples:
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phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
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phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
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rockchip,max-outbound-regions = <16>;
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pinctrl-names = "default";
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pinctrl-0 = <&pcie_clkreqnb_cpm>;
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};
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};
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...
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@ -61,70 +61,38 @@ static void rockchip_pcie_clear_ep_ob_atu(struct rockchip_pcie *rockchip,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC0(region));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC1(region));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(region));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(region));
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}
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static void rockchip_pcie_prog_ep_ob_atu(struct rockchip_pcie *rockchip, u8 fn,
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u32 r, u32 type, u64 cpu_addr,
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u64 pci_addr, size_t size)
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u32 r, u64 cpu_addr, u64 pci_addr,
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size_t size)
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{
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u64 sz = 1ULL << fls64(size - 1);
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int num_pass_bits = ilog2(sz);
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u32 addr0, addr1, desc0, desc1;
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bool is_nor_msg = (type == AXI_WRAPPER_NOR_MSG);
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int num_pass_bits = fls64(size - 1);
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u32 addr0, addr1, desc0;
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/* The minimal region size is 1MB */
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if (num_pass_bits < 8)
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num_pass_bits = 8;
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cpu_addr -= rockchip->mem_res->start;
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addr0 = ((is_nor_msg ? 0x10 : (num_pass_bits - 1)) &
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PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
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(lower_32_bits(cpu_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
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addr1 = upper_32_bits(is_nor_msg ? cpu_addr : pci_addr);
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desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | type;
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desc1 = 0;
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addr0 = ((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
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(lower_32_bits(pci_addr) & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
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addr1 = upper_32_bits(pci_addr);
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desc0 = ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(fn) | AXI_WRAPPER_MEM_WRITE;
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if (is_nor_msg) {
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
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rockchip_pcie_write(rockchip, desc0,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
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rockchip_pcie_write(rockchip, desc1,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
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} else {
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/* PCI bus address region */
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rockchip_pcie_write(rockchip, addr0,
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
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rockchip_pcie_write(rockchip, addr1,
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
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rockchip_pcie_write(rockchip, desc0,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
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rockchip_pcie_write(rockchip, desc1,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
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addr0 =
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((num_pass_bits - 1) & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS) |
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(lower_32_bits(cpu_addr) &
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PCIE_CORE_OB_REGION_ADDR0_LO_ADDR);
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addr1 = upper_32_bits(cpu_addr);
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}
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/* CPU bus address region */
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/* PCI bus address region */
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rockchip_pcie_write(rockchip, addr0,
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r));
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r));
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rockchip_pcie_write(rockchip, addr1,
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ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r));
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ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r));
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rockchip_pcie_write(rockchip, desc0,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r));
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rockchip_pcie_write(rockchip, 0,
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ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r));
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}
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static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
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struct pci_epf_header *hdr)
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{
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u32 reg;
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
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struct rockchip_pcie *rockchip = &ep->rockchip;
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@ -137,8 +105,9 @@ static int rockchip_pcie_ep_write_header(struct pci_epc *epc, u8 fn, u8 vfn,
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PCIE_CORE_CONFIG_VENDOR);
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}
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rockchip_pcie_write(rockchip, hdr->deviceid << 16,
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) + PCI_VENDOR_ID);
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reg = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_DID_VID);
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reg = (reg & 0xFFFF) | (hdr->deviceid << 16);
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rockchip_pcie_write(rockchip, reg, PCIE_EP_CONFIG_DID_VID);
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rockchip_pcie_write(rockchip,
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hdr->revid |
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@ -256,26 +225,20 @@ static void rockchip_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn, u8 vfn,
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ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar));
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}
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static inline u32 rockchip_ob_region(phys_addr_t addr)
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{
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return (addr >> ilog2(SZ_1M)) & 0x1f;
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}
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static int rockchip_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, u8 vfn,
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phys_addr_t addr, u64 pci_addr,
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size_t size)
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{
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
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struct rockchip_pcie *pcie = &ep->rockchip;
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u32 r;
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u32 r = rockchip_ob_region(addr);
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r = find_first_zero_bit(&ep->ob_region_map, BITS_PER_LONG);
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/*
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* Region 0 is reserved for configuration space and shouldn't
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* be used elsewhere per TRM, so leave it out.
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*/
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if (r >= ep->max_regions - 1) {
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dev_err(&epc->dev, "no free outbound region\n");
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return -EINVAL;
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}
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rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, AXI_WRAPPER_MEM_WRITE, addr,
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pci_addr, size);
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rockchip_pcie_prog_ep_ob_atu(pcie, fn, r, addr, pci_addr, size);
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set_bit(r, &ep->ob_region_map);
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ep->ob_addr[r] = addr;
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@ -290,15 +253,11 @@ static void rockchip_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn, u8 vfn,
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struct rockchip_pcie *rockchip = &ep->rockchip;
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u32 r;
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for (r = 0; r < ep->max_regions - 1; r++)
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for (r = 0; r < ep->max_regions; r++)
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if (ep->ob_addr[r] == addr)
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break;
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/*
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* Region 0 is reserved for configuration space and shouldn't
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* be used elsewhere per TRM, so leave it out.
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*/
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if (r == ep->max_regions - 1)
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if (r == ep->max_regions)
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return;
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rockchip_pcie_clear_ep_ob_atu(rockchip, r);
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@ -312,15 +271,15 @@ static int rockchip_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 vfn,
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{
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
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struct rockchip_pcie *rockchip = &ep->rockchip;
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u16 flags;
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u32 flags;
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flags = rockchip_pcie_read(rockchip,
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
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flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK;
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flags |=
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((multi_msg_cap << 1) << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
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PCI_MSI_FLAGS_64BIT;
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(multi_msg_cap << ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET) |
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(PCI_MSI_FLAGS_64BIT << ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET);
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flags &= ~ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP;
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rockchip_pcie_write(rockchip, flags,
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
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@ -332,7 +291,7 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
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{
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struct rockchip_pcie_ep *ep = epc_get_drvdata(epc);
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struct rockchip_pcie *rockchip = &ep->rockchip;
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u16 flags;
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u32 flags;
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flags = rockchip_pcie_read(rockchip,
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
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@ -345,48 +304,25 @@ static int rockchip_pcie_ep_get_msi(struct pci_epc *epc, u8 fn, u8 vfn)
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}
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static void rockchip_pcie_ep_assert_intx(struct rockchip_pcie_ep *ep, u8 fn,
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u8 intx, bool is_asserted)
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u8 intx, bool do_assert)
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{
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struct rockchip_pcie *rockchip = &ep->rockchip;
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u32 r = ep->max_regions - 1;
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u32 offset;
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u32 status;
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u8 msg_code;
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if (unlikely(ep->irq_pci_addr != ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR ||
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ep->irq_pci_fn != fn)) {
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rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
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AXI_WRAPPER_NOR_MSG,
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ep->irq_phys_addr, 0, 0);
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ep->irq_pci_addr = ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR;
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ep->irq_pci_fn = fn;
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}
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intx &= 3;
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if (is_asserted) {
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if (do_assert) {
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ep->irq_pending |= BIT(intx);
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msg_code = ROCKCHIP_PCIE_MSG_CODE_ASSERT_INTA + intx;
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rockchip_pcie_write(rockchip,
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PCIE_CLIENT_INT_IN_ASSERT |
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PCIE_CLIENT_INT_PEND_ST_PEND,
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PCIE_CLIENT_LEGACY_INT_CTRL);
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} else {
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ep->irq_pending &= ~BIT(intx);
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msg_code = ROCKCHIP_PCIE_MSG_CODE_DEASSERT_INTA + intx;
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rockchip_pcie_write(rockchip,
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PCIE_CLIENT_INT_IN_DEASSERT |
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PCIE_CLIENT_INT_PEND_ST_NORMAL,
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PCIE_CLIENT_LEGACY_INT_CTRL);
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}
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status = rockchip_pcie_read(rockchip,
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
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ROCKCHIP_PCIE_EP_CMD_STATUS);
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status &= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
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if ((status != 0) ^ (ep->irq_pending != 0)) {
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status ^= ROCKCHIP_PCIE_EP_CMD_STATUS_IS;
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rockchip_pcie_write(rockchip, status,
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
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ROCKCHIP_PCIE_EP_CMD_STATUS);
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}
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offset =
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ROCKCHIP_PCIE_MSG_ROUTING(ROCKCHIP_PCIE_MSG_ROUTING_LOCAL_INTX) |
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ROCKCHIP_PCIE_MSG_CODE(msg_code) | ROCKCHIP_PCIE_MSG_NO_DATA;
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writel(0, ep->irq_cpu_addr + offset);
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}
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static int rockchip_pcie_ep_send_legacy_irq(struct rockchip_pcie_ep *ep, u8 fn,
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@ -416,9 +352,10 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
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u8 interrupt_num)
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{
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struct rockchip_pcie *rockchip = &ep->rockchip;
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u16 flags, mme, data, data_mask;
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u32 flags, mme, data, data_mask;
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u8 msi_count;
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u64 pci_addr, pci_addr_mask = 0xff;
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u64 pci_addr;
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u32 r;
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/* Check MSI enable bit */
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flags = rockchip_pcie_read(&ep->rockchip,
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|
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@ -452,21 +389,20 @@ static int rockchip_pcie_ep_send_msi_irq(struct rockchip_pcie_ep *ep, u8 fn,
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ROCKCHIP_PCIE_EP_FUNC_BASE(fn) +
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ROCKCHIP_PCIE_EP_MSI_CTRL_REG +
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PCI_MSI_ADDRESS_LO);
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pci_addr &= GENMASK_ULL(63, 2);
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/* Set the outbound region if needed. */
|
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if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
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if (unlikely(ep->irq_pci_addr != (pci_addr & PCIE_ADDR_MASK) ||
|
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ep->irq_pci_fn != fn)) {
|
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rockchip_pcie_prog_ep_ob_atu(rockchip, fn, ep->max_regions - 1,
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AXI_WRAPPER_MEM_WRITE,
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r = rockchip_ob_region(ep->irq_phys_addr);
|
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rockchip_pcie_prog_ep_ob_atu(rockchip, fn, r,
|
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ep->irq_phys_addr,
|
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pci_addr & ~pci_addr_mask,
|
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pci_addr_mask + 1);
|
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ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
|
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pci_addr & PCIE_ADDR_MASK,
|
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~PCIE_ADDR_MASK + 1);
|
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ep->irq_pci_addr = (pci_addr & PCIE_ADDR_MASK);
|
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ep->irq_pci_fn = fn;
|
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}
|
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|
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writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
|
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writew(data, ep->irq_cpu_addr + (pci_addr & ~PCIE_ADDR_MASK));
|
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return 0;
|
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}
|
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|
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|
|
@ -506,6 +442,7 @@ static const struct pci_epc_features rockchip_pcie_epc_features = {
|
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.linkup_notifier = false,
|
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.msi_capable = true,
|
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.msix_capable = false,
|
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.align = 256,
|
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};
|
||||
|
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static const struct pci_epc_features*
|
||||
|
|
@ -547,6 +484,8 @@ static int rockchip_pcie_parse_ep_dt(struct rockchip_pcie *rockchip,
|
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if (err < 0 || ep->max_regions > MAX_REGION_LIMIT)
|
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ep->max_regions = MAX_REGION_LIMIT;
|
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|
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ep->ob_region_map = 0;
|
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|
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err = of_property_read_u8(dev->of_node, "max-functions",
|
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&ep->epc->max_functions);
|
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if (err < 0)
|
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|
|
@ -567,7 +506,9 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
|
|||
struct rockchip_pcie *rockchip;
|
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struct pci_epc *epc;
|
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size_t max_regions;
|
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int err;
|
||||
struct pci_epc_mem_window *windows = NULL;
|
||||
int err, i;
|
||||
u32 cfg_msi, cfg_msix_cp;
|
||||
|
||||
ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
|
||||
if (!ep)
|
||||
|
|
@ -614,15 +555,27 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
|
|||
/* Only enable function 0 by default */
|
||||
rockchip_pcie_write(rockchip, BIT(0), PCIE_CORE_PHY_FUNC_CFG);
|
||||
|
||||
err = pci_epc_mem_init(epc, rockchip->mem_res->start,
|
||||
resource_size(rockchip->mem_res), PAGE_SIZE);
|
||||
windows = devm_kcalloc(dev, ep->max_regions,
|
||||
sizeof(struct pci_epc_mem_window), GFP_KERNEL);
|
||||
if (!windows) {
|
||||
err = -ENOMEM;
|
||||
goto err_uninit_port;
|
||||
}
|
||||
for (i = 0; i < ep->max_regions; i++) {
|
||||
windows[i].phys_base = rockchip->mem_res->start + (SZ_1M * i);
|
||||
windows[i].size = SZ_1M;
|
||||
windows[i].page_size = SZ_1M;
|
||||
}
|
||||
err = pci_epc_multi_mem_init(epc, windows, ep->max_regions);
|
||||
devm_kfree(dev, windows);
|
||||
|
||||
if (err < 0) {
|
||||
dev_err(dev, "failed to initialize the memory space\n");
|
||||
goto err_uninit_port;
|
||||
}
|
||||
|
||||
ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
|
||||
SZ_128K);
|
||||
SZ_1M);
|
||||
if (!ep->irq_cpu_addr) {
|
||||
dev_err(dev, "failed to reserve memory space for MSI\n");
|
||||
err = -ENOMEM;
|
||||
|
|
@ -631,6 +584,32 @@ static int rockchip_pcie_ep_probe(struct platform_device *pdev)
|
|||
|
||||
ep->irq_pci_addr = ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR;
|
||||
|
||||
/*
|
||||
* MSI-X is not supported but the controller still advertises the MSI-X
|
||||
* capability by default, which can lead to the Root Complex side
|
||||
* allocating MSI-X vectors which cannot be used. Avoid this by skipping
|
||||
* the MSI-X capability entry in the PCIe capabilities linked-list: get
|
||||
* the next pointer from the MSI-X entry and set that in the MSI
|
||||
* capability entry (which is the previous entry). This way the MSI-X
|
||||
* entry is skipped (left out of the linked-list) and not advertised.
|
||||
*/
|
||||
cfg_msi = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +
|
||||
ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
|
||||
|
||||
cfg_msi &= ~ROCKCHIP_PCIE_EP_MSI_CP1_MASK;
|
||||
|
||||
cfg_msix_cp = rockchip_pcie_read(rockchip, PCIE_EP_CONFIG_BASE +
|
||||
ROCKCHIP_PCIE_EP_MSIX_CAP_REG) &
|
||||
ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK;
|
||||
|
||||
cfg_msi |= cfg_msix_cp;
|
||||
|
||||
rockchip_pcie_write(rockchip, cfg_msi,
|
||||
PCIE_EP_CONFIG_BASE + ROCKCHIP_PCIE_EP_MSI_CTRL_REG);
|
||||
|
||||
rockchip_pcie_write(rockchip, PCIE_CLIENT_CONF_ENABLE,
|
||||
PCIE_CLIENT_CONFIG);
|
||||
|
||||
return 0;
|
||||
err_epc_mem_exit:
|
||||
pci_epc_mem_exit(epc);
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/clk.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/gpio/consumer.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/of_pci.h>
|
||||
#include <linux/phy/phy.h>
|
||||
#include <linux/platform_device.h>
|
||||
|
|
@ -153,6 +154,12 @@ int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
|
|||
}
|
||||
EXPORT_SYMBOL_GPL(rockchip_pcie_parse_dt);
|
||||
|
||||
#define rockchip_pcie_read_addr(addr) rockchip_pcie_read(rockchip, addr)
|
||||
/* 100 ms max wait time for PHY PLLs to lock */
|
||||
#define RK_PHY_PLL_LOCK_TIMEOUT_US 100000
|
||||
/* Sleep should be less than 20ms */
|
||||
#define RK_PHY_PLL_LOCK_SLEEP_US 1000
|
||||
|
||||
int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
|
||||
{
|
||||
struct device *dev = rockchip->dev;
|
||||
|
|
@ -254,6 +261,16 @@ int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
|
|||
}
|
||||
}
|
||||
|
||||
err = readx_poll_timeout(rockchip_pcie_read_addr,
|
||||
PCIE_CLIENT_SIDE_BAND_STATUS,
|
||||
regs, !(regs & PCIE_CLIENT_PHY_ST),
|
||||
RK_PHY_PLL_LOCK_SLEEP_US,
|
||||
RK_PHY_PLL_LOCK_TIMEOUT_US);
|
||||
if (err) {
|
||||
dev_err(dev, "PHY PLLs could not lock, %d\n", err);
|
||||
goto err_power_off_phy;
|
||||
}
|
||||
|
||||
/*
|
||||
* Please don't reorder the deassert sequence of the following
|
||||
* four reset pins.
|
||||
|
|
|
|||
|
|
@ -38,6 +38,13 @@
|
|||
#define PCIE_CLIENT_MODE_EP HIWORD_UPDATE(0x0040, 0)
|
||||
#define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
|
||||
#define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
|
||||
#define PCIE_CLIENT_LEGACY_INT_CTRL (PCIE_CLIENT_BASE + 0x0c)
|
||||
#define PCIE_CLIENT_INT_IN_ASSERT HIWORD_UPDATE_BIT(0x0002)
|
||||
#define PCIE_CLIENT_INT_IN_DEASSERT HIWORD_UPDATE(0x0002, 0)
|
||||
#define PCIE_CLIENT_INT_PEND_ST_PEND HIWORD_UPDATE_BIT(0x0001)
|
||||
#define PCIE_CLIENT_INT_PEND_ST_NORMAL HIWORD_UPDATE(0x0001, 0)
|
||||
#define PCIE_CLIENT_SIDE_BAND_STATUS (PCIE_CLIENT_BASE + 0x20)
|
||||
#define PCIE_CLIENT_PHY_ST BIT(12)
|
||||
#define PCIE_CLIENT_DEBUG_OUT_0 (PCIE_CLIENT_BASE + 0x3c)
|
||||
#define PCIE_CLIENT_DEBUG_LTSSM_MASK GENMASK(5, 0)
|
||||
#define PCIE_CLIENT_DEBUG_LTSSM_L1 0x18
|
||||
|
|
@ -132,7 +139,10 @@
|
|||
|
||||
#define PCIE_RC_RP_ATS_BASE 0x400000
|
||||
#define PCIE_RC_CONFIG_NORMAL_BASE 0x800000
|
||||
#define PCIE_EP_PF_CONFIG_REGS_BASE 0x800000
|
||||
#define PCIE_RC_CONFIG_BASE 0xa00000
|
||||
#define PCIE_EP_CONFIG_BASE 0xa00000
|
||||
#define PCIE_EP_CONFIG_DID_VID (PCIE_EP_CONFIG_BASE + 0x00)
|
||||
#define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
|
||||
#define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
|
||||
#define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
|
||||
|
|
@ -148,10 +158,11 @@
|
|||
#define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
|
||||
#define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
|
||||
|
||||
#define PCIE_ADDR_MASK 0xffffff00
|
||||
#define PCIE_CORE_AXI_CONF_BASE 0xc00000
|
||||
#define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
|
||||
#define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
|
||||
#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
|
||||
#define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR PCIE_ADDR_MASK
|
||||
#define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
|
||||
#define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
|
||||
#define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
|
||||
|
|
@ -159,7 +170,7 @@
|
|||
#define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
|
||||
#define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
|
||||
#define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
|
||||
#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
|
||||
#define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR PCIE_ADDR_MASK
|
||||
#define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
|
||||
|
||||
/* Size of one AXI Region (not Region 0) */
|
||||
|
|
@ -216,21 +227,28 @@
|
|||
#define ROCKCHIP_PCIE_EP_CMD_STATUS 0x4
|
||||
#define ROCKCHIP_PCIE_EP_CMD_STATUS_IS BIT(19)
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_REG 0x90
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CP1_OFFSET 8
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CP1_MASK GENMASK(15, 8)
|
||||
#define ROCKCHIP_PCIE_EP_MSI_FLAGS_OFFSET 16
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_OFFSET 17
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MMC_MASK GENMASK(19, 17)
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_OFFSET 20
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MME_MASK GENMASK(22, 20)
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_ME BIT(16)
|
||||
#define ROCKCHIP_PCIE_EP_MSI_CTRL_MASK_MSI_CAP BIT(24)
|
||||
#define ROCKCHIP_PCIE_EP_MSIX_CAP_REG 0xb0
|
||||
#define ROCKCHIP_PCIE_EP_MSIX_CAP_CP_OFFSET 8
|
||||
#define ROCKCHIP_PCIE_EP_MSIX_CAP_CP_MASK GENMASK(15, 8)
|
||||
#define ROCKCHIP_PCIE_EP_DUMMY_IRQ_ADDR 0x1
|
||||
#define ROCKCHIP_PCIE_EP_PCI_LEGACY_IRQ_ADDR 0x3
|
||||
#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) (((fn) << 12) & GENMASK(19, 12))
|
||||
#define ROCKCHIP_PCIE_EP_FUNC_BASE(fn) \
|
||||
(PCIE_EP_PF_CONFIG_REGS_BASE + (((fn) << 12) & GENMASK(19, 12)))
|
||||
#define ROCKCHIP_PCIE_EP_VIRT_FUNC_BASE(fn) \
|
||||
(PCIE_EP_PF_CONFIG_REGS_BASE + 0x10000 + (((fn) << 12) & GENMASK(19, 12)))
|
||||
#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0840 + (fn) * 0x0040 + (bar) * 0x0008)
|
||||
(PCIE_CORE_AXI_CONF_BASE + 0x0828 + (fn) * 0x0040 + (bar) * 0x0008)
|
||||
#define ROCKCHIP_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0844 + (fn) * 0x0040 + (bar) * 0x0008)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0000 + ((r) & 0x1f) * 0x0020)
|
||||
(PCIE_CORE_AXI_CONF_BASE + 0x082c + (fn) * 0x0040 + (bar) * 0x0008)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN_MASK GENMASK(19, 12)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_DEVFN(devfn) \
|
||||
(((devfn) << 12) & \
|
||||
|
|
@ -238,20 +256,21 @@
|
|||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK GENMASK(27, 20)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS(bus) \
|
||||
(((bus) << 20) & ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0_BUS_MASK)
|
||||
#define PCIE_RC_EP_ATR_OB_REGIONS_1_32 (PCIE_CORE_AXI_CONF_BASE + 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR0(r) \
|
||||
(PCIE_RC_EP_ATR_OB_REGIONS_1_32 + 0x0000 + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_PCI_ADDR1(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0004 + ((r) & 0x1f) * 0x0020)
|
||||
(PCIE_RC_EP_ATR_OB_REGIONS_1_32 + 0x0004 + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_HARDCODED_RID BIT(23)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK GENMASK(31, 24)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN(devfn) \
|
||||
(((devfn) << 24) & ROCKCHIP_PCIE_AT_OB_REGION_DESC0_DEVFN_MASK)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC0(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0008 + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x000c + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR0(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x0018 + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_CPU_ADDR1(r) \
|
||||
(PCIE_RC_RP_ATS_BASE + 0x001c + ((r) & 0x1f) * 0x0020)
|
||||
(PCIE_RC_EP_ATR_OB_REGIONS_1_32 + 0x0008 + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC1(r) \
|
||||
(PCIE_RC_EP_ATR_OB_REGIONS_1_32 + 0x000c + ((r) & 0x1f) * 0x0020)
|
||||
#define ROCKCHIP_PCIE_AT_OB_REGION_DESC2(r) \
|
||||
(PCIE_RC_EP_ATR_OB_REGIONS_1_32 + 0x0010 + ((r) & 0x1f) * 0x0020)
|
||||
|
||||
#define ROCKCHIP_PCIE_CORE_EP_FUNC_BAR_CFG0(fn) \
|
||||
(PCIE_CORE_CTRL_MGMT_BASE + 0x0240 + (fn) * 0x0008)
|
||||
|
|
|
|||
Loading…
Reference in a new issue