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mmc: sdhci-omap: Add tuning support
MMC tuning procedure is required to support SD card UHS1-SDR104 mode and EMMC HS200 mode. SDR104/HS200 DLL Tuning Procedure for AM572x platform is mentioned in Figure 25-51. SDR104/HS200 DLL Tuning Procedure of AM572x Sitara Processors Silicon Revision 2.0, 1.1 TRM (SPRUHZ6I - October 2014–Revised April 2017 [1]). The tuning function sdhci_omap_execute_tuning() will only be called by the MMC/SD core if the corresponding speed modes are supported by the OMAP silicon which is set in the mmc host "caps" field. [1] -> http://www.ti.com/lit/ug/spruhz6i/spruhz6i.pdf Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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1 changed files with 130 additions and 0 deletions
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@ -37,6 +37,13 @@
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#define CON_INIT BIT(1)
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#define CON_INIT BIT(1)
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#define CON_OD BIT(0)
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#define CON_OD BIT(0)
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#define SDHCI_OMAP_DLL 0x0134
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#define DLL_SWT BIT(20)
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#define DLL_FORCE_SR_C_SHIFT 13
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#define DLL_FORCE_SR_C_MASK (0x7f << DLL_FORCE_SR_C_SHIFT)
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#define DLL_FORCE_VALUE BIT(12)
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#define DLL_CALIB BIT(1)
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#define SDHCI_OMAP_CMD 0x20c
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#define SDHCI_OMAP_CMD 0x20c
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#define SDHCI_OMAP_PSTATE 0x0224
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#define SDHCI_OMAP_PSTATE 0x0224
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@ -63,12 +70,16 @@
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#define SDHCI_OMAP_AC12 0x23c
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#define SDHCI_OMAP_AC12 0x23c
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#define AC12_V1V8_SIGEN BIT(19)
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#define AC12_V1V8_SIGEN BIT(19)
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#define AC12_SCLK_SEL BIT(23)
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#define SDHCI_OMAP_CAPA 0x240
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#define SDHCI_OMAP_CAPA 0x240
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#define CAPA_VS33 BIT(24)
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#define CAPA_VS33 BIT(24)
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#define CAPA_VS30 BIT(25)
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#define CAPA_VS30 BIT(25)
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#define CAPA_VS18 BIT(26)
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#define CAPA_VS18 BIT(26)
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#define SDHCI_OMAP_CAPA2 0x0244
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#define CAPA2_TSDR50 BIT(13)
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#define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
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#define SDHCI_OMAP_TIMEOUT 1 /* 1 msec */
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#define SYSCTL_CLKD_MAX 0x3FF
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#define SYSCTL_CLKD_MAX 0x3FF
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@ -77,6 +88,8 @@
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#define IOV_3V0 3000000 /* 300000 uV */
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#define IOV_3V0 3000000 /* 300000 uV */
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#define IOV_3V3 3300000 /* 330000 uV */
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#define IOV_3V3 3300000 /* 330000 uV */
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#define MAX_PHASE_DELAY 0x7C
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struct sdhci_omap_data {
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struct sdhci_omap_data {
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u32 offset;
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u32 offset;
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};
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};
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@ -198,6 +211,120 @@ static void sdhci_omap_conf_bus_power(struct sdhci_omap_host *omap_host,
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}
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}
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}
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}
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static inline void sdhci_omap_set_dll(struct sdhci_omap_host *omap_host,
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int count)
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{
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int i;
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u32 reg;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
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reg |= DLL_FORCE_VALUE;
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reg &= ~DLL_FORCE_SR_C_MASK;
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reg |= (count << DLL_FORCE_SR_C_SHIFT);
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sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
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reg |= DLL_CALIB;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
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for (i = 0; i < 1000; i++) {
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
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if (reg & DLL_CALIB)
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break;
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}
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reg &= ~DLL_CALIB;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
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}
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static void sdhci_omap_disable_tuning(struct sdhci_omap_host *omap_host)
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{
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u32 reg;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
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reg &= ~AC12_SCLK_SEL;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_AC12, reg);
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
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reg &= ~(DLL_FORCE_VALUE | DLL_SWT);
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sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
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}
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static int sdhci_omap_execute_tuning(struct mmc_host *mmc, u32 opcode)
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{
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struct sdhci_host *host = mmc_priv(mmc);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct sdhci_omap_host *omap_host = sdhci_pltfm_priv(pltfm_host);
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struct device *dev = omap_host->dev;
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struct mmc_ios *ios = &mmc->ios;
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u32 start_window = 0, max_window = 0;
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u8 cur_match, prev_match = 0;
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u32 length = 0, max_len = 0;
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u32 phase_delay = 0;
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int ret = 0;
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u32 reg;
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pltfm_host = sdhci_priv(host);
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omap_host = sdhci_pltfm_priv(pltfm_host);
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dev = omap_host->dev;
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/* clock tuning is not needed for upto 52MHz */
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if (ios->clock <= 52000000)
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return 0;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_CAPA2);
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if (ios->timing == MMC_TIMING_UHS_SDR50 && !(reg & CAPA2_TSDR50))
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return 0;
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_DLL);
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reg |= DLL_SWT;
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sdhci_omap_writel(omap_host, SDHCI_OMAP_DLL, reg);
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while (phase_delay <= MAX_PHASE_DELAY) {
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sdhci_omap_set_dll(omap_host, phase_delay);
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cur_match = !mmc_send_tuning(mmc, opcode, NULL);
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if (cur_match) {
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if (prev_match) {
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length++;
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} else {
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start_window = phase_delay;
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length = 1;
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}
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}
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if (length > max_len) {
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max_window = start_window;
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max_len = length;
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}
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prev_match = cur_match;
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phase_delay += 4;
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}
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if (!max_len) {
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dev_err(dev, "Unable to find match\n");
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ret = -EIO;
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goto tuning_error;
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}
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reg = sdhci_omap_readl(omap_host, SDHCI_OMAP_AC12);
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if (!(reg & AC12_SCLK_SEL)) {
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ret = -EIO;
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goto tuning_error;
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}
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phase_delay = max_window + 4 * (max_len >> 1);
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sdhci_omap_set_dll(omap_host, phase_delay);
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goto ret;
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tuning_error:
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dev_err(dev, "Tuning failed\n");
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sdhci_omap_disable_tuning(omap_host);
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ret:
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sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA);
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return ret;
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}
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static int sdhci_omap_card_busy(struct mmc_host *mmc)
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static int sdhci_omap_card_busy(struct mmc_host *mmc)
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{
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{
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u32 reg, ac12;
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u32 reg, ac12;
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@ -299,6 +426,8 @@ static int sdhci_omap_start_signal_voltage_switch(struct mmc_host *mmc,
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static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
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static void sdhci_omap_set_power_mode(struct sdhci_omap_host *omap_host,
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u8 power_mode)
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u8 power_mode)
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{
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{
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if (omap_host->bus_mode == MMC_POWER_OFF)
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sdhci_omap_disable_tuning(omap_host);
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omap_host->power_mode = power_mode;
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omap_host->power_mode = power_mode;
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}
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}
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@ -635,6 +764,7 @@ static int sdhci_omap_probe(struct platform_device *pdev)
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sdhci_omap_start_signal_voltage_switch;
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sdhci_omap_start_signal_voltage_switch;
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host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
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host->mmc_host_ops.set_ios = sdhci_omap_set_ios;
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host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
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host->mmc_host_ops.card_busy = sdhci_omap_card_busy;
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host->mmc_host_ops.execute_tuning = sdhci_omap_execute_tuning;
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sdhci_read_caps(host);
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sdhci_read_caps(host);
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host->caps |= SDHCI_CAN_DO_ADMA2;
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host->caps |= SDHCI_CAN_DO_ADMA2;
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