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arm: sunxi: use the right clock phandles for UARTs
All the UARTs are connected to clock gates; now that our clock driver is able to handle them, make the switch. Signed-off-by: Emilio López <emilio@elopez.com.ar> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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parent
07c60ef775
commit
9ff49ec75e
2 changed files with 8 additions and 8 deletions
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@ -54,7 +54,7 @@ uart0: serial@01c28000 {
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interrupts = <1>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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clocks = <&apb1_gates 16>;
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status = "disabled";
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};
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@ -64,7 +64,7 @@ uart2: serial@01c28800 {
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interrupts = <3>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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clocks = <&apb1_gates 18>;
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status = "disabled";
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};
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@ -74,7 +74,7 @@ uart4: serial@01c29000 {
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interrupts = <17>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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clocks = <&apb1_gates 20>;
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status = "disabled";
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};
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@ -84,7 +84,7 @@ uart5: serial@01c29400 {
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interrupts = <18>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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clocks = <&apb1_gates 21>;
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status = "disabled";
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};
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@ -94,7 +94,7 @@ uart6: serial@01c29800 {
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interrupts = <19>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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clocks = <&apb1_gates 22>;
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status = "disabled";
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};
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@ -104,7 +104,7 @@ uart7: serial@01c29c00 {
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interrupts = <20>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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clocks = <&apb1_gates 23>;
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status = "disabled";
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};
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};
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@ -191,7 +191,7 @@ uart1: serial@01c28400 {
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interrupts = <2>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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clocks = <&apb1_gates 17>;
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status = "disabled";
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};
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@ -201,7 +201,7 @@ uart3: serial@01c28c00 {
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interrupts = <4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&osc>;
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clocks = <&apb1_gates 19>;
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status = "disabled";
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};
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};
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