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[ARM] 3645/1: S3C2412: irq support for external interrupts
Patch from Ben Dooks Move the decoding of the IRQ_EXT4 and above out of the entry macro, and into an chained irq handler as the EXTINT registers move depending on the CPU being used. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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22346aea8d
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a019f4a9a7
3 changed files with 46 additions and 39 deletions
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@ -191,13 +191,9 @@ static struct irqchip s3c_irq_chip = {
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.ack = s3c_irq_ack,
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.mask = s3c_irq_mask,
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.unmask = s3c_irq_unmask,
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.set_wake = s3c_irq_wake
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.set_wake = s3c_irq_wake
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};
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/* S3C2410_EINTMASK
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* S3C2410_EINTPEND
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*/
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static void
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s3c_irqext_mask(unsigned int irqno)
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{
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@ -205,9 +201,9 @@ s3c_irqext_mask(unsigned int irqno)
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irqno -= EXTINT_OFF;
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mask = __raw_readl(S3C2410_EINTMASK);
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mask = __raw_readl(S3C24XX_EINTMASK);
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mask |= ( 1UL << irqno);
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__raw_writel(mask, S3C2410_EINTMASK);
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__raw_writel(mask, S3C24XX_EINTMASK);
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if (irqno <= (IRQ_EINT7 - EXTINT_OFF)) {
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/* check to see if all need masking */
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@ -232,11 +228,11 @@ s3c_irqext_ack(unsigned int irqno)
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bit = 1UL << (irqno - EXTINT_OFF);
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mask = __raw_readl(S3C2410_EINTMASK);
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mask = __raw_readl(S3C24XX_EINTMASK);
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__raw_writel(bit, S3C2410_EINTPEND);
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__raw_writel(bit, S3C24XX_EINTPEND);
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req = __raw_readl(S3C2410_EINTPEND);
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req = __raw_readl(S3C24XX_EINTPEND);
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req &= ~mask;
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/* not sure if we should be acking the parent irq... */
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@ -257,9 +253,9 @@ s3c_irqext_unmask(unsigned int irqno)
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irqno -= EXTINT_OFF;
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mask = __raw_readl(S3C2410_EINTMASK);
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mask = __raw_readl(S3C24XX_EINTMASK);
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mask &= ~( 1UL << irqno);
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__raw_writel(mask, S3C2410_EINTMASK);
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__raw_writel(mask, S3C24XX_EINTMASK);
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s3c_irq_unmask((irqno <= (IRQ_EINT7 - EXTINT_OFF)) ? IRQ_EINT4t7 : IRQ_EINT8t23);
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}
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@ -572,6 +568,23 @@ s3c_irq_demux_uart2(unsigned int irq,
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s3c_irq_demux_uart(IRQ_S3CUART_RX2, regs);
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}
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static void
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s3c_irq_demux_extint(unsigned int irq,
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struct irqdesc *desc,
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struct pt_regs *regs)
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{
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unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND);
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unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK);
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eintpnd &= ~eintmsk;
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if (eintpnd) {
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irq = fls(eintpnd);
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irq += (IRQ_EINT4 - (4 + 1));
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desc_handle_irq(irq, irq_desc + irq, regs);
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}
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}
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/* s3c24xx_init_irq
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*
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@ -591,12 +604,12 @@ void __init s3c24xx_init_irq(void)
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last = 0;
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for (i = 0; i < 4; i++) {
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pend = __raw_readl(S3C2410_EINTPEND);
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pend = __raw_readl(S3C24XX_EINTPEND);
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if (pend == 0 || pend == last)
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break;
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__raw_writel(pend, S3C2410_EINTPEND);
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__raw_writel(pend, S3C24XX_EINTPEND);
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printk("irq: clearing pending ext status %08x\n", (int)pend);
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last = pend;
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}
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@ -630,12 +643,14 @@ void __init s3c24xx_init_irq(void)
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irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n");
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for (irqno = IRQ_BATT_FLT; irqno <= IRQ_ADCPARENT; irqno++) {
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for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) {
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/* set all the s3c2410 internal irqs */
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switch (irqno) {
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/* deal with the special IRQs (cascaded) */
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case IRQ_EINT4t7:
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case IRQ_EINT8t23:
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case IRQ_UART0:
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case IRQ_UART1:
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case IRQ_UART2:
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@ -659,12 +674,14 @@ void __init s3c24xx_init_irq(void)
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/* setup the cascade irq handlers */
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set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint);
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set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint);
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set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0);
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set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1);
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set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2);
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set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc);
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/* external interrupts */
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for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
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@ -18,8 +18,6 @@
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#define INTPND (0x10)
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#define INTOFFSET (0x14)
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#define EXTINTPEND (0xa8)
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#define EXTINTMASK (0xa4)
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#include <asm/hardware.h>
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#include <asm/arch/irqs.h>
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@ -28,37 +26,23 @@
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mov \base, #S3C24XX_VA_IRQ
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ldr \irqstat, [ \base, #INTPND]
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bics \irqnr, \irqstat, #3<<4 @@ only an GPIO IRQ
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beq 2000f
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@@ try the interrupt offset register, since it is there
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ldr \irqstat, [ \base, #INTPND ]
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teq \irqstat, #0
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beq 1002f
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ldr \irqnr, [ \base, #INTOFFSET ]
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mov \tmp, #1
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tst \irqstat, \tmp, lsl \irqnr
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addne \irqnr, \irqnr, #IRQ_EINT0
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bne 1001f
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@@ the number specified is not a valid irq, so try
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@@ and work it out for ourselves
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mov \irqnr, #IRQ_EINT0 @@ start here
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b 3000f
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2000:
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@@ load the GPIO interrupt register, and check it
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add \tmp, \base, #S3C24XX_VA_GPIO - S3C24XX_VA_IRQ
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ldr \irqstat, [ \tmp, # EXTINTPEND ]
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ldr \irqnr, [ \tmp, # EXTINTMASK ]
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bics \irqstat, \irqstat, \irqnr
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beq 1001f
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mov \irqnr, #(IRQ_EINT4 - 4)
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mov \irqnr, #0 @@ start here
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@@ work out which irq (if any) we got
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3000:
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movs \tmp, \irqstat, lsl#16
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addeq \irqnr, \irqnr, #16
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moveq \irqstat, \irqstat, lsr#16
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@ -75,9 +59,9 @@
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addeq \irqnr, \irqnr, #1
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@@ we have the value
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movs \irqnr, \irqnr
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1001:
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adds \irqnr, \irqnr, #IRQ_EINT0
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1002:
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@@ exit here, Z flag unset if IRQ
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.endm
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@ -23,6 +23,7 @@
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#define S3C2410_IRQREG(x) ((x) + S3C24XX_VA_IRQ)
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#define S3C2410_EINTREG(x) ((x) + S3C24XX_VA_GPIO)
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#define S3C24XX_EINTREG(x) ((x) + S3C24XX_VA_GPIO2)
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#define S3C2410_SRCPND S3C2410_IRQREG(0x000)
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#define S3C2410_INTMOD S3C2410_IRQREG(0x004)
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@ -40,5 +41,10 @@
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#define S3C2410_EINTMASK S3C2410_EINTREG(0x0A4)
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#define S3C2410_EINTPEND S3C2410_EINTREG(0X0A8)
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#define S3C2412_EINTMASK S3C2410_EINTREG(0x0B4)
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#define S3C2412_EINTPEND S3C2410_EINTREG(0X0B8)
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#define S3C24XX_EINTMASK S3C24XX_EINTREG(0x0A4)
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#define S3C24XX_EINTPEND S3C24XX_EINTREG(0X0A8)
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#endif /* ___ASM_ARCH_REGS_IRQ_H */
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