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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 02:39:48 +00:00
serial: stm32: replace access to DMAR bit by dmaengine_pause/resume
It's rather advised to rely on DMA pause / resume instead of clearing/setting DMA request enable bit for the same purpose. Some DMA request/acknowledge race may encountered by doing so. We prefer to use dmaengine_pause and resume instead to pause a dma transfer when it is necessary. Create two new functions (stm32_usart_rx_dma_pause, stm32_usart_rx_dma _resume) to handle dma error when pausing/resuming. And rename stm32_usart_start_rx_dma_cyclic() to stm32_usart_rx_dma_start_or_resume() and use this function to resume an rx dma transfer. If resume fail, stm32_usart_rx_dma_start_or_resume can create a new transfer to continue. It is also safer to close DMA before reset DMAR in stm32_usart_shutdown. Signed-off-by: Valentin Caron <valentin.caron@foss.st.com> Link: https://lore.kernel.org/r/20230808161906.178996-6-valentin.caron@foss.st.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Valentin Caron
Greg Kroah-Hartman
parent
7f28bcea82
commit
a01ae50d7e
1 changed files with 106 additions and 94 deletions
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@ -326,6 +326,22 @@ static int stm32_usart_dma_pause_resume(struct stm32_port *stm32_port,
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return ret;
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}
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static int stm32_usart_rx_dma_pause(struct stm32_port *stm32_port)
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{
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return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
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DMA_IN_PROGRESS, dmaengine_pause,
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stm32_usart_rx_dma_started,
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stm32_usart_rx_dma_terminate);
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}
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static int stm32_usart_rx_dma_resume(struct stm32_port *stm32_port)
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{
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return stm32_usart_dma_pause_resume(stm32_port, stm32_port->rx_ch,
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DMA_PAUSED, dmaengine_resume,
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stm32_usart_rx_dma_started,
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stm32_usart_rx_dma_terminate);
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}
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/* Return true when data is pending (in pio mode), and false when no data is pending. */
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static bool stm32_usart_pending_rx_pio(struct uart_port *port, u32 *sr)
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{
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@ -485,7 +501,8 @@ static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force
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rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
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stm32_port->rx_ch->cookie,
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&stm32_port->rx_dma_state);
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if (rx_dma_status == DMA_IN_PROGRESS) {
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if (rx_dma_status == DMA_IN_PROGRESS ||
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rx_dma_status == DMA_PAUSED) {
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/* Empty DMA buffer */
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size = stm32_usart_receive_chars_dma(port);
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sr = readl_relaxed(port->membase + ofs->isr);
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@ -502,7 +519,6 @@ static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force
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} else {
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/* Disable RX DMA */
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stm32_usart_rx_dma_terminate(stm32_port);
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
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/* Fall back to interrupt mode */
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dev_dbg(port->dev, "DMA error, fallback to irq mode\n");
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size = stm32_usart_receive_chars_pio(port);
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@ -514,6 +530,76 @@ static unsigned int stm32_usart_receive_chars(struct uart_port *port, bool force
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return size;
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}
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static void stm32_usart_rx_dma_complete(void *arg)
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{
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struct uart_port *port = arg;
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struct tty_port *tport = &port->state->port;
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unsigned int size;
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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size = stm32_usart_receive_chars(port, false);
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uart_unlock_and_check_sysrq_irqrestore(port, flags);
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if (size)
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tty_flip_buffer_push(tport);
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}
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static int stm32_usart_rx_dma_start_or_resume(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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struct dma_async_tx_descriptor *desc;
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enum dma_status rx_dma_status;
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int ret;
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if (stm32_port->throttled)
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return 0;
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if (stm32_port->rx_dma_busy) {
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rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
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stm32_port->rx_ch->cookie,
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NULL);
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if (rx_dma_status == DMA_IN_PROGRESS)
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return 0;
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if (rx_dma_status == DMA_PAUSED && !stm32_usart_rx_dma_resume(stm32_port))
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return 0;
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dev_err(port->dev, "DMA failed : status error.\n");
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stm32_usart_rx_dma_terminate(stm32_port);
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}
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stm32_port->rx_dma_busy = true;
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stm32_port->last_res = RX_BUF_L;
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/* Prepare a DMA cyclic transaction */
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desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch,
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stm32_port->rx_dma_buf,
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RX_BUF_L, RX_BUF_P,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!desc) {
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dev_err(port->dev, "rx dma prep cyclic failed\n");
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stm32_port->rx_dma_busy = false;
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return -ENODEV;
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}
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desc->callback = stm32_usart_rx_dma_complete;
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desc->callback_param = port;
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/* Push current DMA transaction in the pending queue */
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ret = dma_submit_error(dmaengine_submit(desc));
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if (ret) {
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dmaengine_terminate_sync(stm32_port->rx_ch);
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stm32_port->rx_dma_busy = false;
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return ret;
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}
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/* Issue pending DMA requests */
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dma_async_issue_pending(stm32_port->rx_ch);
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return 0;
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}
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static void stm32_usart_tx_dma_terminate(struct stm32_port *stm32_port)
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{
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dmaengine_terminate_async(stm32_port->tx_ch);
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@ -585,20 +671,6 @@ static void stm32_usart_tc_interrupt_enable(struct uart_port *port)
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stm32_usart_set_bits(port, ofs->cr1, USART_CR1_TCIE);
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}
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static void stm32_usart_rx_dma_complete(void *arg)
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{
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struct uart_port *port = arg;
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struct tty_port *tport = &port->state->port;
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unsigned int size;
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unsigned long flags;
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spin_lock_irqsave(&port->lock, flags);
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size = stm32_usart_receive_chars(port, false);
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uart_unlock_and_check_sysrq_irqrestore(port, flags);
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if (size)
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tty_flip_buffer_push(tport);
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}
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static void stm32_usart_tx_interrupt_disable(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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@ -924,11 +996,10 @@ static void stm32_usart_throttle(struct uart_port *port)
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spin_lock_irqsave(&port->lock, flags);
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/*
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* Disable DMA request line if enabled, so the RX data gets queued into the FIFO.
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* Pause DMA transfer, so the RX data gets queued into the FIFO.
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* Hardware flow control is triggered when RX FIFO is full.
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*/
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if (stm32_usart_rx_dma_started(stm32_port))
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
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stm32_usart_rx_dma_pause(stm32_port);
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stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
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if (stm32_port->cr3_irq)
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@ -950,14 +1021,15 @@ static void stm32_usart_unthrottle(struct uart_port *port)
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if (stm32_port->cr3_irq)
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stm32_usart_set_bits(port, ofs->cr3, stm32_port->cr3_irq);
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stm32_port->throttled = false;
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/*
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* Switch back to DMA mode (re-enable DMA request line).
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* Switch back to DMA mode (resume DMA).
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* Hardware flow control is stopped when FIFO is not full any more.
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*/
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if (stm32_port->rx_ch)
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stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
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stm32_usart_rx_dma_start_or_resume(port);
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stm32_port->throttled = false;
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spin_unlock_irqrestore(&port->lock, flags);
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}
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@ -968,8 +1040,7 @@ static void stm32_usart_stop_rx(struct uart_port *port)
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const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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/* Disable DMA request line. */
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if (stm32_port->rx_ch)
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
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stm32_usart_rx_dma_pause(stm32_port);
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stm32_usart_clr_bits(port, ofs->cr1, stm32_port->cr1_irq);
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if (stm32_port->cr3_irq)
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@ -981,64 +1052,6 @@ static void stm32_usart_break_ctl(struct uart_port *port, int break_state)
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{
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}
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static int stm32_usart_start_rx_dma_cyclic(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct dma_async_tx_descriptor *desc;
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enum dma_status rx_dma_status;
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int ret;
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if (stm32_port->rx_dma_busy) {
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rx_dma_status = dmaengine_tx_status(stm32_port->rx_ch,
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stm32_port->rx_ch->cookie,
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NULL);
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if (rx_dma_status == DMA_IN_PROGRESS)
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return 0;
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dev_err(port->dev, "DMA failed : status error.\n");
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stm32_usart_rx_dma_terminate(stm32_port);
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}
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stm32_port->rx_dma_busy = true;
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stm32_port->last_res = RX_BUF_L;
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/* Prepare a DMA cyclic transaction */
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desc = dmaengine_prep_dma_cyclic(stm32_port->rx_ch,
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stm32_port->rx_dma_buf,
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RX_BUF_L, RX_BUF_P,
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DMA_DEV_TO_MEM,
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DMA_PREP_INTERRUPT);
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if (!desc) {
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dev_err(port->dev, "rx dma prep cyclic failed\n");
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stm32_port->rx_dma_busy = false;
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return -ENODEV;
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}
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desc->callback = stm32_usart_rx_dma_complete;
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desc->callback_param = port;
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/* Push current DMA transaction in the pending queue */
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ret = dma_submit_error(dmaengine_submit(desc));
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if (ret) {
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dmaengine_terminate_sync(stm32_port->rx_ch);
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stm32_port->rx_dma_busy = false;
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return ret;
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}
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/* Issue pending DMA requests */
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dma_async_issue_pending(stm32_port->rx_ch);
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/*
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* DMA request line not re-enabled at resume when port is throttled.
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* It will be re-enabled by unthrottle ops.
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*/
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if (!stm32_port->throttled)
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stm32_usart_set_bits(port, ofs->cr3, USART_CR3_DMAR);
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return 0;
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}
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static int stm32_usart_startup(struct uart_port *port)
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{
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struct stm32_port *stm32_port = to_stm32_port(port);
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@ -1064,7 +1077,7 @@ static int stm32_usart_startup(struct uart_port *port)
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writel_relaxed(USART_RQR_RXFRQ, port->membase + ofs->rqr);
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if (stm32_port->rx_ch) {
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ret = stm32_usart_start_rx_dma_cyclic(port);
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ret = stm32_usart_rx_dma_start_or_resume(port);
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if (ret) {
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free_irq(port->irq, port);
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return ret;
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@ -1811,11 +1824,6 @@ static int stm32_usart_serial_remove(struct platform_device *pdev)
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pm_runtime_put_noidle(&pdev->dev);
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stm32_usart_clr_bits(port, ofs->cr1, USART_CR1_PEIE);
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cr3 = readl_relaxed(port->membase + ofs->cr3);
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cr3 &= ~USART_CR3_EIE;
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cr3 &= ~USART_CR3_DMAR;
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cr3 &= ~USART_CR3_DDRE;
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writel_relaxed(cr3, port->membase + ofs->cr3);
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if (stm32_port->tx_ch) {
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stm32_usart_of_dma_tx_remove(stm32_port, pdev);
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@ -1827,7 +1835,12 @@ static int stm32_usart_serial_remove(struct platform_device *pdev)
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dma_release_channel(stm32_port->rx_ch);
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}
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAT);
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cr3 = readl_relaxed(port->membase + ofs->cr3);
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cr3 &= ~USART_CR3_EIE;
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cr3 &= ~USART_CR3_DMAR;
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cr3 &= ~USART_CR3_DMAT;
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cr3 &= ~USART_CR3_DDRE;
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writel_relaxed(cr3, port->membase + ofs->cr3);
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if (stm32_port->wakeup_src) {
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dev_pm_clear_wake_irq(&pdev->dev);
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@ -1999,7 +2012,7 @@ static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
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const struct stm32_usart_offsets *ofs = &stm32_port->info->ofs;
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struct tty_port *tport = &port->state->port;
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int ret;
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unsigned int size;
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unsigned int size = 0;
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unsigned long flags;
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if (!stm32_port->wakeup_src || !tty_port_initialized(tport))
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@ -2021,10 +2034,9 @@ static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
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*/
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if (stm32_port->rx_ch) {
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spin_lock_irqsave(&port->lock, flags);
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/* Avoid race with RX IRQ when DMAR is cleared */
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stm32_usart_clr_bits(port, ofs->cr3, USART_CR3_DMAR);
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/* Poll data from DMA RX buffer if any */
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size = stm32_usart_receive_chars(port, true);
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if (!stm32_usart_rx_dma_pause(stm32_port))
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size += stm32_usart_receive_chars(port, true);
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stm32_usart_rx_dma_terminate(stm32_port);
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uart_unlock_and_check_sysrq_irqrestore(port, flags);
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if (size)
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@ -2035,7 +2047,7 @@ static int __maybe_unused stm32_usart_serial_en_wakeup(struct uart_port *port,
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stm32_usart_receive_chars(port, false);
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} else {
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if (stm32_port->rx_ch) {
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ret = stm32_usart_start_rx_dma_cyclic(port);
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ret = stm32_usart_rx_dma_start_or_resume(port);
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if (ret)
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return ret;
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}
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