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Revert "Merge branch 'qcom-dts-updates'"

Browse source 
This reverts commit b79c6fba6c, reversing
these changes made to 0ac2627134:

  commit 6a0eb6c9d9 ("dt-bindings: net: qcom,ipa: make imem interconnect
                       optional")
  commit f8bd3c82bf ("arm64: dts: qcom: sc7280: add IPA information")
  commit fd0f72c34b ("arm64: dts: qcom: sc7180: define ipa_fw_mem node")

I intend for these commits to go through the Qualcomm repository, to
avoid conflicting with other activity being merged there.

Signed-off-by: Alex Elder <elder@linaro.org>
Link: https://lore.kernel.org/r/20210802233019.800250-1-elder@linaro.org
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Alex Elder 2021-08-02 18:30:19 -05:00 committed by Jakub Kicinski
parent 8578880df3
commit a0221a0f9b
3 changed files with 8 additions and 58 deletions
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18
Documentation/devicetree/bindings/net/qcom,ipa.yaml
View file

@ -87,18 +87,16 @@ properties:
- const: ipa-setup-ready
interconnects:
minItems: 2
items:
- description: Path leading to system memory
- description: Path between the AP and IPA config space
- description: Path leading to internal memory
- description: Interconnect path between IPA and main memory
- description: Interconnect path between IPA and internal memory
- description: Interconnect path between IPA and the AP subsystem
interconnect-names:
minItems: 2
items:
- const: memory
- const: config
- const: imem
- const: config
qcom,smem-states:
$ref: /schemas/types.yaml#/definitions/phandle-array
@ -209,11 +207,11 @@ examples:
interconnects =
<&rsc_hlos MASTER_IPA &rsc_hlos SLAVE_EBI1>,
<&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_IPA_CFG>,
<&rsc_hlos MASTER_IPA &rsc_hlos SLAVE_IMEM>;
<&rsc_hlos MASTER_IPA &rsc_hlos SLAVE_IMEM>,
<&rsc_hlos MASTER_APPSS_PROC &rsc_hlos SLAVE_IPA_CFG>;
interconnect-names = "memory",
"config",
"imem";
"imem",
"config";
qcom,smem-states = <&ipa_smp2p_out 0>,
<&ipa_smp2p_out 1>;

5
arch/arm64/boot/dts/qcom/sc7180.dtsi
View file

@ -110,11 +110,6 @@ tz_mem: memory@80b00000 {
no-map;
};
ipa_fw_mem: memory@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
rmtfs_mem: memory@94600000 {
compatible = "qcom,rmtfs-mem";
reg = <0x0 0x94600000 0x0 0x200000>;

43
arch/arm64/boot/dts/qcom/sc7280.dtsi
View file

@ -7,7 +7,6 @@
#include <dt-bindings/clock/qcom,gcc-sc7280.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/interconnect/qcom,sc7280.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
@ -64,11 +63,6 @@ cpucp_mem: memory@80b00000 {
no-map;
reg = <0x0 0x80b00000 0x0 0x100000>;
};
ipa_fw_mem: memory@8b700000 {
reg = <0 0x8b700000 0 0x10000>;
no-map;
};
};
cpus {
@ -514,43 +508,6 @@ mmss_noc: interconnect@1740000 {
qcom,bcm-voters = <&apps_bcm_voter>;
};
ipa: ipa@1e40000 {
compatible = "qcom,sc7280-ipa";
iommus = <&apps_smmu 0x480 0x0>,
<&apps_smmu 0x482 0x0>;
reg = <0 0x1e40000 0 0x8000>,
<0 0x1e50000 0 0x4ad0>,
<0 0x1e04000 0 0x23000>;
reg-names = "ipa-reg",
"ipa-shared",
"gsi";
interrupts-extended = <&intc 0 654 IRQ_TYPE_EDGE_RISING>,
<&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
<&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "ipa",
"gsi",
"ipa-clock-query",
"ipa-setup-ready";
clocks = <&rpmhcc RPMH_IPA_CLK>;
clock-names = "core";
interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>;
interconnect-names = "memory",
"config";
qcom,smem-states = <&ipa_smp2p_out 0>,
<&ipa_smp2p_out 1>;
qcom,smem-state-names = "ipa-clock-enabled-valid",
"ipa-clock-enabled";
status = "disabled";
};
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex", "syscon";
reg = <0 0x01f40000 0 0x40000>;