Merge branches 'pci/host-aardvark', 'pci/host-altera', 'pci/host-dra7xx', 'pci/host-hv', 'pci/host-vmd' and 'pci/host-xilinx' into next
* pci/host-aardvark: arm64: dts: marvell: Add Aardvark PCIe support for Armada 3700 PCI: aardvark: Add Aardvark PCI host controller driver dt-bindings: add DT binding for the Aardvark PCIe controller * pci/host-altera: PCI: altera: Poll for link up status after retraining the link PCI: altera: Check link status before retrain link PCI: altera: Reorder read/write functions * pci/host-dra7xx: PCI: dra7xx: Fix return value in case of error * pci/host-hv: PCI: hv: Fix interrupt cleanup path PCI: hv: Handle all pending messages in hv_pci_onchannelcallback() PCI: hv: Don't leak buffer in hv_pci_onchannelcallback() * pci/host-vmd: x86/PCI: VMD: Separate MSI and MSI-X vector sharing x86/PCI: VMD: Use x86_vector_domain as parent domain x86/PCI: VMD: Use lock save/restore in interrupt enable path x86/PCI: VMD: Initialize list item in IRQ disable x86/PCI: VMD: Select device dma ops to override * pci/host-xilinx: PCI: xilinx: Fix return value in case of error Manually apply changes from pci/demodularize-hosts and pci/host-request-windows to drivers/pci/host/pci-aardvark.c
This commit is contained in:
Bjorn Helgaas
commit
a04bee8285
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@ -0,0 +1,56 @@
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Aardvark PCIe controller
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This PCIe controller is used on the Marvell Armada 3700 ARM64 SoC.
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The Device Tree node describing an Aardvark PCIe controller must
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contain the following properties:
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- compatible: Should be "marvell,armada-3700-pcie"
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- reg: range of registers for the PCIe controller
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- interrupts: the interrupt line of the PCIe controller
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- #address-cells: set to <3>
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- #size-cells: set to <2>
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- device_type: set to "pci"
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- ranges: ranges for the PCI memory and I/O regions
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- #interrupt-cells: set to <1>
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- msi-controller: indicates that the PCIe controller can itself
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handle MSI interrupts
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- msi-parent: pointer to the MSI controller to be used
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- interrupt-map-mask and interrupt-map: standard PCI properties to
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define the mapping of the PCIe interface to interrupt numbers.
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- bus-range: PCI bus numbers covered
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In addition, the Device Tree describing an Aardvark PCIe controller
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must include a sub-node that describes the legacy interrupt controller
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built into the PCIe controller. This sub-node must have the following
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properties:
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- interrupt-controller
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- #interrupt-cells: set to <1>
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Example:
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pcie0: pcie@d0070000 {
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compatible = "marvell,armada-3700-pcie";
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device_type = "pci";
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status = "disabled";
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reg = <0 0xd0070000 0 0x20000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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msi-controller;
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msi-parent = <&pcie0>;
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ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
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0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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@ -8742,6 +8742,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: drivers/pci/host/*mvebu*
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PCI DRIVER FOR AARDVARK (Marvell Armada 3700)
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M: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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L: linux-pci@vger.kernel.org
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L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
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S: Maintained
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F: drivers/pci/host/pci-aardvark.c
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PCI DRIVER FOR NVIDIA TEGRA
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M: Thierry Reding <thierry.reding@gmail.com>
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L: linux-tegra@vger.kernel.org
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@ -76,3 +76,8 @@
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&usb3 {
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status = "okay";
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};
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/* CON17 (PCIe) / CON12 (mini-PCIe) */
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&pcie0 {
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status = "okay";
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};
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@ -141,5 +141,30 @@
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<0x1d40000 0x40000>; /* GICR */
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};
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};
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pcie0: pcie@d0070000 {
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compatible = "marvell,armada-3700-pcie";
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device_type = "pci";
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status = "disabled";
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reg = <0 0xd0070000 0 0x20000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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msi-parent = <&pcie0>;
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msi-controller;
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ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */
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0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &pcie_intc 0>,
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<0 0 0 2 &pcie_intc 1>,
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<0 0 0 3 &pcie_intc 2>,
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<0 0 0 4 &pcie_intc 3>;
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pcie_intc: interrupt-controller {
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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};
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};
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};
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@ -119,10 +119,11 @@ static void vmd_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
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static void vmd_irq_enable(struct irq_data *data)
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{
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struct vmd_irq *vmdirq = data->chip_data;
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unsigned long flags;
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raw_spin_lock(&list_lock);
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raw_spin_lock_irqsave(&list_lock, flags);
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list_add_tail_rcu(&vmdirq->node, &vmdirq->irq->irq_list);
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raw_spin_unlock(&list_lock);
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raw_spin_unlock_irqrestore(&list_lock, flags);
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data->chip->irq_unmask(data);
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}
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@ -130,12 +131,14 @@ static void vmd_irq_enable(struct irq_data *data)
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static void vmd_irq_disable(struct irq_data *data)
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{
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struct vmd_irq *vmdirq = data->chip_data;
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unsigned long flags;
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data->chip->irq_mask(data);
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raw_spin_lock(&list_lock);
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raw_spin_lock_irqsave(&list_lock, flags);
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list_del_rcu(&vmdirq->node);
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raw_spin_unlock(&list_lock);
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INIT_LIST_HEAD_RCU(&vmdirq->node);
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raw_spin_unlock_irqrestore(&list_lock, flags);
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}
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/*
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@ -166,16 +169,20 @@ static irq_hw_number_t vmd_get_hwirq(struct msi_domain_info *info,
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* XXX: We can be even smarter selecting the best IRQ once we solve the
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* affinity problem.
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*/
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static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd)
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static struct vmd_irq_list *vmd_next_irq(struct vmd_dev *vmd, struct msi_desc *desc)
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{
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int i, best = 0;
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int i, best = 1;
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unsigned long flags;
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raw_spin_lock(&list_lock);
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if (!desc->msi_attrib.is_msix || vmd->msix_count == 1)
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return &vmd->irqs[0];
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raw_spin_lock_irqsave(&list_lock, flags);
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for (i = 1; i < vmd->msix_count; i++)
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if (vmd->irqs[i].count < vmd->irqs[best].count)
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best = i;
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vmd->irqs[best].count++;
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raw_spin_unlock(&list_lock);
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raw_spin_unlock_irqrestore(&list_lock, flags);
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return &vmd->irqs[best];
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}
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@ -184,14 +191,15 @@ static int vmd_msi_init(struct irq_domain *domain, struct msi_domain_info *info,
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unsigned int virq, irq_hw_number_t hwirq,
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msi_alloc_info_t *arg)
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{
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struct vmd_dev *vmd = vmd_from_bus(msi_desc_to_pci_dev(arg->desc)->bus);
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struct msi_desc *desc = arg->desc;
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struct vmd_dev *vmd = vmd_from_bus(msi_desc_to_pci_dev(desc)->bus);
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struct vmd_irq *vmdirq = kzalloc(sizeof(*vmdirq), GFP_KERNEL);
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if (!vmdirq)
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return -ENOMEM;
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INIT_LIST_HEAD(&vmdirq->node);
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vmdirq->irq = vmd_next_irq(vmd);
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vmdirq->irq = vmd_next_irq(vmd, desc);
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vmdirq->virq = virq;
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irq_domain_set_info(domain, virq, vmdirq->irq->vmd_vector, info->chip,
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@ -203,11 +211,12 @@ static void vmd_msi_free(struct irq_domain *domain,
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struct msi_domain_info *info, unsigned int virq)
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{
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struct vmd_irq *vmdirq = irq_get_chip_data(virq);
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unsigned long flags;
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/* XXX: Potential optimization to rebalance */
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raw_spin_lock(&list_lock);
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raw_spin_lock_irqsave(&list_lock, flags);
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vmdirq->irq->count--;
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raw_spin_unlock(&list_lock);
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raw_spin_unlock_irqrestore(&list_lock, flags);
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kfree_rcu(vmdirq, rcu);
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}
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@ -261,7 +270,7 @@ static struct device *to_vmd_dev(struct device *dev)
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static struct dma_map_ops *vmd_dma_ops(struct device *dev)
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{
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return to_vmd_dev(dev)->archdata.dma_ops;
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return get_dma_ops(to_vmd_dev(dev));
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}
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static void *vmd_alloc(struct device *dev, size_t size, dma_addr_t *addr,
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@ -367,7 +376,7 @@ static void vmd_teardown_dma_ops(struct vmd_dev *vmd)
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{
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struct dma_domain *domain = &vmd->dma_domain;
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if (vmd->dev->dev.archdata.dma_ops)
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if (get_dma_ops(&vmd->dev->dev))
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del_dma_domain(domain);
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}
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@ -379,7 +388,7 @@ static void vmd_teardown_dma_ops(struct vmd_dev *vmd)
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static void vmd_setup_dma_ops(struct vmd_dev *vmd)
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{
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const struct dma_map_ops *source = vmd->dev->dev.archdata.dma_ops;
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const struct dma_map_ops *source = get_dma_ops(&vmd->dev->dev);
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struct dma_map_ops *dest = &vmd->dma_ops;
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struct dma_domain *domain = &vmd->dma_domain;
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@ -594,7 +603,7 @@ static int vmd_enable_domain(struct vmd_dev *vmd)
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sd->node = pcibus_to_node(vmd->dev->bus);
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vmd->irq_domain = pci_msi_create_irq_domain(NULL, &vmd_msi_domain_info,
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NULL);
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x86_vector_domain);
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if (!vmd->irq_domain)
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return -ENODEV;
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|
|
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|
|
@ -17,6 +17,15 @@ config PCI_MVEBU
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depends on ARM
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depends on OF
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config PCI_AARDVARK
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bool "Aardvark PCIe controller"
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depends on ARCH_MVEBU && ARM64
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depends on OF
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depends on PCI_MSI_IRQ_DOMAIN
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help
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Add support for Aardvark 64bit PCIe Host Controller. This
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controller is part of the South Bridge of the Marvel Armada
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3700 SoC.
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config PCIE_XILINX_NWL
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bool "NWL PCIe Core"
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|
|
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|||
|
|
@ -5,6 +5,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
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obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o
|
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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
|
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obj-$(CONFIG_PCI_AARDVARK) += pci-aardvark.o
|
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obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
|
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obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
|
||||
obj-$(CONFIG_PCIE_RCAR) += pcie-rcar.o
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -181,14 +181,14 @@ static int dra7xx_pcie_init_irq_domain(struct pcie_port *pp)
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|||
|
||||
if (!pcie_intc_node) {
|
||||
dev_err(dev, "No PCIe Intc node found\n");
|
||||
return PTR_ERR(pcie_intc_node);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
pp->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
|
||||
&intx_domain_ops, pp);
|
||||
if (!pp->irq_domain) {
|
||||
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
||||
return PTR_ERR(pp->irq_domain);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -732,16 +732,18 @@ static void hv_msi_free(struct irq_domain *domain, struct msi_domain_info *info,
|
|||
|
||||
pdev = msi_desc_to_pci_dev(msi);
|
||||
hbus = info->data;
|
||||
hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
|
||||
if (!hpdev)
|
||||
int_desc = irq_data_get_irq_chip_data(irq_data);
|
||||
if (!int_desc)
|
||||
return;
|
||||
|
||||
int_desc = irq_data_get_irq_chip_data(irq_data);
|
||||
if (int_desc) {
|
||||
irq_data->chip_data = NULL;
|
||||
hv_int_desc_free(hpdev, int_desc);
|
||||
irq_data->chip_data = NULL;
|
||||
hpdev = get_pcichild_wslot(hbus, devfn_to_wslot(pdev->devfn));
|
||||
if (!hpdev) {
|
||||
kfree(int_desc);
|
||||
return;
|
||||
}
|
||||
|
||||
hv_int_desc_free(hpdev, int_desc);
|
||||
put_pcichild(hpdev, hv_pcidev_ref_by_slot);
|
||||
}
|
||||
|
||||
|
|
@ -1657,14 +1659,16 @@ static void hv_pci_onchannelcallback(void *context)
|
|||
continue;
|
||||
}
|
||||
|
||||
/* Zero length indicates there are no more packets. */
|
||||
if (ret || !bytes_recvd)
|
||||
break;
|
||||
|
||||
/*
|
||||
* All incoming packets must be at least as large as a
|
||||
* response.
|
||||
*/
|
||||
if (bytes_recvd <= sizeof(struct pci_response)) {
|
||||
kfree(buffer);
|
||||
return;
|
||||
}
|
||||
if (bytes_recvd <= sizeof(struct pci_response))
|
||||
continue;
|
||||
desc = (struct vmpacket_descriptor *)buffer;
|
||||
|
||||
switch (desc->type) {
|
||||
|
|
@ -1679,8 +1683,7 @@ static void hv_pci_onchannelcallback(void *context)
|
|||
comp_packet->completion_func(comp_packet->compl_ctxt,
|
||||
response,
|
||||
bytes_recvd);
|
||||
kfree(buffer);
|
||||
return;
|
||||
break;
|
||||
|
||||
case VM_PKT_DATA_INBAND:
|
||||
|
||||
|
|
@ -1727,8 +1730,9 @@ static void hv_pci_onchannelcallback(void *context)
|
|||
desc->type, req_id, bytes_recvd);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
kfree(buffer);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
|
|
@ -61,6 +61,8 @@
|
|||
#define TLP_LOOP 500
|
||||
#define RP_DEVFN 0
|
||||
|
||||
#define LINK_UP_TIMEOUT 5000
|
||||
|
||||
#define INTX_NUM 4
|
||||
|
||||
#define DWORD_MASK 3
|
||||
|
|
@ -81,9 +83,30 @@ struct tlp_rp_regpair_t {
|
|||
u32 reg1;
|
||||
};
|
||||
|
||||
static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
|
||||
const u32 reg)
|
||||
{
|
||||
writel_relaxed(value, pcie->cra_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
|
||||
{
|
||||
return readl_relaxed(pcie->cra_base + reg);
|
||||
}
|
||||
|
||||
static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
|
||||
{
|
||||
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
|
||||
}
|
||||
|
||||
static void altera_pcie_retrain(struct pci_dev *dev)
|
||||
{
|
||||
u16 linkcap, linkstat;
|
||||
struct altera_pcie *pcie = dev->bus->sysdata;
|
||||
int timeout = 0;
|
||||
|
||||
if (!altera_pcie_link_is_up(pcie))
|
||||
return;
|
||||
|
||||
/*
|
||||
* Set the retrain bit if the PCIe rootport support > 2.5GB/s, but
|
||||
|
|
@ -95,9 +118,16 @@ static void altera_pcie_retrain(struct pci_dev *dev)
|
|||
return;
|
||||
|
||||
pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &linkstat);
|
||||
if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB)
|
||||
if ((linkstat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) {
|
||||
pcie_capability_set_word(dev, PCI_EXP_LNKCTL,
|
||||
PCI_EXP_LNKCTL_RL);
|
||||
while (!altera_pcie_link_is_up(pcie)) {
|
||||
timeout++;
|
||||
if (timeout > LINK_UP_TIMEOUT)
|
||||
break;
|
||||
udelay(5);
|
||||
}
|
||||
}
|
||||
}
|
||||
DECLARE_PCI_FIXUP_EARLY(0x1172, PCI_ANY_ID, altera_pcie_retrain);
|
||||
|
||||
|
|
@ -120,17 +150,6 @@ static bool altera_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int devfn,
|
|||
return false;
|
||||
}
|
||||
|
||||
static inline void cra_writel(struct altera_pcie *pcie, const u32 value,
|
||||
const u32 reg)
|
||||
{
|
||||
writel_relaxed(value, pcie->cra_base + reg);
|
||||
}
|
||||
|
||||
static inline u32 cra_readl(struct altera_pcie *pcie, const u32 reg)
|
||||
{
|
||||
return readl_relaxed(pcie->cra_base + reg);
|
||||
}
|
||||
|
||||
static void tlp_write_tx(struct altera_pcie *pcie,
|
||||
struct tlp_rp_regpair_t *tlp_rp_regdata)
|
||||
{
|
||||
|
|
@ -139,11 +158,6 @@ static void tlp_write_tx(struct altera_pcie *pcie,
|
|||
cra_writel(pcie, tlp_rp_regdata->ctrl, RP_TX_CNTRL);
|
||||
}
|
||||
|
||||
static bool altera_pcie_link_is_up(struct altera_pcie *pcie)
|
||||
{
|
||||
return !!((cra_readl(pcie, RP_LTSSM) & RP_LTSSM_MASK) == LTSSM_L0);
|
||||
}
|
||||
|
||||
static bool altera_pcie_valid_config(struct altera_pcie *pcie,
|
||||
struct pci_bus *bus, int dev)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -550,7 +550,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
|
|||
pcie_intc_node = of_get_next_child(node, NULL);
|
||||
if (!pcie_intc_node) {
|
||||
dev_err(dev, "No PCIe Intc node found\n");
|
||||
return PTR_ERR(pcie_intc_node);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
|
||||
|
|
@ -558,7 +558,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
|
|||
port);
|
||||
if (!port->irq_domain) {
|
||||
dev_err(dev, "Failed to get a INTx IRQ domain\n");
|
||||
return PTR_ERR(port->irq_domain);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
/* Setup MSI */
|
||||
|
|
@ -569,7 +569,7 @@ static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
|
|||
&xilinx_pcie_msi_chip);
|
||||
if (!port->irq_domain) {
|
||||
dev_err(dev, "Failed to get a MSI IRQ domain\n");
|
||||
return PTR_ERR(port->irq_domain);
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
xilinx_pcie_enable_msi(port);
|
||||
|
|
|
|||
Loading…
Reference in New Issue