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MIPS: Malta: Cleanup DMA coherence #ifdefs
DMA coherence is not user-selectable in Kconfig, and Malta selects CONFIG_DMA_MAYBE_COHERENT which in turn selects CONFIG_DMA_NONCOHERENT. Remove #ifdefs whose conditions can therefore never be true for Malta. This removes a significant amount of code from bonito_quirks_setup(), but the code is duplicated in plat_enable_iocoherency() anyway so we lose nothing but duplication. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/14188/
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1 changed files with 0 additions and 38 deletions
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@ -145,12 +145,6 @@ static int __init plat_enable_iocoherency(void)
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static void __init plat_setup_iocoherency(void)
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{
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#ifdef CONFIG_DMA_NONCOHERENT
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/*
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* Kernel has been configured with software coherency
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* but we might choose to turn it off and use hardware
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* coherency instead.
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*/
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if (plat_enable_iocoherency()) {
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if (coherentio == IO_COHERENCE_DISABLED)
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pr_info("Hardware DMA cache coherency disabled\n");
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@ -162,10 +156,6 @@ static void __init plat_setup_iocoherency(void)
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else
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pr_info("Software DMA cache coherency enabled\n");
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}
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#else
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if (!plat_enable_iocoherency())
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panic("Hardware DMA cache coherency not supported!");
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#endif
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}
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static void __init pci_clock_check(void)
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@ -227,29 +217,6 @@ static void __init bonito_quirks_setup(void)
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pr_info("Enabled Bonito debug mode\n");
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} else
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BONITO_BONGENCFG &= ~BONITO_BONGENCFG_DEBUGMODE;
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#ifndef CONFIG_DMA_NONCOHERENT
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if (BONITO_PCICACHECTRL & BONITO_PCICACHECTRL_CPUCOH_PRES) {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_CPUCOH_EN;
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pr_info("Enabled Bonito CPU coherency\n");
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argptr = fw_getcmdline();
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if (strstr(argptr, "iobcuncached")) {
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BONITO_PCICACHECTRL &= ~BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG = BONITO_PCIMEMBASECFG &
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~(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Disabled Bonito IOBC coherency\n");
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} else {
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BONITO_PCICACHECTRL |= BONITO_PCICACHECTRL_IOBCCOH_EN;
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BONITO_PCIMEMBASECFG |=
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(BONITO_PCIMEMBASECFG_MEMBASE0_CACHED |
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BONITO_PCIMEMBASECFG_MEMBASE1_CACHED);
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pr_info("Enabled Bonito IOBC coherency\n");
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}
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} else
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panic("Hardware DMA cache coherency not supported");
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#endif
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}
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void __init *plat_get_fdt(void)
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@ -280,11 +247,6 @@ void __init plat_mem_setup(void)
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*/
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enable_dma(4);
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#ifndef CONFIG_DMA_NONCOHERENT
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if (mips_revision_sconid != MIPS_REVISION_SCON_BONITO)
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panic("Hardware DMA cache coherency not supported");
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#endif
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if (mips_revision_sconid == MIPS_REVISION_SCON_BONITO)
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bonito_quirks_setup();
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