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usb: gadget: net2280: check interrupts for all endpoints
USB3380 in enhanced mode has 4 IN and 4 OUT endpoints. Check interrupts for all of them. Tested-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com> Signed-off-by: Mian Yousaf Kaukab <yousaf.kaukab@intel.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
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463e104fb0
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2 changed files with 46 additions and 12 deletions
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@ -2883,6 +2883,26 @@ static void handle_stat0_irqs_superspeed(struct net2280 *dev,
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return;
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return;
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}
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}
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static void usb338x_handle_ep_intr(struct net2280 *dev, u32 stat0)
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{
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u32 index;
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u32 bit;
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for (index = 0; index < ARRAY_SIZE(ep_bit); index++) {
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bit = BIT(ep_bit[index]);
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if (!stat0)
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break;
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if (!(stat0 & bit))
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continue;
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stat0 &= ~bit;
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handle_ep_small(&dev->ep[index]);
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}
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}
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static void handle_stat0_irqs(struct net2280 *dev, u32 stat)
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static void handle_stat0_irqs(struct net2280 *dev, u32 stat)
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{
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{
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struct net2280_ep *ep;
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struct net2280_ep *ep;
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@ -3107,20 +3127,31 @@ static void handle_stat0_irqs(struct net2280 *dev, u32 stat)
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#undef w_length
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#undef w_length
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next_endpoints:
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next_endpoints:
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/* endpoint data irq ? */
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if ((dev->quirks & PLX_SUPERSPEED) && dev->enhanced_mode) {
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scratch = stat & 0x7f;
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u32 mask = (BIT(ENDPOINT_0_INTERRUPT) |
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stat &= ~0x7f;
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USB3380_IRQSTAT0_EP_INTR_MASK_IN |
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for (num = 0; scratch; num++) {
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USB3380_IRQSTAT0_EP_INTR_MASK_OUT);
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u32 t;
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/* do this endpoint's FIFO and queue need tending? */
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if (stat & mask) {
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t = BIT(num);
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usb338x_handle_ep_intr(dev, stat & mask);
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if ((scratch & t) == 0)
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stat &= ~mask;
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continue;
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}
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scratch ^= t;
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} else {
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/* endpoint data irq ? */
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scratch = stat & 0x7f;
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stat &= ~0x7f;
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for (num = 0; scratch; num++) {
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u32 t;
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ep = &dev->ep[num];
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/* do this endpoint's FIFO and queue need tending? */
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handle_ep_small(ep);
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t = BIT(num);
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if ((scratch & t) == 0)
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continue;
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scratch ^= t;
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ep = &dev->ep[num];
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handle_ep_small(ep);
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}
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}
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}
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if (stat)
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if (stat)
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@ -168,6 +168,9 @@ struct net2280_regs {
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#define ENDPOINT_B_INTERRUPT 2
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#define ENDPOINT_B_INTERRUPT 2
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#define ENDPOINT_A_INTERRUPT 1
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#define ENDPOINT_A_INTERRUPT 1
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#define ENDPOINT_0_INTERRUPT 0
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#define ENDPOINT_0_INTERRUPT 0
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#define USB3380_IRQSTAT0_EP_INTR_MASK_IN (0xF << 17)
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#define USB3380_IRQSTAT0_EP_INTR_MASK_OUT (0xF << 1)
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u32 irqstat1;
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u32 irqstat1;
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#define POWER_STATE_CHANGE_INTERRUPT 27
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#define POWER_STATE_CHANGE_INTERRUPT 27
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#define PCI_ARBITER_TIMEOUT_INTERRUPT 26
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#define PCI_ARBITER_TIMEOUT_INTERRUPT 26
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