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MIPS: Fix delay slot bug in `atomic*_sub_if_positive' for R10000_LLSC_WAR
This patch fixes an old bug in MIPS ll/sc atomics, in the `atomic_sub_if_positive' and `atomic64_sub_if_positive' functions, for the R10000_LLSC_WAR case where the result of the subu/dsubu instruction would potentially not be made available to the sc/scd instruction due to being in the delay-slot of the branch-likely (beqzl) instruction. This also removes the need for the `noreorder' directive, allowing GAS to use delay slot scheduling as needed. The same fix is also applied to the standard branch (beqz) case in preparation for a follow-up patch that will cleanup/merge the R10000_LLSC_WAR and non-R10K sections together. Signed-off-by: Joshua Kinard <kumba@gentoo.org> Signed-off-by: Paul Burton <paul.burton@mips.com> Tested-by: Joshua Kinard <kumba@gentoo.org> Patchwork: https://patchwork.linux-mips.org/patch/17735/ Cc: Ralf Baechle <ralf@linux-mips.org> Cc: James Hogan <james.hogan@mips.com> Cc: "Maciej W. Rozycki" <macro@mips.com> Cc: linux-mips@linux-mips.org
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1 changed files with 12 additions and 20 deletions
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@ -225,12 +225,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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" .set arch=r4000 \n"
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"1: ll %1, %2 # atomic_sub_if_positive\n"
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" subu %0, %1, %3 \n"
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" sc %0, %2 \n"
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" .set noreorder \n"
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" beqzl %0, 1b \n"
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" subu %0, %1, %3 \n"
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" .set reorder \n"
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" sc %1, %2 \n"
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" beqzl %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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@ -244,12 +242,10 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
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" .set "MIPS_ISA_LEVEL" \n"
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"1: ll %1, %2 # atomic_sub_if_positive\n"
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" subu %0, %1, %3 \n"
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" sc %0, %2 \n"
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" .set noreorder \n"
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" beqz %0, 1b \n"
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" subu %0, %1, %3 \n"
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" .set reorder \n"
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" sc %1, %2 \n"
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" beqz %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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@ -570,12 +566,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
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" .set arch=r4000 \n"
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"1: lld %1, %2 # atomic64_sub_if_positive\n"
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" dsubu %0, %1, %3 \n"
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" scd %0, %2 \n"
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" .set noreorder \n"
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" beqzl %0, 1b \n"
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" dsubu %0, %1, %3 \n"
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" .set reorder \n"
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" scd %1, %2 \n"
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" beqzl %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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@ -589,12 +583,10 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
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" .set "MIPS_ISA_LEVEL" \n"
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"1: lld %1, %2 # atomic64_sub_if_positive\n"
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" dsubu %0, %1, %3 \n"
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" move %1, %0 \n"
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" bltz %0, 1f \n"
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" scd %0, %2 \n"
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" .set noreorder \n"
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" beqz %0, 1b \n"
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" dsubu %0, %1, %3 \n"
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" .set reorder \n"
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" scd %1, %2 \n"
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" beqz %1, 1b \n"
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"1: \n"
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" .set mips0 \n"
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: "=&r" (result), "=&r" (temp),
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