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drm/amdgpu: Add NBIO SMN headers v2
We need these offsets for PCIE perf counters, so include them as well as the the previously-used defines from the nbio_*.c files v2: Return NBIF definitions back to previous files Signed-off-by: Kent Russell <kent.russell@amd.com> Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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6 changed files with 168 additions and 12 deletions
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@ -27,13 +27,9 @@
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#include "nbio/nbio_6_1_default.h"
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#include "nbio/nbio_6_1_default.h"
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#include "nbio/nbio_6_1_offset.h"
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#include "nbio/nbio_6_1_offset.h"
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#include "nbio/nbio_6_1_sh_mask.h"
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#include "nbio/nbio_6_1_sh_mask.h"
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#include "nbio/nbio_6_1_smn.h"
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#include "vega10_enum.h"
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#include "vega10_enum.h"
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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#define smnPCIE_CONFIG_CNTL 0x11180044
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#define smnPCIE_CI_CNTL 0x11180080
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static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
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static u32 nbio_v6_1_get_rev_id(struct amdgpu_device *adev)
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{
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{
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u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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@ -27,13 +27,11 @@
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#include "nbio/nbio_7_0_default.h"
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#include "nbio/nbio_7_0_default.h"
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#include "nbio/nbio_7_0_offset.h"
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#include "nbio/nbio_7_0_offset.h"
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#include "nbio/nbio_7_0_sh_mask.h"
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#include "nbio/nbio_7_0_sh_mask.h"
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#include "nbio/nbio_7_0_smn.h"
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#include "vega10_enum.h"
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#include "vega10_enum.h"
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#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
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#define smnNBIF_MGCG_CTRL_LCLK 0x1013a05c
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
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static u32 nbio_v7_0_get_rev_id(struct amdgpu_device *adev)
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{
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{
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u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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@ -26,13 +26,10 @@
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#include "nbio/nbio_7_4_offset.h"
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#include "nbio/nbio_7_4_offset.h"
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#include "nbio/nbio_7_4_sh_mask.h"
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#include "nbio/nbio_7_4_sh_mask.h"
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#include "nbio/nbio_7_4_0_smn.h"
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#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
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#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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#define smnPCIE_CI_CNTL 0x11180080
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static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
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static u32 nbio_v7_4_get_rev_id(struct amdgpu_device *adev)
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{
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{
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u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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u32 tmp = RREG32_SOC15(NBIO, 0, mmRCC_DEV0_EPF0_STRAP0);
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58
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
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58
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
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/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _nbio_6_1_SMN_HEADER
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#define _nbio_6_1_SMN_HEADER
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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#define smnPCIE_CONFIG_CNTL 0x11180044
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#define smnPCIE_CI_CNTL 0x11180080
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#define smnPCIE_PERF_COUNT_CNTL 0x11180200
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#define smnPCIE_PERF_CNTL_TXCLK 0x11180204
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#define smnPCIE_PERF_COUNT0_TXCLK 0x11180208
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#define smnPCIE_PERF_COUNT1_TXCLK 0x1118020c
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#define smnPCIE_PERF_CNTL_MST_R_CLK 0x11180210
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#define smnPCIE_PERF_COUNT0_MST_R_CLK 0x11180214
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#define smnPCIE_PERF_COUNT1_MST_R_CLK 0x11180218
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#define smnPCIE_PERF_CNTL_MST_C_CLK 0x1118021c
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#define smnPCIE_PERF_COUNT0_MST_C_CLK 0x11180220
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#define smnPCIE_PERF_COUNT1_MST_C_CLK 0x11180224
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#define smnPCIE_PERF_CNTL_SLV_R_CLK 0x11180228
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#define smnPCIE_PERF_COUNT0_SLV_R_CLK 0x1118022c
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#define smnPCIE_PERF_COUNT1_SLV_R_CLK 0x11180230
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#define smnPCIE_PERF_CNTL_SLV_S_C_CLK 0x11180234
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#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK 0x11180238
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#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK 0x1118023c
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#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK 0x11180240
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#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x11180244
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#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x11180248
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#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1118024c
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#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x11180250
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#define smnPCIE_PERF_CNTL_TXCLK2 0x11180254
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#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258
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#define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c
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#endif // _nbio_6_1_SMN_HEADER
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54
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
Normal file
54
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
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/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _nbio_7_0_SMN_HEADER
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#define _nbio_7_0_SMN_HEADER
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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#define smnPCIE_PERF_COUNT_CNTL 0x11180200
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#define smnPCIE_PERF_CNTL_TXCLK 0x11180204
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#define smnPCIE_PERF_COUNT0_TXCLK 0x11180208
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#define smnPCIE_PERF_COUNT1_TXCLK 0x1118020c
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#define smnPCIE_PERF_CNTL_MST_R_CLK 0x11180210
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#define smnPCIE_PERF_COUNT0_MST_R_CLK 0x11180214
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#define smnPCIE_PERF_COUNT1_MST_R_CLK 0x11180218
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#define smnPCIE_PERF_CNTL_MST_C_CLK 0x1118021c
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#define smnPCIE_PERF_COUNT0_MST_C_CLK 0x11180220
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#define smnPCIE_PERF_COUNT1_MST_C_CLK 0x11180224
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#define smnPCIE_PERF_CNTL_SLV_R_CLK 0x11180228
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#define smnPCIE_PERF_COUNT0_SLV_R_CLK 0x1118022c
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#define smnPCIE_PERF_COUNT1_SLV_R_CLK 0x11180230
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#define smnPCIE_PERF_CNTL_SLV_S_C_CLK 0x11180234
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#define smnPCIE_PERF_COUNT0_SLV_S_C_CLK 0x11180238
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#define smnPCIE_PERF_COUNT1_SLV_S_C_CLK 0x1118023c
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#define smnPCIE_PERF_CNTL_SLV_NS_C_CLK 0x11180240
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#define smnPCIE_PERF_COUNT0_SLV_NS_C_CLK 0x11180244
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#define smnPCIE_PERF_COUNT1_SLV_NS_C_CLK 0x11180248
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#define smnPCIE_PERF_CNTL_EVENT0_PORT_SEL 0x1118024c
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#define smnPCIE_PERF_CNTL_EVENT1_PORT_SEL 0x11180250
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#define smnPCIE_PERF_CNTL_TXCLK2 0x11180254
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#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180258
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#define smnPCIE_PERF_COUNT1_TXCLK2 0x1118025c
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#endif // _nbio_7_0_SMN_HEADER
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53
drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
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drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
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/*
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* Copyright (C) 2019 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
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* AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _nbio_7_4_0_SMN_HEADER
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#define _nbio_7_4_0_SMN_HEADER
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#define smnNBIF_MGCG_CTRL_LCLK 0x1013a21c
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#define smnCPM_CONTROL 0x11180460
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#define smnPCIE_CNTL2 0x11180070
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#define smnPCIE_CI_CNTL 0x11180080
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#define smnPCIE_PERF_COUNT_CNTL 0x11180200
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#define smnPCIE_PERF_CNTL_TXCLK1 0x11180204
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#define smnPCIE_PERF_COUNT0_TXCLK1 0x11180208
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#define smnPCIE_PERF_COUNT1_TXCLK1 0x1118020c
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#define smnPCIE_PERF_CNTL_TXCLK2 0x11180210
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#define smnPCIE_PERF_COUNT0_TXCLK2 0x11180214
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#define smnPCIE_PERF_COUNT1_TXCLK2 0x11180218
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#define smnPCIE_PERF_CNTL_TXCLK3 0x1118021c
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#define smnPCIE_PERF_COUNT0_TXCLK3 0x11180220
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#define smnPCIE_PERF_COUNT1_TXCLK3 0x11180224
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#define smnPCIE_PERF_CNTL_TXCLK4 0x11180228
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#define smnPCIE_PERF_COUNT0_TXCLK4 0x1118022c
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#define smnPCIE_PERF_COUNT1_TXCLK4 0x11180230
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#define smnPCIE_PERF_CNTL_SCLK1 0x11180234
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#define smnPCIE_PERF_COUNT0_SCLK1 0x11180238
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#define smnPCIE_PERF_COUNT1_SCLK1 0x1118023c
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#define smnPCIE_PERF_CNTL_SCLK2 0x11180240
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#define smnPCIE_PERF_COUNT0_SCLK2 0x11180244
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#define smnPCIE_PERF_COUNT1_SCLK2 0x11180248
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#define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL 0x1118024c
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#define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL 0x11180250
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#endif // _nbio_7_4_0_SMN_HEADER
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