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drm/i915: always use INTEL_INFO() to access device info
Hide the way device info is stored, in preparation of making device info a pointer to the const rodata in i915_pci.c. No functional changes. Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/3cd626f248c0d6638f1288938bbb577a12286050.1546267488.git.jani.nikula@intel.com
This commit is contained in:
parent
1400cc7e0d
commit
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4 changed files with 53 additions and 53 deletions
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@ -1636,7 +1636,7 @@ static void i915_welcome_messages(struct drm_i915_private *dev_priv)
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if (drm_debug & DRM_UT_DRIVER) {
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if (drm_debug & DRM_UT_DRIVER) {
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struct drm_printer p = drm_debug_printer("i915 device info:");
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struct drm_printer p = drm_debug_printer("i915 device info:");
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intel_device_info_dump(&dev_priv->info, &p);
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intel_device_info_dump(INTEL_INFO(dev_priv), &p);
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intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
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intel_device_info_dump_runtime(RUNTIME_INFO(dev_priv), &p);
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}
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}
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@ -2202,7 +2202,7 @@ intel_info(const struct drm_i915_private *dev_priv)
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#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
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#define RUNTIME_INFO(dev_priv) (&(dev_priv)->__runtime)
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#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
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#define DRIVER_CAPS(dev_priv) (&(dev_priv)->caps)
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#define INTEL_GEN(dev_priv) ((dev_priv)->info.gen)
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#define INTEL_GEN(dev_priv) (INTEL_INFO(dev_priv)->gen)
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#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
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#define INTEL_DEVID(dev_priv) (RUNTIME_INFO(dev_priv)->device_id)
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#define REVID_FOREVER 0xff
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#define REVID_FOREVER 0xff
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@ -2215,11 +2215,11 @@ intel_info(const struct drm_i915_private *dev_priv)
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/* Returns true if Gen is in inclusive range [Start, End] */
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/* Returns true if Gen is in inclusive range [Start, End] */
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#define IS_GEN_RANGE(dev_priv, s, e) \
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#define IS_GEN_RANGE(dev_priv, s, e) \
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(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
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(!!(INTEL_INFO(dev_priv)->gen_mask & INTEL_GEN_MASK((s), (e))))
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#define IS_GEN(dev_priv, n) \
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#define IS_GEN(dev_priv, n) \
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(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
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(BUILD_BUG_ON_ZERO(!__builtin_constant_p(n)) + \
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(dev_priv)->info.gen == (n))
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INTEL_INFO(dev_priv)->gen == (n))
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/*
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/*
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* Return true if revision is in range [since,until] inclusive.
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* Return true if revision is in range [since,until] inclusive.
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@ -2229,7 +2229,7 @@ intel_info(const struct drm_i915_private *dev_priv)
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#define IS_REVID(p, since, until) \
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#define IS_REVID(p, since, until) \
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(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
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(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
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#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
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#define IS_PLATFORM(dev_priv, p) (INTEL_INFO(dev_priv)->platform_mask & BIT(p))
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#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
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#define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830)
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#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
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#define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G)
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@ -2251,7 +2251,7 @@ intel_info(const struct drm_i915_private *dev_priv)
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#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
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#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046)
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#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
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#define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
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#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
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#define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \
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(dev_priv)->info.gt == 1)
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INTEL_INFO(dev_priv)->gt == 1)
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#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
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#define IS_VALLEYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
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#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
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#define IS_CHERRYVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
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#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
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#define IS_HASWELL(dev_priv) IS_PLATFORM(dev_priv, INTEL_HASWELL)
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@ -2263,7 +2263,7 @@ intel_info(const struct drm_i915_private *dev_priv)
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#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
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#define IS_COFFEELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
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#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
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#define IS_CANNONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
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#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
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#define IS_ICELAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_ICELAKE)
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#define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile)
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#define IS_MOBILE(dev_priv) (INTEL_INFO(dev_priv)->is_mobile)
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#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
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#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
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(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
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#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
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#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \
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@ -2274,13 +2274,13 @@ intel_info(const struct drm_i915_private *dev_priv)
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#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
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#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0xf) == 0xe)
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(INTEL_DEVID(dev_priv) & 0xf) == 0xe)
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#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
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#define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \
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(dev_priv)->info.gt == 3)
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
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#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
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(INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
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#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
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#define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \
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(dev_priv)->info.gt == 3)
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
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#define IS_HSW_GT1(dev_priv) (IS_HASWELL(dev_priv) && \
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(dev_priv)->info.gt == 1)
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INTEL_INFO(dev_priv)->gt == 1)
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/* ULX machines are also considered ULT. */
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/* ULX machines are also considered ULT. */
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#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
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#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \
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INTEL_DEVID(dev_priv) == 0x0A1E)
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INTEL_DEVID(dev_priv) == 0x0A1E)
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@ -2303,21 +2303,21 @@ intel_info(const struct drm_i915_private *dev_priv)
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#define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
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#define IS_AML_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x591C || \
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INTEL_DEVID(dev_priv) == 0x87C0)
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INTEL_DEVID(dev_priv) == 0x87C0)
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#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
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#define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \
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(dev_priv)->info.gt == 2)
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INTEL_INFO(dev_priv)->gt == 2)
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#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
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#define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \
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(dev_priv)->info.gt == 3)
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
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#define IS_SKL_GT4(dev_priv) (IS_SKYLAKE(dev_priv) && \
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(dev_priv)->info.gt == 4)
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INTEL_INFO(dev_priv)->gt == 4)
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#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
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#define IS_KBL_GT2(dev_priv) (IS_KABYLAKE(dev_priv) && \
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(dev_priv)->info.gt == 2)
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INTEL_INFO(dev_priv)->gt == 2)
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#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
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#define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \
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(dev_priv)->info.gt == 3)
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
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(INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
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#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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#define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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(dev_priv)->info.gt == 2)
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INTEL_INFO(dev_priv)->gt == 2)
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#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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#define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \
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(dev_priv)->info.gt == 3)
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INTEL_INFO(dev_priv)->gt == 3)
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#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
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#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \
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(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
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(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
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@ -2390,27 +2390,27 @@ intel_info(const struct drm_i915_private *dev_priv)
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#define ALL_ENGINES (~0)
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#define ALL_ENGINES (~0)
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#define HAS_ENGINE(dev_priv, id) \
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#define HAS_ENGINE(dev_priv, id) \
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(!!((dev_priv)->info.ring_mask & ENGINE_MASK(id)))
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(!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
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#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
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#define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
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#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
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#define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
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#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
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#define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
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#define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
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#define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
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#define HAS_LLC(dev_priv) ((dev_priv)->info.has_llc)
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#define HAS_LLC(dev_priv) (INTEL_INFO(dev_priv)->has_llc)
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#define HAS_SNOOP(dev_priv) ((dev_priv)->info.has_snoop)
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#define HAS_SNOOP(dev_priv) (INTEL_INFO(dev_priv)->has_snoop)
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#define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
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#define HAS_EDRAM(dev_priv) (!!((dev_priv)->edram_cap & EDRAM_ENABLED))
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#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
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#define HAS_WT(dev_priv) ((IS_HASWELL(dev_priv) || \
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IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
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IS_BROADWELL(dev_priv)) && HAS_EDRAM(dev_priv))
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#define HWS_NEEDS_PHYSICAL(dev_priv) ((dev_priv)->info.hws_needs_physical)
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#define HWS_NEEDS_PHYSICAL(dev_priv) (INTEL_INFO(dev_priv)->hws_needs_physical)
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#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
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#define HAS_LOGICAL_RING_CONTEXTS(dev_priv) \
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((dev_priv)->info.has_logical_ring_contexts)
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(INTEL_INFO(dev_priv)->has_logical_ring_contexts)
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#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
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#define HAS_LOGICAL_RING_ELSQ(dev_priv) \
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((dev_priv)->info.has_logical_ring_elsq)
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(INTEL_INFO(dev_priv)->has_logical_ring_elsq)
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#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
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#define HAS_LOGICAL_RING_PREEMPTION(dev_priv) \
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((dev_priv)->info.has_logical_ring_preemption)
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(INTEL_INFO(dev_priv)->has_logical_ring_preemption)
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#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
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#define HAS_EXECLISTS(dev_priv) HAS_LOGICAL_RING_CONTEXTS(dev_priv)
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#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
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#define HAS_PAGE_SIZES(dev_priv, sizes) ({ \
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GEM_BUG_ON((sizes) == 0); \
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GEM_BUG_ON((sizes) == 0); \
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((sizes) & ~(dev_priv)->info.page_sizes) == 0; \
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((sizes) & ~INTEL_INFO(dev_priv)->page_sizes) == 0; \
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})
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})
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#define HAS_OVERLAY(dev_priv) ((dev_priv)->info.display.has_overlay)
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#define HAS_OVERLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_overlay)
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#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
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#define OVERLAY_NEEDS_PHYSICAL(dev_priv) \
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((dev_priv)->info.display.overlay_needs_physical)
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(INTEL_INFO(dev_priv)->display.overlay_needs_physical)
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/* Early gen2 have a totally busted CS tlb and require pinned batches. */
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/* Early gen2 have a totally busted CS tlb and require pinned batches. */
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#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
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#define HAS_BROKEN_CS_TLB(dev_priv) (IS_I830(dev_priv) || IS_I845G(dev_priv))
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#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
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#define HAS_128_BYTE_Y_TILING(dev_priv) (!IS_GEN(dev_priv, 2) && \
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!(IS_I915G(dev_priv) || \
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!(IS_I915G(dev_priv) || \
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IS_I915GM(dev_priv)))
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IS_I915GM(dev_priv)))
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#define SUPPORTS_TV(dev_priv) ((dev_priv)->info.display.supports_tv)
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#define SUPPORTS_TV(dev_priv) (INTEL_INFO(dev_priv)->display.supports_tv)
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#define I915_HAS_HOTPLUG(dev_priv) ((dev_priv)->info.display.has_hotplug)
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#define I915_HAS_HOTPLUG(dev_priv) (INTEL_INFO(dev_priv)->display.has_hotplug)
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#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
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#define HAS_FW_BLC(dev_priv) (INTEL_GEN(dev_priv) > 2)
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#define HAS_FBC(dev_priv) ((dev_priv)->info.display.has_fbc)
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#define HAS_FBC(dev_priv) (INTEL_INFO(dev_priv)->display.has_fbc)
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#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
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#define HAS_CUR_FBC(dev_priv) (!HAS_GMCH_DISPLAY(dev_priv) && INTEL_GEN(dev_priv) >= 7)
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#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
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#define HAS_IPS(dev_priv) (IS_HSW_ULT(dev_priv) || IS_BROADWELL(dev_priv))
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#define HAS_DP_MST(dev_priv) ((dev_priv)->info.display.has_dp_mst)
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#define HAS_DP_MST(dev_priv) (INTEL_INFO(dev_priv)->display.has_dp_mst)
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#define HAS_DDI(dev_priv) ((dev_priv)->info.display.has_ddi)
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#define HAS_DDI(dev_priv) (INTEL_INFO(dev_priv)->display.has_ddi)
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#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) ((dev_priv)->info.has_fpga_dbg)
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#define HAS_FPGA_DBG_UNCLAIMED(dev_priv) (INTEL_INFO(dev_priv)->has_fpga_dbg)
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#define HAS_PSR(dev_priv) ((dev_priv)->info.display.has_psr)
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#define HAS_PSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_psr)
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#define HAS_RC6(dev_priv) ((dev_priv)->info.has_rc6)
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#define HAS_RC6(dev_priv) (INTEL_INFO(dev_priv)->has_rc6)
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#define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p)
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#define HAS_RC6p(dev_priv) (INTEL_INFO(dev_priv)->has_rc6p)
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#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
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#define HAS_RC6pp(dev_priv) (false) /* HW was never validated */
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#define HAS_CSR(dev_priv) ((dev_priv)->info.display.has_csr)
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#define HAS_CSR(dev_priv) (INTEL_INFO(dev_priv)->display.has_csr)
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#define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm)
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#define HAS_RUNTIME_PM(dev_priv) (INTEL_INFO(dev_priv)->has_runtime_pm)
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#define HAS_64BIT_RELOC(dev_priv) ((dev_priv)->info.has_64bit_reloc)
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#define HAS_64BIT_RELOC(dev_priv) (INTEL_INFO(dev_priv)->has_64bit_reloc)
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#define HAS_IPC(dev_priv) ((dev_priv)->info.display.has_ipc)
|
#define HAS_IPC(dev_priv) (INTEL_INFO(dev_priv)->display.has_ipc)
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* For now, anything with a GuC requires uCode loading, and then supports
|
* For now, anything with a GuC requires uCode loading, and then supports
|
||||||
* command submission once loaded. But these are logically independent
|
* command submission once loaded. But these are logically independent
|
||||||
* properties, so we have separate macros to test them.
|
* properties, so we have separate macros to test them.
|
||||||
*/
|
*/
|
||||||
#define HAS_GUC(dev_priv) ((dev_priv)->info.has_guc)
|
#define HAS_GUC(dev_priv) (INTEL_INFO(dev_priv)->has_guc)
|
||||||
#define HAS_GUC_CT(dev_priv) ((dev_priv)->info.has_guc_ct)
|
#define HAS_GUC_CT(dev_priv) (INTEL_INFO(dev_priv)->has_guc_ct)
|
||||||
#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
|
#define HAS_GUC_UCODE(dev_priv) (HAS_GUC(dev_priv))
|
||||||
#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
|
#define HAS_GUC_SCHED(dev_priv) (HAS_GUC(dev_priv))
|
||||||
|
|
||||||
|
@ -2495,7 +2495,7 @@ intel_info(const struct drm_i915_private *dev_priv)
|
||||||
#define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
|
#define USES_GUC_SUBMISSION(dev_priv) intel_uc_is_using_guc_submission(dev_priv)
|
||||||
#define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
|
#define USES_HUC(dev_priv) intel_uc_is_using_huc(dev_priv)
|
||||||
|
|
||||||
#define HAS_POOLED_EU(dev_priv) ((dev_priv)->info.has_pooled_eu)
|
#define HAS_POOLED_EU(dev_priv) (INTEL_INFO(dev_priv)->has_pooled_eu)
|
||||||
|
|
||||||
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
|
#define INTEL_PCH_DEVICE_ID_MASK 0xff80
|
||||||
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
|
#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
|
||||||
|
@ -2535,12 +2535,12 @@ intel_info(const struct drm_i915_private *dev_priv)
|
||||||
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
|
#define HAS_PCH_NOP(dev_priv) (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
|
||||||
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
|
#define HAS_PCH_SPLIT(dev_priv) (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
|
||||||
|
|
||||||
#define HAS_GMCH_DISPLAY(dev_priv) ((dev_priv)->info.display.has_gmch_display)
|
#define HAS_GMCH_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.has_gmch_display)
|
||||||
|
|
||||||
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
|
#define HAS_LSPCON(dev_priv) (INTEL_GEN(dev_priv) >= 9)
|
||||||
|
|
||||||
/* DPF == dynamic parity feature */
|
/* DPF == dynamic parity feature */
|
||||||
#define HAS_L3_DPF(dev_priv) ((dev_priv)->info.has_l3_dpf)
|
#define HAS_L3_DPF(dev_priv) (INTEL_INFO(dev_priv)->has_l3_dpf)
|
||||||
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
|
#define NUM_L3_SLICES(dev_priv) (IS_HSW_GT3(dev_priv) ? \
|
||||||
2 : HAS_L3_DPF(dev_priv))
|
2 : HAS_L3_DPF(dev_priv))
|
||||||
|
|
||||||
|
@ -3302,7 +3302,7 @@ static inline void intel_unregister_dsm_handler(void) { return; }
|
||||||
static inline struct intel_device_info *
|
static inline struct intel_device_info *
|
||||||
mkwrite_device_info(struct drm_i915_private *dev_priv)
|
mkwrite_device_info(struct drm_i915_private *dev_priv)
|
||||||
{
|
{
|
||||||
return (struct intel_device_info *)&dev_priv->info;
|
return (struct intel_device_info *)INTEL_INFO(dev_priv);
|
||||||
}
|
}
|
||||||
|
|
||||||
/* modesetting */
|
/* modesetting */
|
||||||
|
|
|
@ -185,14 +185,14 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
|
||||||
* Device info offset array based helpers for groups of registers with unevenly
|
* Device info offset array based helpers for groups of registers with unevenly
|
||||||
* spaced base offsets.
|
* spaced base offsets.
|
||||||
*/
|
*/
|
||||||
#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
|
#define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \
|
||||||
dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
|
INTEL_INFO(dev_priv)->pipe_offsets[PIPE_A] + (reg) + \
|
||||||
DISPLAY_MMIO_BASE(dev_priv))
|
DISPLAY_MMIO_BASE(dev_priv))
|
||||||
#define _MMIO_TRANS2(pipe, reg) _MMIO(dev_priv->info.trans_offsets[(pipe)] - \
|
#define _MMIO_TRANS2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->trans_offsets[(pipe)] - \
|
||||||
dev_priv->info.trans_offsets[TRANSCODER_A] + (reg) + \
|
INTEL_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + (reg) + \
|
||||||
DISPLAY_MMIO_BASE(dev_priv))
|
DISPLAY_MMIO_BASE(dev_priv))
|
||||||
#define _CURSOR2(pipe, reg) _MMIO(dev_priv->info.cursor_offsets[(pipe)] - \
|
#define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \
|
||||||
dev_priv->info.cursor_offsets[PIPE_A] + (reg) + \
|
INTEL_INFO(dev_priv)->cursor_offsets[PIPE_A] + (reg) + \
|
||||||
DISPLAY_MMIO_BASE(dev_priv))
|
DISPLAY_MMIO_BASE(dev_priv))
|
||||||
|
|
||||||
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
|
#define __MASKED_FIELD(mask, value) ((mask) << 16 | (value))
|
||||||
|
|
|
@ -2361,7 +2361,7 @@ bool intel_has_gpu_reset(struct drm_i915_private *dev_priv)
|
||||||
|
|
||||||
bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
|
bool intel_has_reset_engine(struct drm_i915_private *dev_priv)
|
||||||
{
|
{
|
||||||
return (dev_priv->info.has_reset_engine &&
|
return (INTEL_INFO(dev_priv)->has_reset_engine &&
|
||||||
i915_modparams.reset >= 2);
|
i915_modparams.reset >= 2);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
Loading…
Reference in a new issue