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[ARM] pxa: cpufreq-pxa2xx: sdram_rows detection support
This patch implements Eric Miao's idea to detect the correct value of sdram_rows by inspecting the MDCNFG register settings. It is only tested on two pxa27x devices with 64MB RAM (magician and hx4700) so far. Signed-off-by: Philipp Zabel <philipp.zabel@gmail.com> Signed-off-by: Eric Miao <eric.miao@marvell.com>
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2 changed files with 27 additions and 3 deletions
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@ -64,7 +64,7 @@ typedef struct {
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/* Define the refresh period in mSec for the SDRAM and the number of rows */
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#define SDRAM_TREF 64 /* standard 64ms SDRAM */
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#define SDRAM_ROWS 4096 /* 64MB=8192 32MB=4096 */
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static unsigned int sdram_rows;
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#define CCLKCFG_TURBO 0x1
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#define CCLKCFG_FCS 0x2
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@ -73,6 +73,9 @@ typedef struct {
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#define MDREFR_DB2_MASK (MDREFR_K2DB2 | MDREFR_K1DB2)
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#define MDREFR_DRI_MASK 0xFFF
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#define MDCNFG_DRAC2(mdcnfg) (((mdcnfg) >> 21) & 0x3)
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#define MDCNFG_DRAC0(mdcnfg) (((mdcnfg) >> 5) & 0x3)
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/*
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* PXA255 definitions
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*/
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@ -192,14 +195,28 @@ static void pxa27x_guess_max_freq(void)
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}
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}
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static void init_sdram_rows(void)
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{
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uint32_t mdcnfg = MDCNFG;
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unsigned int drac2 = 0, drac0 = 0;
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if (mdcnfg & (MDCNFG_DE2 | MDCNFG_DE3))
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drac2 = MDCNFG_DRAC2(mdcnfg);
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if (mdcnfg & (MDCNFG_DE0 | MDCNFG_DE1))
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drac0 = MDCNFG_DRAC0(mdcnfg);
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sdram_rows = 1 << (11 + max(drac0, drac2));
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}
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static u32 mdrefr_dri(unsigned int freq)
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{
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u32 dri = 0;
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if (cpu_is_pxa25x())
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dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS * 32));
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dri = ((freq * SDRAM_TREF) / (sdram_rows * 32));
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if (cpu_is_pxa27x())
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dri = ((freq * SDRAM_TREF) / (SDRAM_ROWS - 31)) / 32;
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dri = ((freq * SDRAM_TREF) / (sdram_rows - 31)) / 32;
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return dri;
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}
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@ -334,6 +351,8 @@ static __init int pxa_cpufreq_init(struct cpufreq_policy *policy)
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if (cpu_is_pxa27x())
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pxa27x_guess_max_freq();
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init_sdram_rows();
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/* set default policy and cpuinfo */
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policy->cpuinfo.transition_latency = 1000; /* FIXME: 1 ms, assumed */
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policy->cur = get_clk_frequency_khz(0); /* current freq */
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@ -49,6 +49,11 @@
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#define MECR_NOS (1 << 0) /* Number Of Sockets: 0 -> 1 sock, 1 -> 2 sock */
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#define MECR_CIT (1 << 1) /* Card Is There: 0 -> no card, 1 -> card inserted */
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#define MDCNFG_DE0 (1 << 0) /* SDRAM Bank 0 Enable */
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#define MDCNFG_DE1 (1 << 1) /* SDRAM Bank 1 Enable */
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#define MDCNFG_DE2 (1 << 16) /* SDRAM Bank 2 Enable */
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#define MDCNFG_DE3 (1 << 17) /* SDRAM Bank 3 Enable */
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#define MDREFR_K0DB4 (1 << 29) /* SDCLK0 Divide by 4 Control/Status */
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#define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
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#define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
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