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drm/i915/skl: drop workarounds for A0 and B0 revisions
Pre-production hardware is not supported. Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/7929af62a68504c84038a8db1625bd96ebaa9e6f.1474034059.git.jani.nikula@intel.com
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4c0b8a8bc4
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a117f378f4
5 changed files with 11 additions and 30 deletions
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@ -1299,10 +1299,6 @@ bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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/* WaDisableHBR2:skl */
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if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
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return false;
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if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
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(INTEL_INFO(dev)->gen >= 9))
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return true;
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@ -225,9 +225,6 @@ static u32 intel_dp_training_pattern(struct intel_dp *intel_dp)
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* Intel platforms that support HBR2 also support TPS3. TPS3 support is
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* also mandatory for downstream devices that support HBR2. However, not
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* all sinks follow the spec.
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*
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* Due to WaDisableHBR2 SKL < B0 is the only exception where TPS3 is
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* supported in source but still not enabled.
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*/
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source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
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sink_tps3 = drm_dp_tps3_supported(intel_dp->dpcd);
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@ -375,9 +375,8 @@ static int guc_ucode_xfer(struct drm_i915_private *dev_priv)
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/* Enable MIA caching. GuC clock gating is disabled. */
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I915_WRITE(GUC_SHIM_CONTROL, GUC_SHIM_CONTROL_VALUE);
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/* WaDisableMinuteIaClockGating:skl,bxt */
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if (IS_SKL_REVID(dev, 0, SKL_REVID_B0) ||
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IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
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/* WaDisableMinuteIaClockGating:bxt */
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if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
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I915_WRITE(GUC_SHIM_CONTROL, (I915_READ(GUC_SHIM_CONTROL) &
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~GUC_ENABLE_MIA_CLOCK_GATING));
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}
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@ -269,8 +269,7 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
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struct drm_i915_private *dev_priv = engine->i915;
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engine->disable_lite_restore_wa =
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(IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
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IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) &&
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IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) &&
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(engine->id == VCS || engine->id == VCS2);
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engine->ctx_desc_template = GEN8_CTX_VALID;
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@ -1068,9 +1067,8 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
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{
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uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
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if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) ||
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IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
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/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
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if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) {
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wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1));
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wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0);
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wa_ctx_emit(batch, index,
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@ -851,15 +851,13 @@ static int gen9_init_workarounds(struct intel_engine_cs *engine)
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WA_SET_BIT_MASKED(HALF_SLICE_CHICKEN3,
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GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC);
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/* WaDisableDgMirrorFixInHalfSliceChicken5:skl,bxt */
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if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
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IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
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/* WaDisableDgMirrorFixInHalfSliceChicken5:bxt */
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if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
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WA_CLR_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN5,
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GEN9_DG_MIRROR_FIX_ENABLE);
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/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */
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if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) ||
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IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
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/* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:bxt */
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if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
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WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1,
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GEN9_RHWO_OPTIMIZATION_DISABLE);
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/*
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@ -1023,15 +1021,8 @@ static int skl_init_workarounds(struct intel_engine_cs *engine)
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GEN8_LQSC_RO_PERF_DIS);
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/* WaEnableGapsTsvCreditFix:skl */
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if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, REVID_FOREVER)) {
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I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
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GEN9_GAPS_TSV_CREDIT_DISABLE));
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}
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/* WaDisablePowerCompilerClockGating:skl */
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if (IS_SKL_REVID(dev_priv, SKL_REVID_B0, SKL_REVID_B0))
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WA_SET_BIT_MASKED(HIZ_CHICKEN,
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BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE);
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I915_WRITE(GEN8_GARBCNTL, (I915_READ(GEN8_GARBCNTL) |
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GEN9_GAPS_TSV_CREDIT_DISABLE));
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/* WaBarrierPerformanceFixDisable:skl */
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if (IS_SKL_REVID(dev_priv, SKL_REVID_C0, SKL_REVID_D0))
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