mirrors/linux-stable
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git synced 2024-09-30 06:10:56 +00:00
Code Issues Releases Wiki Activity

cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()

Browse source 
In preparation for changing how the driver handles 'mem_enable' in the CXL
DVSEC control register. Merge the contents of cxl_hdm_decode_init() into
cxl_dvsec_ranges() and rename the combined function cxl_hdm_decode_init().
The possible cleanups and fixes that result from this merge are saved for a
follow-on change.

Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://lore.kernel.org/r/165291690027.1426646.10249756632415633752.stgit@dwillia2-xfh
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams 2022-05-18 16:35:00 -07:00
parent dd2d42ad6f
commit a12562bb70
6 changed files with 83 additions and 104 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

82
drivers/cxl/core/pci.c
View file

@ -175,13 +175,71 @@ static int wait_for_valid(struct cxl_dev_state *cxlds)
return -ETIMEDOUT;
}
/*
* Return positive number of non-zero ranges on success and a negative
* error code on failure. The cxl_mem driver depends on ranges == 0 to
* init HDM operation.
static bool __cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
struct cxl_endpoint_dvsec_info *info)
{
struct cxl_register_map map;
struct cxl_component_reg_map *cmap = &map.component_map;
bool global_enable, retval = false;
void __iomem *crb;
u32 global_ctrl;
/* map hdm decoder */
crb = ioremap(cxlds->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
if (!crb) {
dev_dbg(cxlds->dev, "Failed to map component registers\n");
return false;
}
cxl_probe_component_regs(cxlds->dev, crb, cmap);
if (!cmap->hdm_decoder.valid) {
dev_dbg(cxlds->dev, "Invalid HDM decoder registers\n");
goto out;
}
global_ctrl = readl(crb + cmap->hdm_decoder.offset +
CXL_HDM_DECODER_CTRL_OFFSET);
global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE;
/*
* Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
* [High,Low] when HDM operation is enabled the range register values
* are ignored by the device, but the spec also recommends matching the
* DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
* are expected even though Linux does not require or maintain that
* match.
*/
if (!global_enable && info->mem_enabled && info->ranges)
goto out;
retval = true;
/*
* Permanently (for this boot at least) opt the device into HDM
* operation. Individual HDM decoders still need to be enabled after
* this point.
*/
if (!global_enable) {
dev_dbg(cxlds->dev, "Enabling HDM decode\n");
writel(global_ctrl | CXL_HDM_DECODER_ENABLE,
crb + cmap->hdm_decoder.offset +
CXL_HDM_DECODER_CTRL_OFFSET);
}
out:
iounmap(crb);
return retval;
}
/**
* cxl_hdm_decode_init() - Setup HDM decoding for the endpoint
* @cxlds: Device state
* @info: DVSEC Range cached enumeration
*
* Try to enable the endpoint's HDM Decoder Capability
*/
int cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
struct cxl_endpoint_dvsec_info *info)
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
struct cxl_endpoint_dvsec_info *info)
{
struct pci_dev *pdev = to_pci_dev(cxlds->dev);
int hdm_count, rc, i, ranges = 0;
@ -270,6 +328,16 @@ int cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
info->ranges = ranges;
/*
* If DVSEC ranges are being used instead of HDM decoder registers there
* is no use in trying to manage those.
*/
if (!__cxl_hdm_decode_init(cxlds, info)) {
dev_err(dev,
"Legacy range registers configuration prevents HDM operation.\n");
return -EBUSY;
}
return 0;
}
EXPORT_SYMBOL_NS_GPL(cxl_dvsec_ranges, CXL);
EXPORT_SYMBOL_NS_GPL(cxl_hdm_decode_init, CXL);

4
drivers/cxl/cxlpci.h
View file

@ -74,6 +74,6 @@ static inline resource_size_t cxl_regmap_to_base(struct pci_dev *pdev,
int devm_cxl_port_enumerate_dports(struct cxl_port *port);
struct cxl_dev_state;
struct cxl_endpoint_dvsec_info;
int cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
struct cxl_endpoint_dvsec_info *info);
int cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
struct cxl_endpoint_dvsec_info *info);
#endif /* __CXL_PCI_H__ */

80
drivers/cxl/mem.c
View file

@ -46,74 +46,6 @@ static int create_endpoint(struct cxl_memdev *cxlmd,
return cxl_endpoint_autoremove(cxlmd, endpoint);
}
/**
* cxl_hdm_decode_init() - Setup HDM decoding for the endpoint
* @cxlds: Device state
*
* Additionally, enables global HDM decoding. Warning: don't call this outside
* of probe. Once probe is complete, the port driver owns all access to the HDM
* decoder registers.
*
* Returns: false if DVSEC Ranges are being used instead of HDM
* decoders, or if it can not be determined if DVSEC Ranges are in use.
* Otherwise, returns true.
*/
__mock bool cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
struct cxl_endpoint_dvsec_info *info)
{
struct cxl_register_map map;
struct cxl_component_reg_map *cmap = &map.component_map;
bool global_enable, retval = false;
void __iomem *crb;
u32 global_ctrl;
/* map hdm decoder */
crb = ioremap(cxlds->component_reg_phys, CXL_COMPONENT_REG_BLOCK_SIZE);
if (!crb) {
dev_dbg(cxlds->dev, "Failed to map component registers\n");
return false;
}
cxl_probe_component_regs(cxlds->dev, crb, cmap);
if (!cmap->hdm_decoder.valid) {
dev_dbg(cxlds->dev, "Invalid HDM decoder registers\n");
goto out;
}
global_ctrl = readl(crb + cmap->hdm_decoder.offset +
CXL_HDM_DECODER_CTRL_OFFSET);
global_enable = global_ctrl & CXL_HDM_DECODER_ENABLE;
/*
* Per CXL 2.0 Section 8.1.3.8.3 and 8.1.3.8.4 DVSEC CXL Range 1 Base
* [High,Low] when HDM operation is enabled the range register values
* are ignored by the device, but the spec also recommends matching the
* DVSEC Range 1,2 to HDM Decoder Range 0,1. So, non-zero info->ranges
* are expected even though Linux does not require or maintain that
* match.
*/
if (!global_enable && info->mem_enabled && info->ranges)
goto out;
retval = true;
/*
* Permanently (for this boot at least) opt the device into HDM
* operation. Individual HDM decoders still need to be enabled after
* this point.
*/
if (!global_enable) {
dev_dbg(cxlds->dev, "Enabling HDM decode\n");
writel(global_ctrl | CXL_HDM_DECODER_ENABLE,
crb + cmap->hdm_decoder.offset +
CXL_HDM_DECODER_CTRL_OFFSET);
}
out:
iounmap(crb);
return retval;
}
static void enable_suspend(void *data)
{
cxl_mem_active_dec();
@ -163,7 +95,7 @@ static int cxl_mem_probe(struct device *dev)
if (rc)
return rc;
rc = cxl_dvsec_ranges(cxlds, &info);
rc = cxl_hdm_decode_init(cxlds, &info);
if (rc)
return rc;
@ -173,16 +105,6 @@ static int cxl_mem_probe(struct device *dev)
return rc;
}
/*
* If DVSEC ranges are being used instead of HDM decoder registers there
* is no use in trying to manage those.
*/
if (!cxl_hdm_decode_init(cxlds, &info)) {
dev_err(dev,
"Legacy range registers configuration prevents HDM operation.\n");
return -EBUSY;
}
/*
* The kernel may be operating out of CXL memory on this device,
* there is no spec defined way to determine whether this device

3
tools/testing/cxl/Kbuild
View file

@ -9,7 +9,7 @@ ldflags-y += --wrap=devm_cxl_setup_hdm
ldflags-y += --wrap=devm_cxl_add_passthrough_decoder
ldflags-y += --wrap=devm_cxl_enumerate_decoders
ldflags-y += --wrap=cxl_await_media_ready
ldflags-y += --wrap=cxl_dvsec_ranges
ldflags-y += --wrap=cxl_hdm_decode_init
DRIVERS := ../../../drivers
CXL_SRC := $(DRIVERS)/cxl
@ -36,7 +36,6 @@ cxl_port-y += config_check.o
obj-m += cxl_mem.o
cxl_mem-y := $(CXL_SRC)/mem.o
cxl_mem-y += mock_mem.o
cxl_mem-y += config_check.o
obj-m += cxl_core.o

10
tools/testing/cxl/mock_mem.c
View file

@ -1,10 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-only
/* Copyright(c) 2022 Intel Corporation. All rights reserved. */
#include <linux/types.h>
struct cxl_dev_state;
bool cxl_hdm_decode_init(struct cxl_dev_state *cxlds)
{
return true;
}

8
tools/testing/cxl/test/mock.c
View file

@ -208,8 +208,8 @@ int __wrap_cxl_await_media_ready(struct cxl_dev_state *cxlds)
}
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_await_media_ready, CXL);
int __wrap_cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
struct cxl_endpoint_dvsec_info *info)
int __wrap_cxl_hdm_decode_init(struct cxl_dev_state *cxlds,
struct cxl_endpoint_dvsec_info *info)
{
int rc = 0, index;
struct cxl_mock_ops *ops = get_cxl_mock_ops(&index);
@ -217,12 +217,12 @@ int __wrap_cxl_dvsec_ranges(struct cxl_dev_state *cxlds,
if (ops && ops->is_mock_dev(cxlds->dev))
info->mem_enabled = 1;
else
rc = cxl_dvsec_ranges(cxlds, info);
rc = cxl_hdm_decode_init(cxlds, info);
put_cxl_mock_ops(index);
return rc;
}
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_dvsec_ranges, CXL);
EXPORT_SYMBOL_NS_GPL(__wrap_cxl_hdm_decode_init, CXL);
MODULE_LICENSE("GPL v2");
MODULE_IMPORT_NS(ACPI);