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ARM: EXYNOS: add secure firmware support to AFTR mode code
* Move cp15 registers saving to exynos_save_cp15() helper and add additional helper usage to do_idle firmware method. * Use resume firmware method instead of exynos_cpu_restore_register() and skip exynos_cpu_save_register() on boards with secure firmware enabled. * Use sysram_ns_base_addr + 0x24/0x20 addresses instead of the default ones used by exynos_cpu_set_boot_vector() on boards with secure firmware enabled. * Use do_idle firmware method instead of cpu_do_idle() on boards with secure firmware enabled. Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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parent
0b7778a801
commit
a135e20185
2 changed files with 29 additions and 12 deletions
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@ -25,13 +25,28 @@
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#include "smc.h"
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#include "smc.h"
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#define EXYNOS_SLEEP_MAGIC 0x00000bad
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#define EXYNOS_SLEEP_MAGIC 0x00000bad
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#define EXYNOS_AFTR_MAGIC 0xfcba0d10
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#define EXYNOS_BOOT_ADDR 0x8
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#define EXYNOS_BOOT_ADDR 0x8
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#define EXYNOS_BOOT_FLAG 0xc
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#define EXYNOS_BOOT_FLAG 0xc
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static void exynos_save_cp15(void)
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{
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/* Save Power control and Diagnostic registers */
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asm ("mrc p15, 0, %0, c15, c0, 0\n"
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"mrc p15, 0, %1, c15, c0, 1\n"
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: "=r" (cp15_save_power), "=r" (cp15_save_diag)
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: : "cc");
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}
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static int exynos_do_idle(unsigned long mode)
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static int exynos_do_idle(unsigned long mode)
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{
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{
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switch (mode) {
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switch (mode) {
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case FW_DO_IDLE_AFTR:
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case FW_DO_IDLE_AFTR:
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_save_cp15();
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__raw_writel(virt_to_phys(exynos_cpu_resume_ns),
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sysram_ns_base_addr + 0x24);
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__raw_writel(EXYNOS_AFTR_MAGIC, sysram_ns_base_addr + 0x20);
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exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
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exynos_smc(SMC_CMD_CPU0AFTR, 0, 0, 0);
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break;
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break;
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case FW_DO_IDLE_SLEEP:
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case FW_DO_IDLE_SLEEP:
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@ -96,13 +111,8 @@ static int exynos_cpu_suspend(unsigned long arg)
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static int exynos_suspend(void)
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static int exynos_suspend(void)
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{
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{
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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/* Save Power control and Diagnostic registers */
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exynos_save_cp15();
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asm ("mrc p15, 0, %0, c15, c0, 0\n"
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"mrc p15, 0, %1, c15, c0, 1\n"
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: "=r" (cp15_save_power), "=r" (cp15_save_diag)
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: : "cc");
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}
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writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
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writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
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writel(virt_to_phys(exynos_cpu_resume_ns),
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writel(virt_to_phys(exynos_cpu_resume_ns),
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@ -236,11 +236,19 @@ static void exynos_cpu_set_boot_vector(long flags)
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static int exynos_aftr_finisher(unsigned long flags)
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static int exynos_aftr_finisher(unsigned long flags)
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{
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{
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int ret;
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exynos_set_wakeupmask(0x0000ff3e);
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exynos_set_wakeupmask(0x0000ff3e);
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exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
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/* Set value of power down register for aftr mode */
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/* Set value of power down register for aftr mode */
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exynos_sys_powerdown_conf(SYS_AFTR);
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exynos_sys_powerdown_conf(SYS_AFTR);
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cpu_do_idle();
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ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
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if (ret == -ENOSYS) {
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_save_register();
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exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
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cpu_do_idle();
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}
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return 1;
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return 1;
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}
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}
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@ -250,14 +258,13 @@ void exynos_enter_aftr(void)
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cpu_pm_enter();
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cpu_pm_enter();
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exynos_pm_central_suspend();
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exynos_pm_central_suspend();
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_save_register();
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cpu_suspend(0, exynos_aftr_finisher);
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cpu_suspend(0, exynos_aftr_finisher);
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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scu_enable(S5P_VA_SCU);
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scu_enable(S5P_VA_SCU);
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exynos_cpu_restore_register();
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if (call_firmware_op(resume) == -ENOSYS)
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exynos_cpu_restore_register();
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}
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}
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exynos_pm_central_resume();
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exynos_pm_central_resume();
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