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synced 2024-09-13 14:14:37 +00:00
drm/exynos: sending AVI and AUI info frames
This patch adds code for composing AVI and AUI info frames and send them every VSYNC. This patch is important for hdmi certification. v3: - Moved enums, macros to exynos_hdmi.c. - Corrected hex format. - Added static to hdmi_reg_infoframe. v2: - Added few blank lines. - Corrected comments format. - Added comments for 2's Complement calculation for check sum. v1: - Remove un-necessary blank lines. - Change the case of hex constants. Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com> Signed-off-by: Fahad Kunnathadi <fahad.k@samsung.com> Signed-off-by: Shirish S <s.shirish@samsung.com> Acked-by: Seung-Woo Kim <sw0312.kim@samsung.com> Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
This commit is contained in:
Rahul Sharma
Inki Dae
parent
a4d8de5f1b
commit
a144c2e9f1
2 changed files with 161 additions and 21 deletions
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@ -50,6 +50,29 @@
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#define MAX_HEIGHT 1080
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#define get_hdmi_context(dev) platform_get_drvdata(to_platform_device(dev))
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/* AVI header and aspect ratio */
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#define HDMI_AVI_VERSION 0x02
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#define HDMI_AVI_LENGTH 0x0D
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#define AVI_PIC_ASPECT_RATIO_16_9 (2 << 4)
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#define AVI_SAME_AS_PIC_ASPECT_RATIO 8
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/* AUI header info */
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#define HDMI_AUI_VERSION 0x01
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#define HDMI_AUI_LENGTH 0x0A
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/* HDMI infoframe to configure HDMI out packet header, AUI and AVI */
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enum HDMI_PACKET_TYPE {
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/* refer to Table 5-8 Packet Type in HDMI specification v1.4a */
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/* InfoFrame packet type */
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HDMI_PACKET_TYPE_INFOFRAME = 0x80,
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/* Vendor-Specific InfoFrame */
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HDMI_PACKET_TYPE_VSI = HDMI_PACKET_TYPE_INFOFRAME + 1,
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/* Auxiliary Video information InfoFrame */
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HDMI_PACKET_TYPE_AVI = HDMI_PACKET_TYPE_INFOFRAME + 2,
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/* Audio information InfoFrame */
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HDMI_PACKET_TYPE_AUI = HDMI_PACKET_TYPE_INFOFRAME + 4
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};
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enum hdmi_type {
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HDMI_TYPE13,
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HDMI_TYPE14,
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@ -182,6 +205,7 @@ struct hdmi_v13_conf {
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int height;
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int vrefresh;
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bool interlace;
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int cea_video_id;
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const u8 *hdmiphy_data;
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const struct hdmi_v13_preset_conf *conf;
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};
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@ -353,15 +377,20 @@ static const struct hdmi_v13_preset_conf hdmi_v13_conf_1080p60 = {
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};
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static const struct hdmi_v13_conf hdmi_v13_confs[] = {
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{ 1280, 720, 60, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
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{ 1280, 720, 50, false, hdmiphy_v13_conf74_25, &hdmi_v13_conf_720p60 },
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{ 720, 480, 60, false, hdmiphy_v13_conf27_027, &hdmi_v13_conf_480p },
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{ 1920, 1080, 50, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i50 },
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{ 1920, 1080, 50, false, hdmiphy_v13_conf148_5,
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&hdmi_v13_conf_1080p50 },
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{ 1920, 1080, 60, true, hdmiphy_v13_conf74_25, &hdmi_v13_conf_1080i60 },
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{ 1920, 1080, 60, false, hdmiphy_v13_conf148_5,
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&hdmi_v13_conf_1080p60 },
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{ 1280, 720, 60, false, 4, hdmiphy_v13_conf74_25,
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&hdmi_v13_conf_720p60 },
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{ 1280, 720, 50, false, 19, hdmiphy_v13_conf74_25,
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&hdmi_v13_conf_720p60 },
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{ 720, 480, 60, false, 3, hdmiphy_v13_conf27_027,
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&hdmi_v13_conf_480p },
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{ 1920, 1080, 50, true, 20, hdmiphy_v13_conf74_25,
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&hdmi_v13_conf_1080i50 },
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{ 1920, 1080, 50, false, 31, hdmiphy_v13_conf148_5,
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&hdmi_v13_conf_1080p50 },
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{ 1920, 1080, 60, true, 5, hdmiphy_v13_conf74_25,
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&hdmi_v13_conf_1080i60 },
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{ 1920, 1080, 60, false, 16, hdmiphy_v13_conf148_5,
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&hdmi_v13_conf_1080p60 },
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};
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/* HDMI Version 1.4 */
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@ -479,6 +508,7 @@ struct hdmi_conf {
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int height;
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int vrefresh;
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bool interlace;
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int cea_video_id;
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const u8 *hdmiphy_data;
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const struct hdmi_preset_conf *conf;
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};
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@ -934,16 +964,21 @@ static const struct hdmi_preset_conf hdmi_conf_1080p60 = {
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};
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static const struct hdmi_conf hdmi_confs[] = {
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{ 720, 480, 60, false, hdmiphy_conf27_027, &hdmi_conf_480p60 },
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{ 1280, 720, 50, false, hdmiphy_conf74_25, &hdmi_conf_720p50 },
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{ 1280, 720, 60, false, hdmiphy_conf74_25, &hdmi_conf_720p60 },
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{ 1920, 1080, 50, true, hdmiphy_conf74_25, &hdmi_conf_1080i50 },
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{ 1920, 1080, 60, true, hdmiphy_conf74_25, &hdmi_conf_1080i60 },
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{ 1920, 1080, 30, false, hdmiphy_conf74_176, &hdmi_conf_1080p30 },
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{ 1920, 1080, 50, false, hdmiphy_conf148_5, &hdmi_conf_1080p50 },
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{ 1920, 1080, 60, false, hdmiphy_conf148_5, &hdmi_conf_1080p60 },
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{ 720, 480, 60, false, 3, hdmiphy_conf27_027, &hdmi_conf_480p60 },
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{ 1280, 720, 50, false, 19, hdmiphy_conf74_25, &hdmi_conf_720p50 },
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{ 1280, 720, 60, false, 4, hdmiphy_conf74_25, &hdmi_conf_720p60 },
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{ 1920, 1080, 50, true, 20, hdmiphy_conf74_25, &hdmi_conf_1080i50 },
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{ 1920, 1080, 60, true, 5, hdmiphy_conf74_25, &hdmi_conf_1080i60 },
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{ 1920, 1080, 30, false, 34, hdmiphy_conf74_176, &hdmi_conf_1080p30 },
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{ 1920, 1080, 50, false, 31, hdmiphy_conf148_5, &hdmi_conf_1080p50 },
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{ 1920, 1080, 60, false, 16, hdmiphy_conf148_5, &hdmi_conf_1080p60 },
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};
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struct hdmi_infoframe {
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enum HDMI_PACKET_TYPE type;
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u8 ver;
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u8 len;
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};
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static inline u32 hdmi_reg_read(struct hdmi_context *hdata, u32 reg_id)
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{
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@ -1267,6 +1302,88 @@ static int hdmi_conf_index(struct hdmi_context *hdata,
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return hdmi_v14_conf_index(mode);
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}
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static u8 hdmi_chksum(struct hdmi_context *hdata,
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u32 start, u8 len, u32 hdr_sum)
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{
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int i;
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/* hdr_sum : header0 + header1 + header2
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* start : start address of packet byte1
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* len : packet bytes - 1 */
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for (i = 0; i < len; ++i)
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hdr_sum += 0xff & hdmi_reg_read(hdata, start + i * 4);
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/* return 2's complement of 8 bit hdr_sum */
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return (u8)(~(hdr_sum & 0xff) + 1);
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}
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static void hdmi_reg_infoframe(struct hdmi_context *hdata,
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struct hdmi_infoframe *infoframe)
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{
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u32 hdr_sum;
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u8 chksum;
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u32 aspect_ratio;
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u32 mod;
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u32 vic;
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DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
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mod = hdmi_reg_read(hdata, HDMI_MODE_SEL);
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if (hdata->dvi_mode) {
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hdmi_reg_writeb(hdata, HDMI_VSI_CON,
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HDMI_VSI_CON_DO_NOT_TRANSMIT);
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hdmi_reg_writeb(hdata, HDMI_AVI_CON,
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HDMI_AVI_CON_DO_NOT_TRANSMIT);
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hdmi_reg_writeb(hdata, HDMI_AUI_CON, HDMI_AUI_CON_NO_TRAN);
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return;
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}
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switch (infoframe->type) {
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case HDMI_PACKET_TYPE_AVI:
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hdmi_reg_writeb(hdata, HDMI_AVI_CON, HDMI_AVI_CON_EVERY_VSYNC);
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hdmi_reg_writeb(hdata, HDMI_AVI_HEADER0, infoframe->type);
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hdmi_reg_writeb(hdata, HDMI_AVI_HEADER1, infoframe->ver);
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hdmi_reg_writeb(hdata, HDMI_AVI_HEADER2, infoframe->len);
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hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
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/* Output format zero hardcoded ,RGB YBCR selection */
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hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 0 << 5 |
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AVI_ACTIVE_FORMAT_VALID |
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AVI_UNDERSCANNED_DISPLAY_VALID);
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aspect_ratio = AVI_PIC_ASPECT_RATIO_16_9;
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hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(2), aspect_ratio |
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AVI_SAME_AS_PIC_ASPECT_RATIO);
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if (hdata->type == HDMI_TYPE13)
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vic = hdmi_v13_confs[hdata->cur_conf].cea_video_id;
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else
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vic = hdmi_confs[hdata->cur_conf].cea_video_id;
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hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(4), vic);
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chksum = hdmi_chksum(hdata, HDMI_AVI_BYTE(1),
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infoframe->len, hdr_sum);
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DRM_DEBUG_KMS("AVI checksum = 0x%x\n", chksum);
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hdmi_reg_writeb(hdata, HDMI_AVI_CHECK_SUM, chksum);
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break;
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case HDMI_PACKET_TYPE_AUI:
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hdmi_reg_writeb(hdata, HDMI_AUI_CON, 0x02);
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hdmi_reg_writeb(hdata, HDMI_AUI_HEADER0, infoframe->type);
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hdmi_reg_writeb(hdata, HDMI_AUI_HEADER1, infoframe->ver);
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hdmi_reg_writeb(hdata, HDMI_AUI_HEADER2, infoframe->len);
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hdr_sum = infoframe->type + infoframe->ver + infoframe->len;
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chksum = hdmi_chksum(hdata, HDMI_AUI_BYTE(1),
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infoframe->len, hdr_sum);
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DRM_DEBUG_KMS("AUI checksum = 0x%x\n", chksum);
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hdmi_reg_writeb(hdata, HDMI_AUI_CHECK_SUM, chksum);
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break;
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default:
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break;
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}
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}
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static bool hdmi_is_connected(void *ctx)
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{
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struct hdmi_context *hdata = ctx;
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@ -1542,6 +1659,8 @@ static void hdmi_conf_reset(struct hdmi_context *hdata)
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static void hdmi_conf_init(struct hdmi_context *hdata)
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{
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struct hdmi_infoframe infoframe;
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/* disable HPD interrupts */
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hdmi_reg_writemask(hdata, HDMI_INTC_CON, 0, HDMI_INTC_EN_GLOBAL |
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HDMI_INTC_EN_HPD_PLUG | HDMI_INTC_EN_HPD_UNPLUG);
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@ -1576,9 +1695,17 @@ static void hdmi_conf_init(struct hdmi_context *hdata)
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hdmi_reg_writeb(hdata, HDMI_V13_AUI_CON, 0x02);
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hdmi_reg_writeb(hdata, HDMI_V13_ACR_CON, 0x04);
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} else {
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infoframe.type = HDMI_PACKET_TYPE_AVI;
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infoframe.ver = HDMI_AVI_VERSION;
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infoframe.len = HDMI_AVI_LENGTH;
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hdmi_reg_infoframe(hdata, &infoframe);
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infoframe.type = HDMI_PACKET_TYPE_AUI;
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infoframe.ver = HDMI_AUI_VERSION;
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infoframe.len = HDMI_AUI_LENGTH;
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hdmi_reg_infoframe(hdata, &infoframe);
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/* enable AVI packet every vsync, fixes purple line problem */
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hdmi_reg_writeb(hdata, HDMI_AVI_CON, 0x02);
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hdmi_reg_writeb(hdata, HDMI_AVI_BYTE(1), 2 << 5);
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hdmi_reg_writemask(hdata, HDMI_CON_1, 2, 3 << 5);
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}
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}
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@ -298,14 +298,14 @@
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#define HDMI_AVI_HEADER1 HDMI_CORE_BASE(0x0714)
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#define HDMI_AVI_HEADER2 HDMI_CORE_BASE(0x0718)
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#define HDMI_AVI_CHECK_SUM HDMI_CORE_BASE(0x071C)
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#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n))
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#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0720 + 4 * (n-1))
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#define HDMI_AUI_CON HDMI_CORE_BASE(0x0800)
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#define HDMI_AUI_HEADER0 HDMI_CORE_BASE(0x0810)
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#define HDMI_AUI_HEADER1 HDMI_CORE_BASE(0x0814)
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#define HDMI_AUI_HEADER2 HDMI_CORE_BASE(0x0818)
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#define HDMI_AUI_CHECK_SUM HDMI_CORE_BASE(0x081C)
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#define HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n))
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#define HDMI_AUI_BYTE(n) HDMI_CORE_BASE(0x0820 + 4 * (n-1))
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#define HDMI_MPG_CON HDMI_CORE_BASE(0x0900)
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#define HDMI_MPG_CHECK_SUM HDMI_CORE_BASE(0x091C)
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@ -338,6 +338,19 @@
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#define HDMI_AN_SEED_2 HDMI_CORE_BASE(0x0E60)
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#define HDMI_AN_SEED_3 HDMI_CORE_BASE(0x0E64)
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/* AVI bit definition */
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#define HDMI_AVI_CON_DO_NOT_TRANSMIT (0 << 1)
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#define HDMI_AVI_CON_EVERY_VSYNC (1 << 1)
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#define AVI_ACTIVE_FORMAT_VALID (1 << 4)
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#define AVI_UNDERSCANNED_DISPLAY_VALID (1 << 1)
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/* AUI bit definition */
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#define HDMI_AUI_CON_NO_TRAN (0 << 0)
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/* VSI bit definition */
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#define HDMI_VSI_CON_DO_NOT_TRANSMIT (0 << 0)
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/* HDCP related registers */
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#define HDMI_HDCP_SHA1(n) HDMI_CORE_BASE(0x7000 + 4 * (n))
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#define HDMI_HDCP_KSV_LIST(n) HDMI_CORE_BASE(0x7050 + 4 * (n))
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