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MIPS: mm: Add MIPS R6 instruction encodings
MIPS R6 defines new opcodes for ll, sc, cache and pref instructions so we need to take these into consideration in the micro-assembler. Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
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51eec48e12
commit
a168b8f1cd
2 changed files with 38 additions and 3 deletions
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@ -83,9 +83,12 @@ enum spec3_op {
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swe_op = 0x1f, bshfl_op = 0x20,
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swle_op = 0x21, swre_op = 0x22,
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prefe_op = 0x23, dbshfl_op = 0x24,
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lbue_op = 0x28, lhue_op = 0x29,
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lbe_op = 0x2c, lhe_op = 0x2d,
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lle_op = 0x2e, lwe_op = 0x2f,
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cache6_op = 0x25, sc6_op = 0x26,
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scd6_op = 0x27, lbue_op = 0x28,
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lhue_op = 0x29, lbe_op = 0x2c,
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lhe_op = 0x2d, lle_op = 0x2e,
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lwe_op = 0x2f, pref6_op = 0x35,
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ll6_op = 0x36, lld6_op = 0x37,
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rdhwr_op = 0x3b
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};
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@ -38,6 +38,14 @@
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| (e) << RE_SH \
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| (f) << FUNC_SH)
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/* This macro sets the non-variable bits of an R6 instruction. */
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#define M6(a, b, c, d, e) \
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((a) << OP_SH \
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| (b) << RS_SH \
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| (c) << RT_SH \
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| (d) << SIMM9_SH \
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| (e) << FUNC_SH)
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/* Define these when we are not the ISA the kernel is being compiled with. */
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#ifdef CONFIG_CPU_MICROMIPS
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#define CL_uasm_i_b(buf, off) ISAOPC(_beq)(buf, 0, 0, off)
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@ -62,7 +70,11 @@ static struct insn insn_table[] = {
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{ insn_bltzl, M(bcond_op, 0, bltzl_op, 0, 0, 0), RS | BIMM },
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{ insn_bltz, M(bcond_op, 0, bltz_op, 0, 0, 0), RS | BIMM },
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{ insn_bne, M(bne_op, 0, 0, 0, 0, 0), RS | RT | BIMM },
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#ifndef CONFIG_CPU_MIPSR6
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{ insn_cache, M(cache_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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#else
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{ insn_cache, M6(cache_op, 0, 0, 0, cache6_op), RS | RT | SIMM9 },
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#endif
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{ insn_daddiu, M(daddiu_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_daddu, M(spec_op, 0, 0, 0, 0, daddu_op), RS | RT | RD },
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{ insn_dinsm, M(spec3_op, 0, 0, 0, 0, dinsm_op), RS | RT | RD | RE },
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@ -85,13 +97,22 @@ static struct insn insn_table[] = {
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{ insn_jal, M(jal_op, 0, 0, 0, 0, 0), JIMM },
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{ insn_jalr, M(spec_op, 0, 0, 0, 0, jalr_op), RS | RD },
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{ insn_j, M(j_op, 0, 0, 0, 0, 0), JIMM },
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#ifndef CONFIG_CPU_MIPSR6
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{ insn_jr, M(spec_op, 0, 0, 0, 0, jr_op), RS },
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#else
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{ insn_jr, M(spec_op, 0, 0, 0, 0, jalr_op), RS },
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#endif
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{ insn_lb, M(lb_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_ld, M(ld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_ldx, M(spec3_op, 0, 0, 0, ldx_op, lx_op), RS | RT | RD },
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{ insn_lh, M(lh_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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#ifndef CONFIG_CPU_MIPSR6
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{ insn_lld, M(lld_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_ll, M(ll_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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#else
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{ insn_lld, M6(spec3_op, 0, 0, 0, lld6_op), RS | RT | SIMM9 },
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{ insn_ll, M6(spec3_op, 0, 0, 0, ll6_op), RS | RT | SIMM9 },
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#endif
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{ insn_lui, M(lui_op, 0, 0, 0, 0, 0), RT | SIMM },
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{ insn_lw, M(lw_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
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@ -104,11 +125,20 @@ static struct insn insn_table[] = {
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{ insn_mul, M(spec2_op, 0, 0, 0, 0, mul_op), RS | RT | RD},
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{ insn_ori, M(ori_op, 0, 0, 0, 0, 0), RS | RT | UIMM },
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{ insn_or, M(spec_op, 0, 0, 0, 0, or_op), RS | RT | RD },
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#ifndef CONFIG_CPU_MIPSR6
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{ insn_pref, M(pref_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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#else
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{ insn_pref, M6(spec3_op, 0, 0, 0, pref6_op), RS | RT | SIMM9 },
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#endif
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{ insn_rfe, M(cop0_op, cop_op, 0, 0, 0, rfe_op), 0 },
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{ insn_rotr, M(spec_op, 1, 0, 0, 0, srl_op), RT | RD | RE },
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#ifndef CONFIG_CPU_MIPSR6
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{ insn_scd, M(scd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sc, M(sc_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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#else
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{ insn_scd, M6(spec3_op, 0, 0, 0, scd6_op), RS | RT | SIMM9 },
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{ insn_sc, M6(spec3_op, 0, 0, 0, sc6_op), RS | RT | SIMM9 },
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#endif
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{ insn_sd, M(sd_op, 0, 0, 0, 0, 0), RS | RT | SIMM },
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{ insn_sll, M(spec_op, 0, 0, 0, 0, sll_op), RT | RD | RE },
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{ insn_sllv, M(spec_op, 0, 0, 0, 0, sllv_op), RS | RT | RD },
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@ -198,6 +228,8 @@ static void build_insn(u32 **buf, enum opcode opc, ...)
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op |= build_set(va_arg(ap, u32));
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if (ip->fields & SCIMM)
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op |= build_scimm(va_arg(ap, u32));
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if (ip->fields & SIMM9)
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op |= build_scimm9(va_arg(ap, u32));
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va_end(ap);
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**buf = op;
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