mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-11-01 17:08:10 +00:00
MIPS: Alchemy: fold mach-db1xxx/db1x00 headers into board code
Merge the db1200.h and db1300.h headers into their only users. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> Cc: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/6660/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Manuel Lauss
Ralf Baechle
parent
970e268d6e
commit
a16afa5327
4 changed files with 80 additions and 133 deletions
|
|
@ -38,13 +38,59 @@
|
|||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-au1x00/au1100_mmc.h>
|
||||
#include <asm/mach-au1x00/au1xxx_dbdma.h>
|
||||
#include <asm/mach-au1x00/au1xxx_psc.h>
|
||||
#include <asm/mach-au1x00/au1200fb.h>
|
||||
#include <asm/mach-au1x00/au1550_spi.h>
|
||||
#include <asm/mach-db1x00/bcsr.h>
|
||||
#include <asm/mach-db1x00/db1200.h>
|
||||
|
||||
#include "platform.h"
|
||||
|
||||
#define BCSR_INT_IDE 0x0001
|
||||
#define BCSR_INT_ETH 0x0002
|
||||
#define BCSR_INT_PC0 0x0004
|
||||
#define BCSR_INT_PC0STSCHG 0x0008
|
||||
#define BCSR_INT_PC1 0x0010
|
||||
#define BCSR_INT_PC1STSCHG 0x0020
|
||||
#define BCSR_INT_DC 0x0040
|
||||
#define BCSR_INT_FLASHBUSY 0x0080
|
||||
#define BCSR_INT_PC0INSERT 0x0100
|
||||
#define BCSR_INT_PC0EJECT 0x0200
|
||||
#define BCSR_INT_PC1INSERT 0x0400
|
||||
#define BCSR_INT_PC1EJECT 0x0800
|
||||
#define BCSR_INT_SD0INSERT 0x1000
|
||||
#define BCSR_INT_SD0EJECT 0x2000
|
||||
#define BCSR_INT_SD1INSERT 0x4000
|
||||
#define BCSR_INT_SD1EJECT 0x8000
|
||||
|
||||
#define DB1200_IDE_PHYS_ADDR 0x18800000
|
||||
#define DB1200_IDE_REG_SHIFT 5
|
||||
#define DB1200_IDE_PHYS_LEN (16 << DB1200_IDE_REG_SHIFT)
|
||||
#define DB1200_ETH_PHYS_ADDR 0x19000300
|
||||
#define DB1200_NAND_PHYS_ADDR 0x20000000
|
||||
|
||||
#define PB1200_IDE_PHYS_ADDR 0x0C800000
|
||||
#define PB1200_ETH_PHYS_ADDR 0x0D000300
|
||||
#define PB1200_NAND_PHYS_ADDR 0x1C000000
|
||||
|
||||
#define DB1200_INT_BEGIN (AU1000_MAX_INTR + 1)
|
||||
#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
|
||||
#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
|
||||
#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
|
||||
#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
|
||||
#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
|
||||
#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
|
||||
#define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
|
||||
#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
|
||||
#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
|
||||
#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
|
||||
#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
|
||||
#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
|
||||
#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
|
||||
#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
|
||||
#define PB1200_SD1_INSERT_INT (DB1200_INT_BEGIN + 14)
|
||||
#define PB1200_SD1_EJECT_INT (DB1200_INT_BEGIN + 15)
|
||||
#define DB1200_INT_END (DB1200_INT_BEGIN + 15)
|
||||
|
||||
const char *get_system_type(void);
|
||||
|
||||
static int __init db1200_detect_board(void)
|
||||
|
|
|
|||
|
|
@ -26,12 +26,44 @@
|
|||
#include <asm/mach-au1x00/au1200fb.h>
|
||||
#include <asm/mach-au1x00/au1xxx_dbdma.h>
|
||||
#include <asm/mach-au1x00/au1xxx_psc.h>
|
||||
#include <asm/mach-db1x00/db1300.h>
|
||||
#include <asm/mach-db1x00/bcsr.h>
|
||||
#include <asm/mach-au1x00/prom.h>
|
||||
|
||||
#include "platform.h"
|
||||
|
||||
/* FPGA (external mux) interrupt sources */
|
||||
#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
|
||||
#define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
|
||||
#define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
|
||||
#define DB1300_CF_INT (DB1300_FIRST_INT + 2)
|
||||
#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
|
||||
#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
|
||||
#define DB1300_DC_INT (DB1300_FIRST_INT + 6)
|
||||
#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
|
||||
#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
|
||||
#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
|
||||
#define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
|
||||
#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
|
||||
#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
|
||||
#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
|
||||
#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
|
||||
#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
|
||||
#define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
|
||||
|
||||
/* SMSC9210 CS */
|
||||
#define DB1300_ETH_PHYS_ADDR 0x19000000
|
||||
#define DB1300_ETH_PHYS_END 0x197fffff
|
||||
|
||||
/* ATA CS */
|
||||
#define DB1300_IDE_PHYS_ADDR 0x18800000
|
||||
#define DB1300_IDE_REG_SHIFT 5
|
||||
#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
|
||||
|
||||
/* NAND CS */
|
||||
#define DB1300_NAND_PHYS_ADDR 0x20000000
|
||||
#define DB1300_NAND_PHYS_END 0x20000fff
|
||||
|
||||
|
||||
static struct i2c_board_info db1300_i2c_devs[] __initdata = {
|
||||
{ I2C_BOARD_INFO("wm8731", 0x1b), }, /* I2S audio codec */
|
||||
{ I2C_BOARD_INFO("ne1619", 0x2d), }, /* adm1025-compat hwmon */
|
||||
|
|
|
|||
|
|
@ -1,91 +0,0 @@
|
|||
/*
|
||||
* AMD Alchemy DBAu1200 Reference Board
|
||||
* Board register defines.
|
||||
*
|
||||
* ########################################################################
|
||||
*
|
||||
* This program is free software; you can distribute it and/or modify it
|
||||
* under the terms of the GNU General Public License (Version 2) as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
* for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License along
|
||||
* with this program; if not, write to the Free Software Foundation, Inc.,
|
||||
* 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
|
||||
*
|
||||
* ########################################################################
|
||||
*
|
||||
*
|
||||
*/
|
||||
#ifndef __ASM_DB1200_H
|
||||
#define __ASM_DB1200_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-au1x00/au1xxx_psc.h>
|
||||
|
||||
/* Bit positions for the different interrupt sources */
|
||||
#define BCSR_INT_IDE 0x0001
|
||||
#define BCSR_INT_ETH 0x0002
|
||||
#define BCSR_INT_PC0 0x0004
|
||||
#define BCSR_INT_PC0STSCHG 0x0008
|
||||
#define BCSR_INT_PC1 0x0010
|
||||
#define BCSR_INT_PC1STSCHG 0x0020
|
||||
#define BCSR_INT_DC 0x0040
|
||||
#define BCSR_INT_FLASHBUSY 0x0080
|
||||
#define BCSR_INT_PC0INSERT 0x0100
|
||||
#define BCSR_INT_PC0EJECT 0x0200
|
||||
#define BCSR_INT_PC1INSERT 0x0400
|
||||
#define BCSR_INT_PC1EJECT 0x0800
|
||||
#define BCSR_INT_SD0INSERT 0x1000
|
||||
#define BCSR_INT_SD0EJECT 0x2000
|
||||
#define BCSR_INT_SD1INSERT 0x4000
|
||||
#define BCSR_INT_SD1EJECT 0x8000
|
||||
|
||||
#define IDE_REG_SHIFT 5
|
||||
|
||||
#define DB1200_IDE_PHYS_ADDR 0x18800000
|
||||
#define DB1200_IDE_PHYS_LEN (16 << IDE_REG_SHIFT)
|
||||
#define DB1200_ETH_PHYS_ADDR 0x19000300
|
||||
#define DB1200_NAND_PHYS_ADDR 0x20000000
|
||||
|
||||
#define PB1200_IDE_PHYS_ADDR 0x0C800000
|
||||
#define PB1200_ETH_PHYS_ADDR 0x0D000300
|
||||
#define PB1200_NAND_PHYS_ADDR 0x1C000000
|
||||
|
||||
/*
|
||||
* External Interrupts for DBAu1200 as of 8/6/2004.
|
||||
* Bit positions in the CPLD registers can be calculated by taking
|
||||
* the interrupt define and subtracting the DB1200_INT_BEGIN value.
|
||||
*
|
||||
* Example: IDE bis pos is = 64 - 64
|
||||
* ETH bit pos is = 65 - 64
|
||||
*/
|
||||
enum external_db1200_ints {
|
||||
DB1200_INT_BEGIN = AU1000_MAX_INTR + 1,
|
||||
|
||||
DB1200_IDE_INT = DB1200_INT_BEGIN,
|
||||
DB1200_ETH_INT,
|
||||
DB1200_PC0_INT,
|
||||
DB1200_PC0_STSCHG_INT,
|
||||
DB1200_PC1_INT,
|
||||
DB1200_PC1_STSCHG_INT,
|
||||
DB1200_DC_INT,
|
||||
DB1200_FLASHBUSY_INT,
|
||||
DB1200_PC0_INSERT_INT,
|
||||
DB1200_PC0_EJECT_INT,
|
||||
DB1200_PC1_INSERT_INT,
|
||||
DB1200_PC1_EJECT_INT,
|
||||
DB1200_SD0_INSERT_INT,
|
||||
DB1200_SD0_EJECT_INT,
|
||||
PB1200_SD1_INSERT_INT,
|
||||
PB1200_SD1_EJECT_INT,
|
||||
|
||||
DB1200_INT_END = DB1200_INT_BEGIN + 15,
|
||||
};
|
||||
|
||||
#endif /* __ASM_DB1200_H */
|
||||
|
|
@ -1,40 +0,0 @@
|
|||
/*
|
||||
* NetLogic DB1300 board constants
|
||||
*/
|
||||
|
||||
#ifndef _DB1300_H_
|
||||
#define _DB1300_H_
|
||||
|
||||
/* FPGA (external mux) interrupt sources */
|
||||
#define DB1300_FIRST_INT (ALCHEMY_GPIC_INT_LAST + 1)
|
||||
#define DB1300_IDE_INT (DB1300_FIRST_INT + 0)
|
||||
#define DB1300_ETH_INT (DB1300_FIRST_INT + 1)
|
||||
#define DB1300_CF_INT (DB1300_FIRST_INT + 2)
|
||||
#define DB1300_VIDEO_INT (DB1300_FIRST_INT + 4)
|
||||
#define DB1300_HDMI_INT (DB1300_FIRST_INT + 5)
|
||||
#define DB1300_DC_INT (DB1300_FIRST_INT + 6)
|
||||
#define DB1300_FLASH_INT (DB1300_FIRST_INT + 7)
|
||||
#define DB1300_CF_INSERT_INT (DB1300_FIRST_INT + 8)
|
||||
#define DB1300_CF_EJECT_INT (DB1300_FIRST_INT + 9)
|
||||
#define DB1300_AC97_INT (DB1300_FIRST_INT + 10)
|
||||
#define DB1300_AC97_PEN_INT (DB1300_FIRST_INT + 11)
|
||||
#define DB1300_SD1_INSERT_INT (DB1300_FIRST_INT + 12)
|
||||
#define DB1300_SD1_EJECT_INT (DB1300_FIRST_INT + 13)
|
||||
#define DB1300_OTG_VBUS_OC_INT (DB1300_FIRST_INT + 14)
|
||||
#define DB1300_HOST_VBUS_OC_INT (DB1300_FIRST_INT + 15)
|
||||
#define DB1300_LAST_INT (DB1300_FIRST_INT + 15)
|
||||
|
||||
/* SMSC9210 CS */
|
||||
#define DB1300_ETH_PHYS_ADDR 0x19000000
|
||||
#define DB1300_ETH_PHYS_END 0x197fffff
|
||||
|
||||
/* ATA CS */
|
||||
#define DB1300_IDE_PHYS_ADDR 0x18800000
|
||||
#define DB1300_IDE_REG_SHIFT 5
|
||||
#define DB1300_IDE_PHYS_LEN (16 << DB1300_IDE_REG_SHIFT)
|
||||
|
||||
/* NAND CS */
|
||||
#define DB1300_NAND_PHYS_ADDR 0x20000000
|
||||
#define DB1300_NAND_PHYS_END 0x20000fff
|
||||
|
||||
#endif /* _DB1300_H_ */
|
||||
Loading…
Reference in a new issue