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staging: vt6655: Replace VNSvOutPortD with iowrite32

Browse source 
Replace macro VNSvOutPortD with iowrite32 because it replaces
just one line.
The name of macro and the arguments use CamelCase which
is not accepted by checkpatch.pl

Signed-off-by: Philipp Hortmann <philipp.g.hortmann@gmail.com>
Link: https://lore.kernel.org/r/03b6ff0250aa797f45a855ff2fc76f8013f73dc0.1653203927.git.philipp.g.hortmann@gmail.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Philipp Hortmann 2022-05-22 21:49:24 +02:00 committed by Greg Kroah-Hartman
parent d371f5fd4f
commit a18263ebc8
8 changed files with 41 additions and 51 deletions
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2
drivers/staging/vt6655/baseband.c
View file

@ -2013,7 +2013,7 @@ bool bb_vt3253_init(struct vnt_private *priv)
byVT3253B0_AGC4_RFMD2959[ii][0],
byVT3253B0_AGC4_RFMD2959[ii][1]);
VNSvOutPortD(iobase + MAC_REG_ITRTMSET, 0x23);
iowrite32(0x23, iobase + MAC_REG_ITRTMSET);
MACvRegBitsOn(iobase, MAC_REG_PAPEDELAY, BIT(0));
}
priv->abyBBVGA[0] = 0x18;

33
drivers/staging/vt6655/card.c
View file

@ -293,10 +293,8 @@ bool CARDbUpdateTSF(struct vnt_private *priv, unsigned char byRxRate,
qwTSFOffset = CARDqGetTSFOffset(byRxRate, qwBSSTimestamp,
local_tsf);
/* adjust TSF, HW's TSF add TSF Offset reg */
VNSvOutPortD(priv->port_offset + MAC_REG_TSFOFST,
(u32)qwTSFOffset);
VNSvOutPortD(priv->port_offset + MAC_REG_TSFOFST + 4,
(u32)(qwTSFOffset >> 32));
iowrite32((u32)qwTSFOffset, priv->port_offset + MAC_REG_TSFOFST);
iowrite32((u32)(qwTSFOffset >> 32), priv->port_offset + MAC_REG_TSFOFST + 4);
MACvRegBitsOn(priv->port_offset, MAC_REG_TFTCTL,
TFTCTL_TSFSYNCEN);
}
@ -329,9 +327,8 @@ bool CARDbSetBeaconPeriod(struct vnt_private *priv,
iowrite16(wBeaconInterval, priv->port_offset + MAC_REG_BI);
priv->wBeaconInterval = wBeaconInterval;
/* Set NextTBTT */
VNSvOutPortD(priv->port_offset + MAC_REG_NEXTTBTT, (u32)qwNextTBTT);
VNSvOutPortD(priv->port_offset + MAC_REG_NEXTTBTT + 4,
(u32)(qwNextTBTT >> 32));
iowrite32((u32)qwNextTBTT, priv->port_offset + MAC_REG_NEXTTBTT);
iowrite32((u32)(qwNextTBTT >> 32), priv->port_offset + MAC_REG_NEXTTBTT + 4);
MACvRegBitsOn(priv->port_offset, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);
return true;
@ -411,7 +408,7 @@ void CARDvSafeResetTx(struct vnt_private *priv)
MACvSetCurrTXDescAddr(TYPE_AC0DMA, priv, priv->td1_pool_dma);
/* set MAC Beacon TX pointer */
VNSvOutPortD(priv->port_offset + MAC_REG_BCNDMAPTR, priv->tx_beacon_dma);
iowrite32((u32)priv->tx_beacon_dma, priv->port_offset + MAC_REG_BCNDMAPTR);
}
/*
@ -452,8 +449,8 @@ void CARDvSafeResetRx(struct vnt_private *priv)
}
/* set perPkt mode */
VNSvOutPortD(priv->port_offset + MAC_REG_RXDMACTL0, RX_PERPKT);
VNSvOutPortD(priv->port_offset + MAC_REG_RXDMACTL1, RX_PERPKT);
iowrite32(RX_PERPKT, priv->port_offset + MAC_REG_RXDMACTL0);
iowrite32(RX_PERPKT, priv->port_offset + MAC_REG_RXDMACTL1);
/* set MAC RD pointer */
MACvSetCurrRx0DescAddr(priv, priv->rd0_pool_dma);
@ -552,7 +549,7 @@ void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type)
/* swap over to get correct write order */
swap(phy.swap[0], phy.swap[1]);
VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_1, phy.field_write);
iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_1);
/* RSPINF_b_2 */
vnt_get_phy_field(priv, 14,
@ -561,7 +558,7 @@ void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type)
swap(phy.swap[0], phy.swap[1]);
VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_2, phy.field_write);
iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_2);
/* RSPINF_b_5 */
vnt_get_phy_field(priv, 14,
@ -570,7 +567,7 @@ void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type)
swap(phy.swap[0], phy.swap[1]);
VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_5, phy.field_write);
iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_5);
/* RSPINF_b_11 */
vnt_get_phy_field(priv, 14,
@ -579,7 +576,7 @@ void CARDvSetRSPINF(struct vnt_private *priv, u8 bb_type)
swap(phy.swap[0], phy.swap[1]);
VNSvOutPortD(priv->port_offset + MAC_REG_RSPINF_B_11, phy.field_write);
iowrite32(phy.field_write, priv->port_offset + MAC_REG_RSPINF_B_11);
/* RSPINF_a_6 */
s_vCalculateOFDMRParameter(RATE_6M,
@ -798,8 +795,8 @@ void CARDvSetFirstNextTBTT(struct vnt_private *priv,
qwNextTBTT = CARDqGetNextTBTT(qwNextTBTT, wBeaconInterval);
/* Set NextTBTT */
VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwNextTBTT);
VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwNextTBTT >> 32));
iowrite32((u32)qwNextTBTT, iobase + MAC_REG_NEXTTBTT);
iowrite32((u32)(qwNextTBTT >> 32), iobase + MAC_REG_NEXTTBTT + 4);
MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);
}
@ -824,8 +821,8 @@ void CARDvUpdateNextTBTT(struct vnt_private *priv, u64 qwTSF,
qwTSF = CARDqGetNextTBTT(qwTSF, wBeaconInterval);
/* Set NextTBTT */
VNSvOutPortD(iobase + MAC_REG_NEXTTBTT, (u32)qwTSF);
VNSvOutPortD(iobase + MAC_REG_NEXTTBTT + 4, (u32)(qwTSF >> 32));
iowrite32((u32)qwTSF, iobase + MAC_REG_NEXTTBTT);
iowrite32((u32)(qwTSF >> 32), iobase + MAC_REG_NEXTTBTT + 4);
MACvRegBitsOn(iobase, MAC_REG_TFTCTL, TFTCTL_TBTTSYNCEN);
pr_debug("Card:Update Next TBTT[%8llx]\n", qwTSF);
}

22
drivers/staging/vt6655/device_main.c
View file

@ -1055,7 +1055,7 @@ static void vnt_interrupt_process(struct vnt_private *priv)
* update ISR counter
*/
while (isr && priv->vif) {
VNSvOutPortD(priv->port_offset + MAC_REG_ISR, isr);
iowrite32(isr, priv->port_offset + MAC_REG_ISR);
if (isr & ISR_FETALERR) {
pr_debug(" ISR_FETALERR\n");
@ -1134,7 +1134,7 @@ static void vnt_interrupt_work(struct work_struct *work)
if (priv->vif)
vnt_interrupt_process(priv);
VNSvOutPortD(priv->port_offset + MAC_REG_IMR, IMR_MASK_VALUE);
iowrite32(IMR_MASK_VALUE, priv->port_offset + MAC_REG_IMR);
}
static irqreturn_t vnt_interrupt(int irq, void *arg)
@ -1143,7 +1143,7 @@ static irqreturn_t vnt_interrupt(int irq, void *arg)
schedule_work(&priv->interrupt_work);
VNSvOutPortD(priv->port_offset + MAC_REG_IMR, 0);
iowrite32(0, priv->port_offset + MAC_REG_IMR);
return IRQ_HANDLED;
}
@ -1253,7 +1253,7 @@ static int vnt_start(struct ieee80211_hw *hw)
device_init_registers(priv);
dev_dbg(&priv->pcid->dev, "enable MAC interrupt\n");
VNSvOutPortD(priv->port_offset + MAC_REG_IMR, IMR_MASK_VALUE);
iowrite32(IMR_MASK_VALUE, priv->port_offset + MAC_REG_IMR);
ieee80211_wake_queues(hw);
@ -1522,20 +1522,16 @@ static void vnt_configure(struct ieee80211_hw *hw,
if (priv->mc_list_count > 2) {
MACvSelectPage1(priv->port_offset);
VNSvOutPortD(priv->port_offset +
MAC_REG_MAR0, 0xffffffff);
VNSvOutPortD(priv->port_offset +
MAC_REG_MAR0 + 4, 0xffffffff);
iowrite32(0xffffffff, priv->port_offset + MAC_REG_MAR0);
iowrite32(0xffffffff, priv->port_offset + MAC_REG_MAR0 + 4);
MACvSelectPage0(priv->port_offset);
} else {
MACvSelectPage1(priv->port_offset);
VNSvOutPortD(priv->port_offset +
MAC_REG_MAR0, (u32)multicast);
VNSvOutPortD(priv->port_offset +
MAC_REG_MAR0 + 4,
(u32)(multicast >> 32));
iowrite32((u32)multicast, priv->port_offset + MAC_REG_MAR0);
iowrite32((u32)(multicast >> 32),
priv->port_offset + MAC_REG_MAR0 + 4);
MACvSelectPage0(priv->port_offset);
}

2
drivers/staging/vt6655/mac.c
View file

@ -458,7 +458,7 @@ bool MACbShutdown(struct vnt_private *priv)
{
void __iomem *io_base = priv->port_offset;
/* disable MAC IMR */
VNSvOutPortD(io_base + MAC_REG_IMR, 0);
iowrite32(0, io_base + MAC_REG_IMR);
MACvSetLoopbackMode(priv, MAC_LB_INTERNAL);
/* stop the adapter */
if (!MACbSafeStop(priv)) {

26
drivers/staging/vt6655/mac.h
View file

@ -594,9 +594,9 @@ do { \
unsigned long dwData; \
dwData = ioread32(iobase + MAC_REG_RXDMACTL0); \
if (dwData & DMACTL_RUN) \
VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL0); \
else \
VNSvOutPortD(iobase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL0); \
} while (0)
#define MACvReceive1(iobase) \
@ -604,9 +604,9 @@ do { \
unsigned long dwData; \
dwData = ioread32(iobase + MAC_REG_RXDMACTL1); \
if (dwData & DMACTL_RUN) \
VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
iowrite32(DMACTL_WAKE, iobase + MAC_REG_RXDMACTL1); \
else \
VNSvOutPortD(iobase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
iowrite32(DMACTL_RUN, iobase + MAC_REG_RXDMACTL1); \
} while (0)
#define MACvTransmit0(iobase) \
@ -614,9 +614,9 @@ do { \
unsigned long dwData; \
dwData = ioread32(iobase + MAC_REG_TXDMACTL0); \
if (dwData & DMACTL_RUN) \
VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
iowrite32(DMACTL_WAKE, iobase + MAC_REG_TXDMACTL0); \
else \
VNSvOutPortD(iobase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
iowrite32(DMACTL_RUN, iobase + MAC_REG_TXDMACTL0); \
} while (0)
#define MACvTransmitAC0(iobase) \
@ -624,9 +624,9 @@ do { \
unsigned long dwData; \
dwData = ioread32(iobase + MAC_REG_AC0DMACTL); \
if (dwData & DMACTL_RUN) \
VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
iowrite32(DMACTL_WAKE, iobase + MAC_REG_AC0DMACTL); \
else \
VNSvOutPortD(iobase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
iowrite32(DMACTL_RUN, iobase + MAC_REG_AC0DMACTL); \
} while (0)
#define MACvClearStckDS(iobase) \
@ -648,7 +648,7 @@ do { \
unsigned long dwOrgValue; \
dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
dwOrgValue = dwOrgValue | ENCFG_PROTECTMD; \
VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
} while (0)
#define MACvDisableProtectMD(iobase) \
@ -656,7 +656,7 @@ do { \
unsigned long dwOrgValue; \
dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
dwOrgValue = dwOrgValue & ~ENCFG_PROTECTMD; \
VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
} while (0)
#define MACvEnableBarkerPreambleMd(iobase) \
@ -664,7 +664,7 @@ do { \
unsigned long dwOrgValue; \
dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
dwOrgValue = dwOrgValue | ENCFG_BARKERPREAM; \
VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
} while (0)
#define MACvDisableBarkerPreambleMd(iobase) \
@ -672,7 +672,7 @@ do { \
unsigned long dwOrgValue; \
dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
dwOrgValue = dwOrgValue & ~ENCFG_BARKERPREAM; \
VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
} while (0)
#define MACvSetBBType(iobase, byTyp) \
@ -681,7 +681,7 @@ do { \
dwOrgValue = ioread32(iobase + MAC_REG_ENCFG); \
dwOrgValue = dwOrgValue & ~ENCFG_BBTYPE_MASK; \
dwOrgValue = dwOrgValue | (unsigned long)byTyp; \
VNSvOutPortD(iobase + MAC_REG_ENCFG, dwOrgValue); \
iowrite32((u32)dwOrgValue, iobase + MAC_REG_ENCFG); \
} while (0)
#define MACvSetRFLE_LatchBase(iobase) \

2
drivers/staging/vt6655/rf.c
View file

@ -171,7 +171,7 @@ bool IFRFbWriteEmbedded(struct vnt_private *priv, unsigned long dwData)
unsigned short ww;
unsigned long dwValue;
VNSvOutPortD(iobase + MAC_REG_IFREGCTL, dwData);
iowrite32((u32)dwData, iobase + MAC_REG_IFREGCTL);
/* W_MAX_TIMEOUT is the timeout period */
for (ww = 0; ww < W_MAX_TIMEOUT; ww++) {

2
drivers/staging/vt6655/rxtx.c
View file

@ -1420,7 +1420,7 @@ static int vnt_beacon_xmit(struct vnt_private *priv,
priv->wBCNBufLen = sizeof(*short_head) + skb->len;
VNSvOutPortD(priv->port_offset + MAC_REG_BCNDMAPTR, priv->tx_beacon_dma);
iowrite32((u32)priv->tx_beacon_dma, priv->port_offset + MAC_REG_BCNDMAPTR);
iowrite16(priv->wBCNBufLen, priv->port_offset + MAC_REG_BCNDMACTL + 2);
/* Set auto Transmit on */

3
drivers/staging/vt6655/upc.h
View file

@ -20,9 +20,6 @@
/* For memory mapped IO */
#define VNSvOutPortD(dwIOAddress, dwData) \
iowrite32((u32)(dwData), dwIOAddress)
/*--------------------- Export Classes ----------------------------*/
/*--------------------- Export Variables --------------------------*/