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drm/i915: Remove lrc default desc from GEM context
We only compute the lrc_descriptor() on pinning the context, i.e. infrequently, so we do not benefit from storing the template as the addressing mode is also fixed for the lifetime of the intel_context. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com> Acked-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190730133035.1977-9-chris@chris-wilson.co.uk
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parent
8ef7e3409c
commit
a1c9ca223c
4 changed files with 10 additions and 35 deletions
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@ -397,30 +397,6 @@ static void context_close(struct i915_gem_context *ctx)
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i915_gem_context_put(ctx);
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}
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static u32 default_desc_template(const struct drm_i915_private *i915,
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const struct i915_address_space *vm)
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{
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u32 address_mode;
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u32 desc;
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desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
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address_mode = INTEL_LEGACY_32B_CONTEXT;
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if (vm && i915_vm_is_4lvl(vm))
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address_mode = INTEL_LEGACY_64B_CONTEXT;
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desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
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if (IS_GEN(i915, 8))
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desc |= GEN8_CTX_L3LLC_COHERENT;
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/* TODO: WaDisableLiteRestore when we start using semaphore
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* signalling between Command Streamers
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* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE;
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*/
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return desc;
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}
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static struct i915_gem_context *
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__create_context(struct drm_i915_private *i915)
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{
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@ -459,7 +435,6 @@ __create_context(struct drm_i915_private *i915)
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i915_gem_context_set_recoverable(ctx);
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ctx->ring_size = 4 * PAGE_SIZE;
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ctx->desc_template = default_desc_template(i915, NULL);
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for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp); i++)
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ctx->hang_timestamp[i] = jiffies - CONTEXT_FAST_HANG_JIFFIES;
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@ -478,8 +453,9 @@ __set_ppgtt(struct i915_gem_context *ctx, struct i915_address_space *vm)
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struct i915_gem_engines_iter it;
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struct intel_context *ce;
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GEM_BUG_ON(old && i915_vm_is_4lvl(vm) != i915_vm_is_4lvl(old));
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ctx->vm = i915_vm_get(vm);
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ctx->desc_template = default_desc_template(ctx->i915, vm);
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for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
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i915_vm_put(ce->vm);
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@ -171,8 +171,6 @@ struct i915_gem_context {
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/** ring_size: size for allocating the per-engine ring buffer */
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u32 ring_size;
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/** desc_template: invariant fields for the HW context descriptor */
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u32 desc_template;
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/** guilty_count: How many times this context has caused a GPU hang. */
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atomic_t guilty_count;
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@ -417,13 +417,17 @@ lrc_descriptor(struct intel_context *ce, struct intel_engine_cs *engine)
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BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (BIT(GEN8_CTX_ID_WIDTH)));
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BUILD_BUG_ON(GEN11_MAX_CONTEXT_HW_ID > (BIT(GEN11_SW_CTX_ID_WIDTH)));
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desc = ctx->desc_template; /* bits 0-11 */
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GEM_BUG_ON(desc & GENMASK_ULL(63, 12));
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desc = INTEL_LEGACY_32B_CONTEXT;
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if (i915_vm_is_4lvl(ce->vm))
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desc = INTEL_LEGACY_64B_CONTEXT;
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desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
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desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
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if (IS_GEN(engine->i915, 8))
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desc |= GEN8_CTX_L3LLC_COHERENT;
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desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE;
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/* bits 12-31 */
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GEM_BUG_ON(desc & GENMASK_ULL(63, 32));
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/*
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* The following 32bits are copied into the OA reports (dword 2).
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* Consider updating oa_get_render_ctx_id in i915_perf.c when changing
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@ -291,9 +291,6 @@ shadow_context_descriptor_update(struct intel_context *ce,
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* Update bits 0-11 of the context descriptor which includes flags
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* like GEN8_CTX_* cached in desc_template
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*/
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desc &= U64_MAX << 12;
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desc |= ce->gem_context->desc_template & ((1ULL << 12) - 1);
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desc &= ~(0x3 << GEN8_CTX_ADDRESSING_MODE_SHIFT);
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desc |= workload->ctx_desc.addressing_mode <<
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GEN8_CTX_ADDRESSING_MODE_SHIFT;
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