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drm/i915: Use standard form terminating condition for lane for loops
Use <4 instead of <=3 as the terminating condition for the loops over the 4 lanes. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20211006204937.30774-4-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
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1 changed files with 2 additions and 2 deletions
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@ -1067,7 +1067,7 @@ static void icl_ddi_combo_vswing_program(struct intel_encoder *encoder,
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/* Program PORT_TX_DW4 */
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/* We cannot write to GRP. It would overwrite individual loadgen. */
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for (ln = 0; ln <= 3; ln++) {
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for (ln = 0; ln < 4; ln++) {
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val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
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val &= ~(POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
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CURSOR_COEFF_MASK);
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@ -1114,7 +1114,7 @@ static void icl_combo_phy_set_signal_levels(struct intel_encoder *encoder,
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* <= 6 GHz and 1,2 lanes (LN0=0, LN1=1, LN2=1, LN3=0)
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* > 6 GHz (LN0=0, LN1=0, LN2=0, LN3=0)
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*/
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for (ln = 0; ln <= 3; ln++) {
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for (ln = 0; ln < 4; ln++) {
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val = intel_de_read(dev_priv, ICL_PORT_TX_DW4_LN(ln, phy));
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val &= ~LOADGEN_SELECT;
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