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PCI: cadence: Allow PTM Responder to be enabled
This enables the Controller [RP] to automatically respond with Response/ResponseD messages if CDNS_PCIE_LM_TPM_CTRL_PTMRSEN and PCI_PTM_CTRL_ENABLE bits are both set. Link: https://lore.kernel.org/r/20220512055539.1782437-1-christian.gmeiner@gmail.com Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
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2 changed files with 14 additions and 0 deletions
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@ -123,6 +123,14 @@ static int cdns_pcie_retrain(struct cdns_pcie *pcie)
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return ret;
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}
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static void cdns_pcie_host_enable_ptm_response(struct cdns_pcie *pcie)
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{
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u32 val;
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val = cdns_pcie_readl(pcie, CDNS_PCIE_LM_PTM_CTRL);
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cdns_pcie_writel(pcie, CDNS_PCIE_LM_PTM_CTRL, val | CDNS_PCIE_LM_TPM_CTRL_PTMRSEN);
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}
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static int cdns_pcie_host_start_link(struct cdns_pcie_rc *rc)
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{
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struct cdns_pcie *pcie = &rc->pcie;
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@ -501,6 +509,8 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc)
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if (rc->quirk_detect_quiet_flag)
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cdns_pcie_detect_quiet_min_delay_set(&rc->pcie);
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cdns_pcie_host_enable_ptm_response(pcie);
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ret = cdns_pcie_start_link(pcie);
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if (ret) {
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dev_err(dev, "Failed to start link\n");
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@ -116,6 +116,10 @@
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#define LM_RC_BAR_CFG_APERTURE(bar, aperture) \
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(((aperture) - 2) << ((bar) * 8))
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/* PTM Control Register */
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#define CDNS_PCIE_LM_PTM_CTRL (CDNS_PCIE_LM_BASE + 0x0da8)
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#define CDNS_PCIE_LM_TPM_CTRL_PTMRSEN BIT(17)
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/*
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* Endpoint Function Registers (PCI configuration space for endpoint functions)
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*/
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